ACPM-7821 4 x 4 Power Amplifier Module for J-CDMA (898 – 925 MHz) Data Sheet Description Features The ACPM-7821 is a CDMA (Code Division Multiple Access) power amplifier module designed for handsets operating in the 898–925MHz bandwidth. The ACPM-7821 meets stringent CDMA linearity requirements up to 28 dBm output power. • Excellent linearity A low current (Vcont) pin is provided for high efficiency improvement of the low output power range. The ACPM-7821 features CoolPAM circuit technology offering state-of-the-art reliability, temperature stability and ruggedness. ACPM-7821 is self contained, incorporating 50 ohm input and output matching networks. • High efficiency • 10-pin surface mounting package (4 mm x 4 mm x 1.1 mm) • Low quiescent current • Internal 50Ω matching networks for both RF input and output • CDMA 95A/B, CDMA2000-1X/EVDO Applications • Digital Cellular (J-CDMA) Functional Block Diagram Vref(1) Vcont(2) Bias Circuit & Control Logic Input Match RF Input (4) Inter Stage Match DA Output Match PA RF Output (8) MMIC MODULE Vcc1(5) Vcc2(6) Ordering Information Part Number ACPM-7821-TR1 ACPM-7821-BLK No. of Devices Container 1000 100 7" Tape and Reel Bulk Table 1. Absolute Maximum Ratings[1] Parameter Symbol Min. Nominal Max. Unit RF Input Power Pin – – 10.0 dBm DC Supply Voltage Vcc 0 3.4 5.0 V DC Reference Voltage Vref 0 2.85 3.3 V Control Voltage Vcont 0 2.85 3.3 V Storage Temperature Tstg -55 – +125 °C Table 2. Recommended Operating Conditions Parameter Symbol Min. Nominal Max. Unit DC Supply Voltage Vcc 3.2 3.4 4.2 V DC Reference Voltage Vref 2.75 2.85 2.95 V Mode Control Voltage – High Power Mode – Low Power Mode Vcont Vcont – – 0 2.85 – – V V Operating Frequency Fo 898 – 925 MHz Case Operating Temperature To -30 25 85 °C Table 3. Power Range Truth Table Power Mode Symbol Vref Vcont[2] Range High Power Mode PR2 2.85 Low ~ 28 dBm Low Power Mode PR1 2.85 High ~ 17 dBm Shut Down Mode – 0 – – Notes: 1. No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value. 2. High (2.0V – 3.0V), Low (0.0V – 0.5V). 2 Table 4. Electrical Characteristics for CDMA Mode (Vcc=3.4V, Vref=2.85V, T=25°C) Characteristics Symbol Condition Min. Typ. Max. Unit Gain Gain_hi Gain_low Pout = 28.0 dBm Pout = 17 dBm 24 17 27 20 dB dB Power Added Efficiency PAE_hi PAE_low Pout = 28.0 dBm Pout = 17 dBm 37 17 41.2 21.5 % % Total Supply Current Icc_hi Icc_low Pout = 28.0 dBm Pout = 17 dBm 450 68 500 86 mA mA Quiescent Current Iq_hi Iq_low High Power Mode Low Power Mode 85 14 115 22 mA mA Reference Current Iref_hi Iref_low Pout = 28.0 dBm Pout = 17 dBm 4 4.5 7 8 mA mA Control Current[1] Icont Pout = 17 dBm 0.2 1 mA Total Current in Power-down mode Ipd Vref = 0V 0.2 5 µA ACPR in High power mode 0.885 MHz offset ACPR1_hi 1.98 MHz offset ACPR2_hi Pout = 28.0 dBm Pout = 28.0 dBm -53 -60 -46 -57 dBc dBc ACPR in Low power mode 0.885 MHz offset ACPR1_low 1.98 MHz offset ACPR2_low Pout = 17 dBm Pout = 17 dBm -57 -68 -46 -57 dBc dBc Harmonic Suppression Second Third Pout = 28.0 dBm Pout = 28.0 dBm -35 -55 -30 -40 dBc dBc 2:1 2.5:1 VSWR -60 dBc -134 dBm/Hz 10:1 VSWR 2f0 3f0 Input VSWR VSWR Stability (Spurious Output) S VSWR 6:1, All phase Noise Power in Rx Band RxBN Pout = 28.0 dBm Ruggedness (No Damage) Ru Pout < 28.0 dBm, Pin < 10.0 dBm Notes: 1. Control current when series 6.2kohm is used. 2. Characterized with IS-95 modulated signal 3 -136 Characterization Data(Vcc=3.4V, Vref=2.85V, T=25°C) 30 500 450 25 400 350 20 898MHz 910MHz 250 925MHz 200 Gain (dB) Current (mA) 898MHz 300 910MHz 15 925MHz 10 150 100 5 50 0 0 -10 -5 0 5 10 15 20 25 -10 30 -5 0 5 10 Figure 1. Total Current vs. Output Power. 20 25 30 Figure 2. Gain vs. Output Power. -30 45 -35 40 -40 35 30 -45 898MHz -50 910MHz 898MHz 25 910MHz 20 925MHz ACPR1 (dBc) PAE (%) 15 Pout (dBm) Pout (dBm) -55 925MHz -60 15 -65 10 -70 -75 5 -80 0 -10 -10 -5 0 5 10 15 20 25 -5 0 5 10 15 20 25 30 30 Pout (dBm) Pout (dBm) Figure 3. Power Added Efficiency vs. Output Power. -40 -45 -50 -55 ACPR2 (dBc) 898MHz -60 910MHz -65 925MHz -70 -75 -80 -85 -90 -10 -5 0 5 10 15 20 25 30 Pout (dBm) Figure 5. Adjacent Channel Power Ratio 2 vs. Output Power. 4 Figure 4. Adjacent Channel Power Ratio 1 vs. Output Power. Evaluation Board Description Vref 1 Vref C1 100pF Vcont C2 100pF R1 6.2kohm RF In Vcc1 C4 2.2µF C3 22pF C7 68pF 2 Vcont GND 9 3 GND RF Out 8 4 RF In GND 7 5 Vcc1 Vcc2 6 Figure 6. Evaluation Board Schematic. C1 R1 C2 AVAGO ACPM-7821 PYYWW AAAAA C7 C3 C4 C5 C6 Figure 7. Evaluation Board Assembly Diagram. 5 GND 10 RF Out C5 1.5nF C6 Vcc2 2.2µF Package Dimensions and Pin Descriptions Pin 1 Mark 1 10 2 9 3 8 4 7 5 6 1.1± 0.1 TOP VIEW SIDE VIEW 1.9 0.5 0.6 0.85 1.9 4 ± 0.1 4 ± 0.1 1.0 0.85 0.48 1.7 0.4 0.4 Pin # Name Description 1 Vref Reference Voltage 2 Vcont Control Voltage 3 GND Ground 4 RF In RF Input 5 Vcc1 Supply Voltage 6 Vcc2 Supply Voltage 7 GND Ground 8 RF Out RF Output 9 GND Ground 10 GND Ground BOTTOM VIEW Figure 8. Package Dimensional Drawing and Pin Descriptions. 6 PIN DESCRIPTIONS Package Dimensions and Pin Descriptions, continued Pin 1 Mark AVAGO ACPM-7821 Manufacturing Part Number PYYWW Lot Number P Manufacturing info YY Manufacturing Year WW Work Week AAAAA Assembly Lot Number AAAAA Figure 9. Marking Specifications. 7 Peripheral Circuit in Handset +2.85V C8 MSM PA_ON PA_R0 R1 C2 C1 Output Matching Circuit ACPM-7821 Vdd Vref Vcont GND IN Vcc1 RF In RF SAW GND GND OUT GND Vcc2 RF Out C6 Duplexer C7 C3 L1 C4 C5 VBATT Notes: - Recommended voltage for Vref is 2.85V Place C1 near to Vref pin. Place C3 and C4 close to pin 5 (Vcc1) and pin 6 (Vcc2). These capacitors can affect the RF performance Use 50Ω transmission line between PAM and Duplexer and make it as short as possible to reduce conduction loss π-type circuit topology is good to use for matching circuit between PA and Duplexer. Pull-up resistor(R1) should be used to limit current drain. 6.2kΩ is recommended for ACPM-7821 Figure 10. Peripheral Circuit. 8 Calibration power where PA mode changes from high mode to low mode), should be adopted to prevent system oscillation. 3 to 5 dB is recommended for Hysteresis. Calibration procedure is shown in Figure 11. Two calibration tables, high mode and low mode respectively, are required for CoolPAM, which is due to gain difference in each mode. Average Current and Talk Time Probability Distribution Function implies that what is important for longer talk time is the efficiency of low or medium power range rather than the efficiency at full power. ACPM-7821 idle current is 14 mA and operating current at 17 dBm is 68 mA at nominal condition. This PA with low current consumption prolongs talk time by no less than 30 minutes compared to other PAs. For continuous output power at the mode change points, the input power should be adjusted according to gain step during the mode change. Offset Value (difference between rising point and falling point) Offset value, which is the difference between the rising point (output power where PA mode changes from low mode to high mode) and falling point (output Average current = ∫(PDF x Current)dp TX AGC Gain Low mode High Mode High mode Low Mode Min PWR Falling Rising Pout Max PWR Falling Pout Rising Figure 12. Setting of offset between rising and falling power. Figure 11. Calibration procedure. 5.00 700 4.50 CDG Urban 4.00 600 CDG Suburban 500 3.50 3.00 400 2.50 2.00 300 1.50 200 1.00 100 0.50 0.00 0 -50 -40 -30 -20 -10 0 10 20 30 PA Out (dBm) Conv PAM Digitally Controlled PA Figure 13. CDMA Power Distribution Function. 9 Cool PAM PCB Design Guidelines The recommended ACPM-7821 PCB Land pattern is shown in Figure 14 and Figure 15. The substrate is coated with solder mask between the I/O and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. 0.1 0.25 0.85 Stencil Design Guidelines A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The recommended stencil layout is shown in Figure 16. Reducing the stencil opening can potentially generate more voids. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads or conductive paddle to adjacent I/O pads. Considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100 mm (4 mils) or 0.127 mm (5 mils) thick stainless steel which is capable of producing the required fine stencil outline. 0.4 0.7 0.6 Ø 0.3mm on 0.6mm pitch Figure 14. Metallization. 0.8 0.65 0.5 1.8 0.6 0.85 2.0 0.8 x 0.5 0.8 x 0.6 Figure 15. Solder Mask Opening. 0.7 0.6 0.4 1.6 0.85 1.6 Figure 16. Solder Paste Stencil Aperture. 10 Tape Drawing Dimension List Annote Millimeter Annote Millimeter A0 4.40±0.10 P2 2.00±0.05 B0 4.40±0.10 P10 40.00±0.20 K0 1.70±0.10 E 1.75±0.10 D0 1.55±0.05 F 5.50±0.05 D1 1.60±0.10 W 12.00±0.30 P0 4.00±0.10 T 0.30±0.05 P1 8.00±0.10 Figure 17. Tape and Reel Format – 4 mm x 4mm. 11 Reel Drawing BACK VIEW FRONT VIEW Figure 18. Plastic Reel Format –13"/4". 12 Handling and Storage package at various temperatures and relative humidity, and times. After soak, the components are subjected to three consecutive simulated reflows. ESD (Electrostatic Discharge) Electrostatic discharge occurs naturally in the environment. With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, destructive damage will result. ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site. The out of bag exposure time maximum limits are determined by the classification test describe above which corresponds to an MSL classification level 6 to 1 according to the JEDEC standard IPC/JEDEC J-STD-020A and J-STD-033. MSL (Moisture Sensitivity Level) ACPM-7821 is MSL3. Thus, according to the J-STD033 p.11 the maximum Manufacturers Exposure Time (MET) for this part is 168 hours. After this time period, the part would need to be removed from the reel, de-taped and then re-bake. Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. Avago follows JEDEC Standard J-STD 020A. Each component and package type is classified for moisture sensitivity by soaking a known dry MSL classification ref low temperature for the ACPM-7821 is targeted at 250° C +0/-5° C. Figure 19 and Table 7 show typical SMT profile for maximum temperature of 250° C +0/-5° C. Table 5. ESD Classification Pin# All Pins HBM MM CDM Rating Class Rating Class Rating Class ±1000V Class 1C (JESD22-A115-A) ± 200V Class B ± 200V Class II (JESD22-C101C) Note: 1. PA module products should be considered extremely ESD sensitive. Table 6. Moisture Classification Level and Floor Life MSL Level Floor Life (out of bag) at factory ambient ≤ 30°C/60% RH or as stated 1 Unlimited at ≤ 30oC/85% RH 2 1 year 2a 4 weeks 3 168 hours 4 72 hours 5 48 hours 5a 24 hours 6 Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label Note: 1. The MSL Level is marked on the MSL Label on each shipping bag. 13 Handling and Storage, continued Figure 19. Typical SMT Reflow Profile for Maximum Temperature = 250 +0/-5°C. Table 7. Typical SMT Reflow Profile for Maximum Temperature = 250+0/-5°C Profile Feature Sn-Pb Solder Pb-Free Solder Average ramp-up rate (TL to TP) 3°C/sec max 3°C/sec max Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) 100°C 150°C 60–120 sec 100°C 150°C 60–180 sec Tsmax to TL - Ramp-up Rate 3°C/sec max Time maintained above: - Temperature (TL) - Time (TL) 183°C 60–150 sec 217°C 60–150 sec Peak Temperature (Tp) 225 +0/-5°C 250 +0/-5°C Time within 5°C of actual Peak Temperature (tp) 10–30 sec 10–30 sec Ramp-down Rate 6°C/sec max 6°C/sec max Time 25°C to Peak Temperature 6 min max. 8 min max. 14 Handling and Storage, continued Storage Conditions Packages described in this document must be stored in sealed moisture barrier, anti-static bags. Shelf life in a sealed moisture barrier bag is 12 months at <40° C and 90% relative humidity (RH) J-STD-033 p.7. Out-of-Bag Time Duration After unpacking the device must be soldered to the PCB within 168 hours as listed in the J-STD-020B p.11 with factory conditions <30oC and 60% RH. Baking It is not necessary to re-bake the part if both conditions (storage conditions and out-of-bag condition) have been satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are 125°C for 24 hours J-STD-033 p.8. CAUTION: Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be re-reeled, de-taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking) Board Rework Component Removal, Rework and Remount If a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200° C. This method will minimize moisture related component damage. If any component temperature exceeds 200°C, the board must be baked dry per 4-2 prior to rework and/or component removal. Component temperatures shall be measured at the top center of the package body. Any SMD packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature. 15 Removal for Failure Analysis Not following the requirements of 4-1 may cause moisture/reflow damage that could hinder or completely prevent the determination of the original failure mechanism. Baking of Populated Boards Some SMD packages and board materials are not able to withstand long duration bakes at 125° C. Examples of this are some FR-4 materials, which cannot withstand a 24 hr bake at 125°C. Batteries and electrolytic capacitors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the appropriate bake duration based on the component to be removed. For additional considerations see IPC-7711 and IPC-7721. Derating due to Factory Environmental Conditions Factory floor life exposures for SMD packages removed from the dry bags will be a function of the ambient environmental conditions. A safe, yet conservative, handling approach is to expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in Table 6. This approach, however, does not work if the factory humidity or temperature are greater than the testing conditions of 30° C/60% RH. A solution for addressing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component packaging materials (ref. JESD22-A120). Recommended equivalent total floor life exposures can be estimated for a range of humidity’s and temperatures based on the nominal plastic thickness for each device. Table 8 lists equivalent derated floor lives for humidity’s ranging from 20– 90% RH for three temperatures, 20° C, 25° C, and 30° C. This table is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in calculating Table 8: 1. Activation Energy for diffusion = 0.35eV (smallest known value). 2. For ≤60% RH, use Diffusivity = 0.121exp (- 0.35eV/kT) mm2/s (this uses smallest known Diffusivity @ 30° C). 3. For >60% RH, use Diffusivity = 1.320exp (- 0.35eV/kT) mm2/s (this uses largest known Diffusivity @ 30° C). Table 8. Recommended Equivalent Total Floor Life (days) @ 20°C, 25°C & 30°C For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified) For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies, Limited. All rights reserved. Obsoletes 5989-2534EN AV01-0265EN July 10, 2006