AVAGO WS1403-BLK

WS1403
CDMA PCS 3x3 Power Amplifier Module
(1850-1910 MHz)
Data Sheet
Description
Features
The WS1403 is a CDMA Personal Communication Service
(PCS) Power Amplifier (PA), designed for handsets
operating in the 1850~1910 MHz bandwidth.
• Excellent linearity
Digital mode control of CoolPAM reduces current
consumption, which enables extended talk time of
mobile devices.
The WS1403 meets stringent CDMA linearity
requirements to and beyond 28 dBm output power. The
3 mm x 3 mm form factor 8-pin surface mount package
is self contained, incorporating 50 ohm input and output
matching networks.
• Low quiescent current
• High efficiency
PAE at 28 dBm: 39.8%
PAE at 17 dBm: 22.3%
• 8-pin surface mounting package
3 mm x 3 mm x 1.0 mm
• Internal 50 ohm matching networks for both RF input
and output
• RoHS compliant
Applications
• Digital CDMA PCS
• Wireless Local loop
Order Information
Functional Block Diagram
Vref (1)
Part Number
No. of Devices
Container
WS1403-TR1
1,000
7” Tape and Reel
WS1403-BLK
100
BULK
Vcont (2)
MMIC
BIAS CIRCUIT & CONTROL LOGIC
RF
INPUT
(3)
INPUT
MATCH
DA
INTER
STAGE
MATCH
PA
OUTPUT
MATCH
MODULE
Vcc1 (4)
Vcc2 (5)
RF
OUTPUT
(6)
Table 1. Absolute Maximum Ratings[1]
Parameter
Symbol
Min.
Nominal
Max.
Unit
RF Input Power
Pin
–
–
10.0
dBm
DC Supply Voltage
Vcc
0
3.4
5.0
V
Reference Voltage
Vref
0
2.85
3.3
V
Control Voltage
Vcont
0
2.85
3.3
V
Storage Temperature
Tstg
-55
–
+125
°C
Table 2. Recommended Operating Condition
Parameter
Symbol
Min.
Nominal
Max.
Unit
DC Supply Voltage
Vcc
3.2
3.4
4.2
V
DC Reference Voltage
Vref
2.75
2.85
2.95
V
Mode Control Voltage
– High Power Mode
– Low Power Mode
Vcont
Vcont
0
2.0
0
2.85
0.5
3.0
V
V
Operating Frequency
Fo
1850
1910
MHz
Ambient Temperature
Ta
-30
85
°C
25
Table 3. Power Range Truth Table
Power Mode
Symbol
Vref
Vcont[2]
Range
High Power Mode
PR2
2.85
Low
~ 28 dBm
Low Power Mode
PR1
2.85
High
~ 17 dBm
Shut Down Mode
–
0
-
–
Notes:
1. No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value.
2. High (2.0 – 3.0 V), Low (0.0 V – 0.5 V).
Table 4. Electrical Characteristics for CDMA Mode (Vcc = 3.4 V, Vref = 2.85 V, T = 25°C, Zin/Zout = 50 ohm)
Characteristics
Symbol
Operating Frequency Range
F
Condition
Min.
Typ.
Max.
Unit
1850
–
1910
MHz
Gain_hi
High Power Mode, Pout = 28 dBm
24
28
dB
Gain_low
Low Power Mode, Pout = 17 dBm
14
18
dB
PAE_hi
High Power Mode, Pout = 28 dBm
35.6
39.8
%
PAE_ low
Low Power Mode, Pout = 17 dBm
16.1
22.3
%
Icc_hi
High Power Mode, Pout = 28 dBm
465
520
mA
Icc_ low
Low Power Mode, Pout = 17 dBm
65
90
mA
Iq_hi
High Power Mode
91
125
mA
Iq_ low
Low Power Mode
12
22
mA
Iref_hi
High Power Mode, Pout = 28 dBm
2
7
mA
Iref_low
Low Power Mode, Pout = 17 dBm
3.3
8
mA
Control Current
Icont
Low Power Mode, Pout = 17 dBm
0.19
1
mA
Total Current in Power-Down
Mode
Ipd
Vref = 0 V
0.2
5
µA
Adjacent
Channel
Power
Ratio
1.25 MHz offset
ACPR1_hi
High Power Mode, Pout = 28 dBm
-52
-47
dBc
1.98 MHz offset
ACPR2_hi
-59
-56
dBc
1.25 MHz offset
ACPR1_ low
-54
-47
dBc
1.98 MHz offset
ACPR2_ low
-65
-56
dBc
Second
2f0
-40
-33
dBc
Third
3f0
-64
-45
dBc
Input VSWR
VSWR
1.4:1
2.0:1
Stability (Spurious Output)
S
Noise Power in Rx Band
RxBN
Gain
Power Added Efficiency
Total Supply Current
Quiescent Current
Reference Current
Harmonic
Suppression
Ruggedness
Low Power Mode, Pout = 17 dBm
High Power Mode, Pout = 28 dBm
VSWR 6:1, All Phase
-137
No Damage
Pout <28 dBm, Pin <10 dBm, All Phase
High Power Mode
-60
dBc
-133
dBm/Hz
10:1
VSWR
Characteristics Data (Vcc = 3.4 V, Vref = 2.85 V, T = 25°C, Zin/Zout = 50 ohm)
35
500
400
1850 MHz
350
1880 MHz
300
1910 MHz
30
Gain (dB)
Current (mA)
450
250
200
25
20
150
1850 MHz
100
15
1880 MHz
1910 MHz
50
0
0
5
10
15
20
25
10
30
0
5
10
Pout (dBm)
15
20
25
30
Pout (dBm)
Figure 1. Total current vs. output power
Figure 2. Gain vs. output power
45
-40
40
-45
35
-50
ACPR1 (dBc)
PAE (%)
30
25
20
15
10
5
0
-65
1880 MHz
-70
0
5
10
15
20
25
30
1880 MHz
1910 MHz
-60
-65
-70
-75
1850 MHz
1880 MHz
-80
1910 MHz
5
10
15
0
5
10
15
20
Figure 4. Adjacent channel power ratio 1 vs. output power
-55
0
-75
Pout (dBm)
-50
ACPR2 (dBc)
1850 MHz
1910 MHz
Figure 3. Power added efficiency vs. output power
20
Pout (dBm)
Figure 5. Adjacent channel power ratio 2 vs. output power
-60
1850 MHz
Pout (dBm)
-85
-55
25
30
25
30
Evaluation Board Description
Vref
Vcont
R1
0 ohm
C3
100pF
1 Vref
GND 8
2 Vcont
GND 7
3 RF In
RF Out 6
4 Vcc1
Vcc2 5
C4
100pF
RF In
Vcc1
C5
2.2µF
C1
100pF
RF Out
Figure 6. Evaluation board schematic
3
4
1403
PYYWW
AAAAA
Figure 7. Evaluation board assembly diagram
Vcc2
C2
150pF
C6
2.2µF
Package Dimensions and Pin Descriptions
0.60
PIN 1 MARK
1
8
2
7
3 ± 0.1
3
6
4
5
3 ± 0.1
1.0 ± 0.1
TOP VIEW
SIDE VIEW
0.7
0.15 x 45
1.40
PIN DESCRIPTIONS
1.20
1.40
2.80
3.0
0.40
PIN #
NAME
DESCRIPTION
1
Vref
Reference Voltage
2
Vcont
Control Voltage
3
RF In
RF Input
4
Vcc1
Supply Voltage
5
Vcc2
Supply Voltage
6
RF Out
RF Output
7
GND
Ground
8
GND
Ground
0.80
0.40
R 0.10
X-RAY BOTTOM VIEW
0.40
Figure 8. Package dimensional drawing and pin descriptions (all dimensions are in millimeters)
PIN 1 MARK
1403
Manufacturing Part Number
PYYWW
Lot Number
P
YY
WW
AAAAA
AAAAA
Figure 9. Marking specifications
Manufacturing Info
Manufacturing Year
Work Week
Assembly Lot
Peripheral Circuit in Handset
+2.85 V
MSM
C8
PA_ON
PA_RO
C2
C1
WS1403
Vref
RF In
Vcont
TX
FILTER
Output Matching Circuit
GND
GND
RF IN
RF OUT
Vcc1
Vcc2
C6
RF Out
Duplexer
C7
C3
L1
C4
C5
VBATT
Figure 10. Peripheral circuit
Notes:
• Recommended voltage for Vref is 2.85 V.
• Place C1 near to Vref pin.
• Place C3 and C4 close to pin 4 (Vcc1) and pin 5 (Vcc2). These capacitors can affect the RF performance.
• Use 50 W transmission line between PAM and Duplexer and make it as short as possible to reduce conduction loss.
• π-type circuit topology is good to use for matching circuit between PA and Duplexer.
Calibration
Calibration procedure is shown in Figure 11. Two
calibration tables, high mode and low mode respectively,
are required for Cool PAM, which is due to gain difference
in each mode. For continuous output power at the mode
change points, the input power should be adjusted
according to gain step during the mode change.
TX_AGC
Offset Value (Difference between Rising Point and Falling
Point)
Offset value, which is the difference between the rising
point (output power where PA mode changes from low
mode to high mode) and falling point (output power
where PA mode changes from high mode to low mode),
should be adopted to prevent system oscillation. 3 to 5
dB is recommended for hysteresis.
GAIN
Low Mode
High Mode
High Mode
Low Mode
Min. PWR
Falling Rising
Figure 11. Calibration procedure
Pout
Max. PWR
Falling
Rising
Pout
Figure 12. Setting of offset between rising and falling power
5.00
700
3.50
PDF (%)
600
CDG Urban
CDG Suburban
4.00
500
3.00
400
2.50
300
2.00
1.50
CURRENT (mA)
4.50
200
1.00
100
0.50
0
-50
-40
-30
-20
-10
0
10
20
30
0
PA Out (dBm)
Conventional PAM
Digitally Controlled PAM
Cool PAM
Figure 13. CDMA power distribution function
Average Current & Talk Time
Stencil Design Guidelines
Probability Distribution Function implies that what is
important for longer talk time is the efficiency of low
or medium power range rather than the efficiency at
full power. WS1403 idle current is 12 mA and operating
current at 17 dBm is 65 mA at nominal condition. This PA
with low current consumption prolongs talk time by no
less than 30 minutes compared to other PAs.
A properly designed solder screen or stencil is required
to ensure optimum amount of solder paste is deposited
onto the PCB pads.
The recommended stencil layout is shown in Figure 16.
Reducing the stencil opening can potentially generate
more voids. On the other hand, stencil openings larger
than 100% will lead to excessive solder paste smear or
bridging across the I/O pads or conductive paddle to
adjacent I/O pads. Considering the fact that solder paste
thickness will directly affect the quality of the solder
joint, a good choice is to use laser cut stencil composed
of 0.100 mm (4 mils) or 0.127 mm (5 mils) thick stainless
steel which is capable of producing the required fine
stencil outline.
Average current = ∫(PDF x Current)dp
PCB Design Guidelines
The recommended WS1403 PCB land pattern is shown
in Figure 14 and Figure 15. The substrate is coated with
solder mask between the I/O and conductive paddle to
protect the gold pads from short circuit that is caused by
solder bleeding/bridging.
∅ 0.3 mm ON
0.5 mm PITCH
0.6
0.55
0.7
0.5
0.6
0.4
0.5
0.4
1.325
1.05
0.1
0.8
0.8
0.8
0.5
1.4
1.1
0.25
Figure 14. Metallization
Figure 15. Solder mask opening
Figure 16. Solder paste stencil aperture
Tape and Reel Information
P10 (3)
P2 (1)
P0
T
D0
Y
F
A
F (1)
W
B0
Y
SECTION Y - Y
X
P1 (2)
X
D1
A0
R 0.5
0.1
K0
1403
PYYWW
AAAAA
SECTION X - X
DETAIL A
DIMENSIONS
NOTATION
MILLIMETERS
A0
3.40 ± 0.10
B0
3.40 ± 0.10
K0
1.35 ± 0.10
D0
1.55 ± 0.05
D1
1.60 ± 0.10
P0
4.00 ± 0.10
P1
8.00 ± 0.10
P2
2.00 ± 0.05
P10
40.00 ± 0.20
E
1.75 ± 0.10
F
5.50 ± 0.05
W
12.00 ± 0.30
T
0.30 ± 0.05
Figure 17. Tape and reel format – 3 mm x 3 mm
R 1.0
Reel Drawing
BACK VIEW
FRONT VIEW
Figure 18. Plastic reel format (all dimensions are in millimeters)
10
Handling and Storage
ESD (Electrostatic Discharge)
Electrostatic discharge occurs naturally in the
environment. With the increase in voltage potential, the
outlet of neutralization or discharge will be sought. If the
acquired discharge route is through a semiconductor
device, destructive damage will result.
ESD countermeasure methods should be developed and
used to control potential ESD damage during handling
in a factory environment at each manufacturing site.
MSL (Moisture Sensitivity Level)
Plastic encapsulated surface mount package is
sensitive to damage induced by absorbed moisture and
temperature.
Avago Technologies follows JEDEC Standard J-STD 020B.
Each component and package type is classified for
moisture sensitivity by soaking a known dry package at
various temperatures and relative humidity, and times.
After soak, the components are subjected to three
consecutive simulated reflows.
The out of bag exposure time maximum limits are
determined by the classification test describe below
which corresponds to a MSL classification level 6 to 1
according to the JEDEC standard IPC/JEDEC J-STD-020B
and J-STD-033.
WS1403 is MSL3. Thus, according to the J-STD-033 p.11
the maximum Manufacturers Exposure Time (MET) for
this part is 168 hours. After this time period, the part
would need to be removed from the reel, de-taped and
then re-baked. MSL classification reflow temperature
for the WS1403 is targeted at 260°C +0/-5°C. Figure
19 and Table 7 show typical SMT profile for maximum
temperature of 260 +0/-5°C.
Table 5. ESD Classification
Pin #
Name
Description
HBM
CDM
Classification
1
Vref
Reference Voltage
±2000 V
±200 V
Class 2
2
Vcont
Control Voltage
±2000 V
±200 V
Class 2
3
RF In
RF Input
±2000 V
±200 V
Class 2
4
Vcc1
Supply Voltage
±2000 V
±200 V
Class 2
5
Vcc2
Supply Voltage
±2000 V
±200 V
Class 2
6
RF Out
RF Output
±2000 V
±200 V
Class 2
7
GND
Ground
±2000 V
±200 V
Class 2
8
GND
Ground
±2000 V
±200 V
Class 2
Note:
1. Module products should be considered extremely ESD sensitive.
Table 6. Moisture Classification Level and Floor Life
MSL Level
Floor Life (Out of Bag) at Factory Ambient = < 30°C/60% RH or As Stated
1
Unlimited at = < 30°C/85% RH
2
1 year
2a
4 weeks
3
168 hours
4
72 hours
5
48 hours
5a
24 hours
6
Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label.
Note:
1. The MSL Level is marked on the MSL Label on each shipping bag.
11
tp
TEMPERATURE
TP
CRITICAL ZONE
TL TO TP
RAMP UP
TL
tL
Tsmax
Tsmin
ts
PREHEAT
RAMP DOWN
25
t 25°C TO PEAK
TIME
Figure 19. Typical SMT reflow profile for maximum temperature = 260 +0/-5°C
Table 7. Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5°C
Profile Feature
Sn-Pb Solder
Pb-Free Solder
Average Ramp-Up Rate (TL to TP)
3°C/sec max
3°C /sec max
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (Min to Max) (ts)
100°C
150°C
60-120 sec
150°C
200°C
60-180 sec
Tsmax to TL
- Ramp-Up Rate
3°C /sec max
Time Maintained Above:
- Temperature (TL)
- Time (TL)
183°C
60-150 sec
217°C
60-150 sec
Peak Temperature (Tp)
240 +0/-5°C
260 +0/-5°C
Time Within 5°C of Actual Peak Temperature (tp)
10-30 sec
20-40 sec
Ramp-Down Rate
6°C/sec max
6°C/sec max
Time 25°C to Peak Temperature
6 min max.
8 min max.
12
Storage Condition
Baking of Populated Boards
Packages described in this document must be stored
in sealed moisture barrier, antistatic bags. Shelf life in a
sealed moisture barrier bag is 12 months at <40°C and
90% relative humidity (RH) J-STD-033 p.7.
Some SMD packages and board materials are not able
to withstand long duration bakes at 125°C. Examples of
this are some FR-4 materials, which cannot withstand a
24 hr bake at 125°C. Batteries and electrolytic capacitors
are also temperature sensitive. With component and
board temperature restrictions in mind, choose a
bake temperature from Table 4-1 in J-STD 033; then
determine the appropriate bake duration based on the
component to be removed. For additional considerations
see IPC-7711 and IPC-7721.
Out-of-Bag Time Duration
After unpacking, the device must be soldered to the PCB
within 168 hours as listed in the J-STD-020B p.11 with
factory conditions <30°C and 60% RH.
Baking
It is not necessary to re-bake the part if both conditions
(storage conditions and out-of bag conditions) have
been satisfied. Baking must be done if at least one of
the conditions above have not been satisfied. The baking
conditions are 125°C for 12 hours J-STD-033 p.8.
CAUTION
Tape and reel materials typically cannot be baked at the
temperature described above. If out-of-bag exposure
time is exceeded, parts must be baked for a longer time
at low temperatures, or the parts must be de-reeled, detaped, re-baked and then put back on tape and reel. (See
moisture sensitive warning label on each shipping bag
for information of baking).
Board Rework
Component Removal, Rework and Remount
If a component is to be removed from the board, it is
recommended that localized heating be used and the
maximum body temperatures of any surface mount
component on the board not exceed 200°C. This
method will minimize moisture related component
damage. If any component temperature exceeds 200°C,
the board must be baked dry per 4-2 prior to rework
and/or component removal. Component temperatures
shall be measured at the top center of the package body.
Any SMD packages that have not exceeded their floor
life can be exposed to a maximum body temperature as
high as their specified maximum reflow temperature.
Removal for Failure Analysis
Not following the above requirements may cause
moisture/reflow damage that could hinder or
completely prevent the determination of the original
failure mechanism.
13
Derating Due to Factory Environmental Conditions
Factory floor life exposures for SMD packages removed
from the dry bags will be a function of the ambient
environmental conditions. A safe, yet conservative,
handling approach is to expose the SMD packages only
up to the maximum time limits for each moisture
sensitivity level as shown in Table 7. This approach,
however, does not work if the factory humidity or
temperature is greater than the testing conditions of
30°C/60% RH. A solution for addressing this problem
is to derate the exposure times based on the knowledge
of moisture diffusion in the component package
materials ref. JESD22-A120). Recommended equivalent
total floor life exposures can be estimated for a range
of humidities and temperatures based on the nominal
plastic thickness for each device.
Table 8 lists equivalent derated floor lives for humidities
ranging from 20-90% RH for three temperature, 20°C,
25°C, and 30°C.
This table is applicable to SMDs molded with novolac,
biphenyl or multifunctional epoxy mold compounds.
The following assumptions were used in calculating
Table 8:
1. Activation Energy for diffusion = 0.35eV (smallest
known value).
2. For ≤60% RH, use Diffusivity = 0.121exp ( -0.35eV/kT)
mm2/s
(this used smallest known Diffusivity @ 30°C).
3. For >60% RH, use Diffusivity = 1.320exp ( -0.35eV/kT)
mm2/s
(this used largest known Diffusivity @ 30°C).
Table 8. Recommended Equivalent Total Floor Life (days) @ 20°C, 25°C and 30°C for ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified)
Maximum Percent Relative Humidity
Package Type and Body
Thickness
Moisture Sensitivity Level
Level 2a
Body Thickness
≥3.1 mm
Level 3
including
PQFPs >84 pin,
PLCCs (square)
Level 4
All MQFPs
or
All BGAs ≥1 mm
Level 5
Level 5a
Level 2a
Body 2.1 mm
≤ Thickness
Level 3
<3.1 mm including
PLCCs (rectangular)
18-32 pin
Level 4
SOICs (wide body)
SOICs ≥20 pins,
PQFPs ≤80 pins
Level 5
Level 5a
Level 2a
Body Thickness
Level 3
<2.1 mm
including
SOICs <18 pin
Level 4
All TQFPs, TSOPs or
All BGAs <1 mm body
thickness
Level 5
Level 5a
14
5%
10%
20%
30%
40%
50%
60%
70%
80%
90%
∞
∞
∞
60
41
33
28
10
7
6
30°C
∞
∞
∞
78
53
42
36
14
10
8
25°C
∞
∞
∞
∞
∞
10
103
9
69
8
57
7
47
7
19
5
13
4
10
4
20°C
30°C
∞
∞
13
11
10
9
9
7
6
5
25°C
∞
∞
∞
5
17
4
14
4
13
4
12
3
12
3
10
3
8
2
7
2
20°C
30°C
∞
6
5
5
5
5
4
3
3
3
25°C
∞
∞
8
4
7
3
7
3
7
2
7
2
6
2
5
2
4
1
4
1
20°C
30°C
∞
5
5
4
4
3
3
2
2
2
25°C
∞
∞
7
2
7
1
6
1
5
1
5
1
4
1
3
1
2
1
3
1
20°C
30°C
∞
3
2
2
2
2
2
1
1
1
25°C
∞
∞
5
∞
4
∞
3
∞
3
86
3
39
2
28
2
4
2
3
2
2
20°C
30°C
∞
∞
∞
∞
148
51
27
6
4
3
25°C
∞
∞
∞
∞
∞
19
∞
12
∞
9
69
8
49
7
8
3
5
2
4
2
20°C
30°C
∞
∞
25
15
12
10
9
5
3
3
25°C
∞
∞
∞
7
32
5
19
4
15
4
13
3
12
3
7
2
5
2
4
1
20°C
30°C
∞
9
7
5
5
4
4
3
2
2
25°C
∞
∞
11
4
9
3
7
3
6
2
6
2
5
2
4
1
3
1
3
1
20°C
30°C
∞
5
4
3
3
3
3
2
1
1
25°C
∞
∞
6
2
5
1
5
1
4
1
4
1
4
1
3
1
3
0.5
2
0.5
20°C
30°C
∞
2
2
2
2
2
2
1
1
1
25°C
∞
∞
3
∞
2
∞
2
∞
2
∞
2
∞
2
28
2
1
2
1
1
1
20°C
30°C
∞
∞
∞
∞
∞
∞
∞
2
1
1
25°C
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
11
∞
7
2
1
2
1
1
1
20°C
30°C
∞
∞
∞
∞
∞
14
10
2
1
1
25°C
∞
∞
∞
∞
∞
∞
∞
9
∞
5
20
4
13
3
2
1
2
1
1
1
20°C
30°C
∞
∞
∞
12
7
5
4
2
1
1
25°C
∞
∞
∞
∞
∞
13
17
5
9
3
7
2
6
2
2
1
2
1
1
1
20°C
30°C
∞
∞
18
6
4
3
3
2
1
1
25°C
∞
∞
∞
10
26
3
8
2
6
1
5
1
4
1
2
1
2
1
1
0.5
20°C
30°C
∞
13
5
3
2
2
2
1
1
1
25°C
∞
18
6
4
3
2
2
2
2
1
20°C
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved.
AV02-0291EN - August 26, 2008