EPSON S1C33401

S1C33401
CMOS 32-bit Single Chip Microcomputer
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32-bit C33 ADV RISC Core with 8K-byte Cache
Low Power Consumption
Multiply Accumulation
Built-in 32K-byte + 1K-byte RAM
10-bit ADC
4-ch. SIO
10-ch. PWM Timer with DA16 Mode
Card Interfaces
High-speed DMA, Intelligent DMA
■ DESCRIPTIONS
The S1C33401 is a 32-bit RISC-type microcomputer originally developed for embedded applications by Seiko Epson.
The S1C33401 is built around the C33 ADV core block that includes the CPU, MMU, cache, and modules that allow
various external memory and I/O devices to be connected directly, and incorporates a bus block that includes the DMA
controller and other control units. In addition to these primary units, the S1C33401 incorporates a basic peripheral circuit
block that includes an interrupt controller, timers, serial interfaces, card interfaces, input/output ports, and A/D
converter, and an extended peripheral circuit block that includes a chip ID register, RTC, and other components.
The S1C33401 is manufactured by a 0.18 μm fine-pattern CMOS process, backed by sophisticated clock control
functions, and can operate at higher speed with less power than ever before. In addition to its use as an embedded-type
processor in various portable systems, the S1C33401 features a built-in C33 ADV CPU to provide enhanced functionality
for multimedia support while retaining upward compatibility with the conventional C33 STD CPU, making it an ideal
solution to the requirements of mobile multimedia applications.
Product Lineup
Model No.
Package
S1C33401F00A∗∗∗
QFP20-184pin
S1C33401B00A∗∗∗
PFBGA-160pin
■ FEATURES
CORE
● CPU
•
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•
Original Seiko Epson 32-bit RISC-type CPU – C33 ADV
Internal 32-bit data processing
4GB address space
Powerful instruction set
- Code length:
16 bits per instruction
- Number of instructions: 164
- Main instructions executable in 1 cycle (including immediate-extended instructions, each consisting of two to three
instructions)
- 15.15 ns per instruction (when operating at 66 MHz, max.)
• Multimedia support functions
- Built-in 32-bit × 16-bit multiplier
- 16 × 16, 32 × 16 and 32 × 32-bit multiplication
- 16 × 16, 32 × 16 and 32 × 32-bit multiply-accumulate operations
- Repeated execution by loop and repeat instructions
- Rounding to minimum/maximum values by saturation instruction
- ALU instruction execution with post-shift
● High-speed Bus Control Unit (HBCU)
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•
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•
Controls memory access by the CPU by dividing 4GB logical space into eight 512MB blocks.
Manages MMU, CCU, and ASID processing in each block.
Capable of multiplexing logical space using ASID and mirroring physical space.
Can simultaneously process A0RAM data read/write operations and instruction fetching from cache.
SEIKO EPSON CORPORATION
S1C33401
● Memory Management Unit (MMU)
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•
•
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•
Converts logical space into physical space in page units (4KB or 64KB per page).
Supports 16 entries per way for a total of 64 entries, due to 4-way set associative method.
Can protect memory for each page.
Allows optional selection of using cache for each page.
Supports five causes of MMU exception.
● Cache Control Unit (CCU)
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Physical address-based instruction/data coexisting type of cache
Contains 8KB cache.
Supports 128 entries per way for a total of 512 lines, due to 4-way set associative method (4 words per line).
Allows selection of write-through or write-back mode for writing to cache.
Can lock a specified way and interrupt handler routine.
Forwarding function to allow immediate instruction/data transfer even during refill.
● Clock Management Unit (CMU)
• Controls reset and NMI input.
• System clock control
- Selects clock source, turns clock on/off, and divides operating clock.
- Controls clock according to standby mode (SLEEP, HALT, or HALT2).
• Controls clock supply for each module (manual/auto).
● Debug Unit (DBG)
• Supports on-chip trace/break and other debugging functions at the chip level.
• Provides an advanced debugging environment in conjunction with the ICD (in-circuit debugger) and debugger.
INTERNAL MEMORY
● High-speed RAM Incorporated in Area 0 (A0RAM)
• 32KB
• High-speed access with zero wait state
● RAM Incorporated in Area 3 (A3RAM)
• 1KB
• Access with one wait state
• Also usable as IDMA control information table
BUS CONTROL UNITS AND DMA CONTROLLER
● Basic Bus Control Unit (BBCU)
• Controls external address space by dividing it into 19 areas (Areas 4 to 22).
• Allows selection of external/internal access, endian mode, interface mode, device type, device size, and number of
access cycles for each area.
• Outputs 8 chip-enable signals (#CE4–#CE11) corresponding to each external area.
• Supports two interface modes: A0 and BSL (with BSL mode for external memory only).
• Allows direct connection of SRAM, ROM, burst ROM, or flash memory to external bus.
• Allows insertion of wait state from external #WAIT pin (for SRAM type only).
• Arbitrates bus contention with external bus masters.
● Extended Bus Control Unit (EBCU)
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2
Allows direct connection of SDRAM (in one of Areas 4 to 22 selected).
Data bus width: 16 bits
Bank address: Up to four banks accommodated.
Burst length:
Fixed to 1 (with burst read/write executed by issuing successive commands).
CAS latency: 1, 2, or 3
Write mode:
Single write
Supports self-refresh and auto-refresh.
Programmable refresh cycle
Allows selection of bank active mode (with or without auto-precharge).
EPSON
S1C33401
● High-speed DMA Controller (HSDMA)
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•
Up to four channels
Capable of high-speed DMA transfer because of no need to read/write transfer conditions, etc. from/to memory.
Supports dual-address and single-address transfers.
Activated by DMA request input, interrupt cause, or software trigger.
Can generate interrupt upon completion of transfer.
● Intelligent DMA Controller (IDMA)
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Up to 128 channels
Supports dual-address transfers.
Programmable DMA transfer control information in RAM (except A0RAM)
Activated by a specific interrupt cause or software trigger.
Can be linked from one IDMA channel to another.
Can generate an interrupt upon completion of transfer.
INTERNAL PERIPHERAL CIRCUITS
● OSC3 Oscillator Circuit
• Generates the main system clock.
• Crystal/ceramic oscillator: 5 MHz (min.) to 33 MHz (max.)
• External clock input:
2 MHz (min.) to 33 MHz (max.)
● PLL
• Allows selection of whether to use ×1 to ×16 OSC3 oscillation frequency.
• PLL input frequency: 5 MHz (min.) to 33 MHz (max.)
• PLL output frequency: 20 MHz (min.) to 66 MHz (max.)
● SSCG (Spread Spectrum Clock Generator)
• SS-modulation circuit for system source clock (OSC3, PLL, or OSC1) to reduce Electromagnetic Interference (EMI)
noise
● Interrupt Controller (ITC)
• Branches to interrupt handling routine via interrupt vector table.
• Can activate intelligent DMA.
• Handles 9 exceptions:
- Reset exception (1)
- Divide by zero exception (1)
- Address misaligned exception (1)
- NMI (1)
- Software exceptions (4)
- MMU exception (1)
• Handles 64 maskable interrupts:
- Port/key input interrupts (18)
- DMA controller interrupts (5)
- 16-bit timer interrupts (20)
- 8-bit timer interrupts (6)
- Serial interface interrupts (12)
- A/D converter interrupts (2)
- RTC interrupt (1)
● Prescaler (PSC)
• Programmable 8-bit and 16-bit timers, and A/D converter clock settings
● 8-bit Timer (T8)
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6-channel, 8-bit programmable timers
Can generate an interrupt upon underflow.
Can output the clock generated by underflow to external devices.
Generates serial interface clock as programmed.
Can output a trigger to A/D converter at specified intervals.
EPSON
3
S1C33401
● 16-bit Timer (T16)
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10-channel, 16-bit programmable timers
Can be used as PWM timer.
Supports DA16 mode.
Can generate two interrupts per channel upon underflow or when matching compared value.
Can output clock generated by underflow or when matching compared value to external devices.
● Watchdog Timer (WDT)
• 30-bit watchdog timer capable of generating NMI
• Programmable setting of NMI generation cycle
● Serial Interface (SIO)
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4 channels
Contains 4-byte receive data buffer (FIFO) and 2-byte transmit data buffer (FIFO) for each channel.
Supports full-duplex communication.
Selectable between 8-bit clock-synchronous and 8-bit or 7-bit asynchronous modes.
Supports IrDA 1.0 interface.
Can generate transmit buffer empty, receive buffer full, and receive error interrupts.
● Card Interface (CARD)
• Supports SmartMedia card (NAND flash).
• Supports CompactFlash card.
• Supports PC card (2 channels).
● I/O Ports (PORT)
• Up to 71 ports
• Can be used as general-purpose I/O pins when not used for peripheral functions.
• Programmable port input and key input interrupts
● A/D Converter (ADC)
• 4-channel, 10-bit A/D converters
• Can generate an interrupt upon completion of conversion.
• Can generate an interrupt when converted value is outside specified upper and lower limits.
● RTC
• Contains BCD time (second, minute, and hour) counters and calendar (day, days of the week, month, and year)
counters.
• Allows selection between 24-hour and 12-hour modes.
• Equipped with function for 30-second correction in software.
• Can periodically generate interrupts (at intervals of 1/64 or 1 second, 1 minute, or 1 hour).
• Powered independently of other modules, and can operate even when system power is turned off.
• Contains an OSC1 oscillator circuit to generate 32.768 kHz (typ.) clock.
OPERATING CONDITIONS AND POWER CONSUMPTION
● Power Supply Voltage
• Core power supply voltages (VDD, PLLVDD, RTCVDD): 1.65 V to 1.95 V (1.8 V ± 0.15 V)
2.70 V to 3.60 V (3.0/3.3 V ± 0.3 V)
• I/O power supply voltages (VDDE , TMVDD, AVDD):
● Input Voltage
• High-level input voltage: 2.20 V (min.) to VDDE (max.)
• Low-level input voltage: V SS (min.) to 0.80 V (max.)
● Operating Clock Frequency
• CPU:
66 MHz (max.)
• Bus (BBCU, EBCU): 66 MHz (max.)
● Operating Temperature
• -40°C to 85°C
4
EPSON
S1C33401
● Power Consumption
• In SLEEP mode: 25 μW (typ.)
• In HALT mode: 36 mW (typ., 66 MHz)
• During operation: 65 mW (typ., 66 MHz, cache off)
FORM OF SHIPMENT
• PFBGA 160-pin plastic package (10 mm × 10 mm × 1.2 mm, 0.65 mm pitch)
• QFP20 184-pin plastic package (20 mm × 20 mm × 1.7 mm, 0.40 mm pitch)
■ BLOCK DIAGRAM
S1C33401
C33 ADV Core Block
C33 ADV CPU
DBG
MMU
HBCU
A0RAM
(Area 0 No-Wait RAM)
CMU
Standard Peripheral Block
Interrupt controller
(ITC)
Prescaler
(PSC)
A3RAM
(Area 3 RAM)
Bridge
High-speed bus
OSC3/PLL
CCU
8-bit Timer
(T8)
Bus Control Block
DMA
EBCU
(SDRAM Controller)
BBCU
(SRAM Controller)
16-bit Timer/PWM
(T16)
Extended Peripheral Block
Watchdog Timer
(WDT)
Real Time Clock
(RTC)
Serial Interface
(SIO)
Chip ID, Pin control
and Misc. registers
Card Interface
(CARD)
(Area 6)
I/O Ports
(PORT)
A/D Converter
(ADC)
(Area 1)
EPSON
5
P95(SOUT3/ASTB/DTD5)
P96(#SCLK3/CARD4/DTD6)
P97(#SRDY3/CARD5/DTD7)
VDDE
P82(#DMAEND2/EXCL5/DBT)
P83(#DMAEND3/EXCL6/DTS0)
P84(PSC_CLK/CARD2/DTS1)
P85(CMU_CLK/CARD3/DTS2)
VDD
P86(TM8/CARD0/DTS3)
P87(TM9/CARD1/DTS4)
VSS
P80(#DMAACK2/T8UF3/EXCL3)
P81(#DMAACK3/T8UF4/EXCL4)
VDDE
N.C.
P30(#DMAREQ0/T8UF0/EXCL0)
P31(#DMAREQ1/T8UF1/EXCL1)
P32(#DMAREQ2/CARD2/EXCL2)
P33(#DMAREQ3/CARD3/WDT_CLK)
P60(#BUSREQ/CARD4)
P61(#BUSACK/CARD5)
VSS
N.C.
VDD
N.C.
P62(#BUSGET/T8UF2/#ADTRG)
CMU_CLK(P63/BCLK/T8UF5)
VDDE
#CE4(P50/CARD0)
#CE5(P51)
#CE6(P52)
#CE7(P53/CARD1)
#CE8(P54)
VSS
P64(#WAIT)
TMVDD
P10(TM0)
P11(TM1)
VDD
P12(TM2)
P13(TM3)
P14(TM4/#DMAEND0)
P15(TM5/#DMAEND1)
P16(TM6/#DMAACK0)
P17(TM7/#DMAACK1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
VSS
#CE11(P56)
#CE9(P55)
#CE10
P27(DQMH/#SRDY3)
P26(DQML/#SCLK3)
VSS
P21(SDCLK/SOUT2)
VDD
P25(#SDWE/SOUT3)
VDDE
P24(#SDCAS/SIN3)
P23(#SDRAS/#SRDY2)
P22(#SDCS/#SCLK2)
P20(SDCKE/SIN2)
VSS
D15
D14
D13
VDDE
N.C.
VDD
N.C.
D12
D11
VSS
N.C.
D10
D9
D8
D7
VDDE
D6
VSS
D5
D4
D3
VDD
D2
D1
VSS
VDDE
D0
#BSL
#WRH
#WRL
S1C33401
■ PIN LAYOUT DIAGRAM
QFP20-184pin
RTCVDD
#STBY
OSC1
OSC2
PLLVDD
VCP
PLLVSS
VDD
BURNIN
SCANEN
OSC3
OSC4
VSS
TST0
TST1
VDDE
#RESET
#NMI
P00(SIN0)
P01(SOUT0)
P02(#SCLK0)
VDD
N.C.
P03(#SRDY0)
P04(SIN1)
N.C.
VSS
P05(SOUT1)
P06(#SCLK1)
P07(#SRDY1)
DSIO
DST0(P65)
DST1(P66)
DST2
VDD
DPCO(P67)
VSS
DCLK
VDDE
N.C.
P90(SIN2/EXCL7/DTD0)
P91(SOUT2/EXCL8/DTD1)
P92(#SCLK2/EXCL9/DTD2)
P93(#SRDY2/R/W/DTD3)
P94(SIN3/ACST/DTD4)
VSS
6
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
EPSON
#RD
VSS
A0
A1
A2
VDDE
A3
A4
VSS
A5
VDD
A6
A7
A8
A9
A10
N.C.
VDDE
N.C.
VSS
A11
VDD
N.C.
A12
A13
A14
A15
A16
A17
VSS
A18(P47)
VDDE
A19(P46)
A20(P45)
A21(P44)
VDD
A22(P43)
A23(P42)
A24(P41)
A25(P40)
VSS
AVDD
P73(AIN3)
P72(AIN2)
P71(AIN1)
P70(AIN0)
S1C33401
PFBGA-160pin
Top View
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A1 Corner
1
2
P92
#SCLK2
EXCL9
N.C. DTD2
A
B
C
D
E
F
G
H
J
K
L
M
N
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Index
A B C D E F G H J K L MN P
3
P90
Bottom View
4
DCLK
SIN2
EXCL7
DTD0
5
6
7
8
P66
P06
P03
P00
DST1
#SCLK1
#SRDY0
SIN0
9
10
OSC4
OSC3
11
VSS
13
OSC1
14
A
P93
P91
P67
P65
P05
SOUT3
ASTB
DTD5
#SRDY2
R/W
DTD3
SOUT2
EXCL8
DTD1
DPCO
DST0
SOUT1
P97
P96
VSS
P94
DSIO
P07
P04
P01
#SRDY3
CARD5
DTD7
#SCLK3
CARD4
DTD6
#SRDY1
SIN1
SOUT0
P84
P83
P82
VSS
P02
#RESET
PSC_CLK
CARD2
DTS1
#DMAEND3
EXCL6
DTS0
#DMAEND2
EXCL5
DBT
P86
VSS
P85
SIN3
ACST
DTD4
VDDE
DST2
VDD
#NMI
TST1
SCANEN VDD
RTCVDD
#STBY
VSS
B
TST0
BURNIN
VCP
PLLVDD
#CE10
P27
DQMH
#SRDY3
VDDE
#SCLK0
#CE11
PLLVSS
P56
P26
VSS
VDD
SDCLK
SOUT2
#CE9
P25
P24
P55
#SDWE
SOUT3
#SDCAS
SIN3
VDD
P23
D15
P81
P30
P87
P80
#DMAACK3
T8UF4
EXCL4
#DMAREQ0
T8UF0
EXCL0
TM9
CARD1
DTS4
#DMAACK2
T8UF3
EXCL3
P32
P61
P31
P33
P22
#DMAREQ2
CARD2
EXCL2
#BUSACK
CARD5
#DMAREQ1
T8UF1
EXCL1
#DMAREQ3
CARD3
WDT_CLK
#SDCS
#SCLK2
CMU_CLK P62
P60
VDDE
P63
BCLK
T8UF5
#BUSGET
T8UF2
#ADTRG
#BUSREQ
CARD4
#CE6
#CE5
#CE7
#CE4
P52
P51
P53
CARD1
P50
CARD0
P64
TMVDD
VSS
#CE8
#SDRAS
#SRDY2
Top View
VDDE
D13
D
VDDE
E
P20
SDCKE
SIN2
D14
F
VDD
G
D11
D12
VSS
H
D9
D8
D10
D7
J
VSS
D4
D6
D5
P54
K
P11
P12
P13
P10
TM1
TM2
TM3
TM0
P14
P16
P17
P15
A23
TM4
#DMAEND0
TM6
#DMAACK0
TM7
#DMAACK1
TM5
#DMAEND1
P42
P70
P71
AVDD
A25
A22
A19
AIN0
AIN1
P40
P43
P46
P
VDD
A21
A16
VSS
A6
A4
D3
VDD
D2
D1
P44
L
VDDE
A14
A11
A9
VSS
#WRL
#WRH
#BSL
D0
M
P72
P73
A24
A20
A18
AIN2
AIN3
P41
P45
P47
A17
A13
A8
A5
VDDE
A1
VSS
#RD
N
A15
A12
A10
A7
A3
A2
A0
P
N.C.
1
C
P21
DQML
#SCLK3
CMU_CLK
CARD3
DTS2
#WAIT
12
OSC2
N.C.
P95
TM8
CARD0
DTS3
A1 Corner
P NM L K J H G F E D C B A
N.C.
2
3
4
5
6
7
8
EPSON
9
10
11
12
13
14
7
S1C33401
■ PIN DESCRIPTION
Power Supply Pin List
Pin name
VDD
VSS
PLLVDD
PLLVSS
RTCVDD
VDDE
TMVDD
AVDD
Pin No.
Function
QFP
PFBGA
9,25,40,57,71,82,101,
B7,B11,E4,F11,G14,
Power supply (+) for the internal logic circuits (1.65 V to 1.95 V)
117,130,146,160,173
L5,L12
12,23,35,52,63,73,84,91,98, A11,B14,C3,D6,D13,E2, Power supply (–); GND
105,113,123,132,138,151, H14,K3,K11,L8,M10,N13
165,175,184
Power supply (+) for the PLL (PLLVDD = VDD)
C12
143
Power supply (–) for the PLL (PLLVSS = VSS)
D11
145
Power supply (+) for the RTC (RTCVDD = VDD)
B12
139
4,15,29,61,75,87,97,107, D4,D9,E14,H4,H11,M6,N11 Power supply (+) for the I/O block (2.7 V to 3.6 V)
119,128,154,177
Power supply (+) for PWM timer outputs (P1x port) (TMVDD = VDDE)
K2
37
Power supply (+) for the analog system and AIN0–AIN3 (AVDD = VDDE)
N3
51
External Bus Pin List
Pin name
D[15:0]
#BSL
#RD
#WRL
#WRH
A[17:0]
A18
P47
A19
P46
A20
P45
A21
P44
A22
P43
A23
P42
A24
P41
A25
P40
#CE11
P56
#CE10
#CE9
P55
#CE8
P54
8
Pin No.
QFP
PFBGA
122–120, F13,G13,
115,114, G12,H13,
111–108, H12,J13,
106, J11,J12,
104–102, J14,K13,
100,99, K14,K12,
96
L11,L13,
L14,M14
95
M13
92
N14
93
M11
94
M12
64–69, N7,L7,
72,
P7,M7,
77–81, N8,P8,
83,85, M8,P9,
86,
M9,N9,
88–90 P10,L9,
N10,L10,
P11,P12,
N12,P13
62
P6
I/O Pull-up
Function
Module
I/O
∗2
Data bus (D15–D0)
BBCU
EBCU
O
O
O
O
O
∗1
∗1
∗1
∗1
∗1
Bus strobe (low byte) signal in BSL mode
Read signal
Write (low byte) signal in A0 mode or write signal in BSL mode
Write (high byte) signal in A0 mode or Bus strobe (high byte) signal in BSL mode
Address bus (A17–A0)
BBCU
BBCU
BBCU
BBCU
BBCU
EBCU
I/O
∗1
A18:
Address bus (A18) (default)
P47:
General-purpose I/O port
A19:
Address bus (A19) (default)
P46:
General-purpose I/O port
A20:
Address bus (A20) (default)
P45:
General-purpose I/O port
A21:
Address bus (A21) (default)
P44:
General-purpose I/O port
A22:
Address bus (A22) (default)
P43:
General-purpose I/O port
A23:
Address bus (A23) (default)
P42:
General-purpose I/O port
A24:
Address bus (A24) (default)
P41:
General-purpose I/O port
A25:
Address bus (A25) (default)
P40:
General-purpose I/O port
#CE11: Chip enable signal for areas 11 and 12 (default)
P56:
General-purpose I/O port
Chip enable signal for areas 10, 13 and 20
#CE9: Chip enable signal for areas 9 and 22 (default)
P55:
General-purpose I/O port
#CE8: Chip enable signal for areas 8 and 21 (default)
P54:
General-purpose I/O port
BBCU
PORT
BBCU
PORT
BBCU
PORT
BBCU
PORT
BBCU
PORT
BBCU
PORT
BBCU
PORT
BBCU
PORT
BBCU
PORT
BBCU
BBCU
PORT
BBCU
PORT
60
N6
I/O
∗1
59
P5
I/O
∗1
58
L6
I/O
∗1
56
N5
I/O
∗1
55
M5
I/O
∗1
54
P4
I/O
∗1
53
N4
I/O
∗1
137
D10
I/O
∗1
135
136
C13
E11
I/O
I/O
∗1
∗1
34
K4
I/O
∗1
EPSON
S1C33401
Pin name
#CE7
P53
CARD1
#CE6
P52
#CE5
P51
#CE4
P50
CARD0
Pin No.
I/O Pull-up
Function
QFP
PFBGA
33
J3
I/O
#CE7: Chip enable signal for areas 7 and 19 (default)
∗1
P53:
General-purpose I/O port
CARD1:Card I/F signal 1 output (#SMWR or #CFCE2)
32
J1
I/O
#CE6: Chip enable signal for areas 6, 17 and 18 (default)
∗1
P52:
General-purpose I/O port
31
J2
I/O
#CE5: Chip enable signal for areas 5, 15 and 16 (default)
∗1
P51:
General-purpose I/O port
30
J4
I/O
∗1
#CE4: Chip enable signal for areas 4 and 14 (default)
P50:
General-purpose I/O port
CARD0:Card I/F signal 0 output (#SMRD or #CFCE1)
Module
BBCU
PORT
CARD
BBCU
PORT
BBCU
PORT
BBCU
PORT
CARD
Input/Output Port and Peripheral Circuit Pin List
Pin name
P00
SIN0
P01
SOUT0
P02
#SCLK0
P03
#SRDY0
P04
SIN1
P05
SOUT1
P06
#SCLK1
P07
#SRDY1
P10
TM0
P11
TM1
P12
TM2
P13
TM3
P14
TM4
#DMAEND0
P15
TM5
#DMAEND1
P16
TM6
#DMAACK0
P17
TM7
#DMAACK1
P20
SDCKE
SIN2
P21
SDCLK
SOUT2
P22
#SDCS
#SCLK2
P23
#SDRAS
#SRDY2
P24
#SDCAS
SIN3
Pin No.
I/O Pull-up
Function
QFP
PFBGA
157
A8
I/O
P00:
General-purpose I/O port (default)
∗1
SIN0:
Serial I/F Ch.0 data input
158
C8
I/O
P01:
General-purpose I/O port (default)
∗1
SOUT0:
Serial I/F Ch.0 data output
159
D7
I/O
P02:
General-purpose I/O port (default)
∗1
#SCLK0:
Serial I/F Ch.0 clock input/output
162
A7
I/O
∗1
P03:
General-purpose I/O port (default)
#SRDY0:
Serial I/F Ch.0 ready signal input/output
163
C7
I/O
∗1
P04:
General-purpose I/O port (default)
SIN1:
Serial I/F Ch.1 data input
166
B6
I/O
∗1
P05:
General-purpose I/O port (default)
SOUT1:
Serial I/F Ch.1 data output
167
A6
I/O
∗1
P06:
General-purpose I/O port (default)
#SCLK1:
Serial I/F Ch.1 clock input/output
168
C6
I/O
∗1
P07:
General-purpose I/O port (default)
#SRDY1:
Serial I/F Ch.1 ready signal input/output
38
L4
I/O
∗1
P10:
General-purpose I/O port (default)
TM0:
16-bit timer 0 output
39
L1
I/O
∗1
P11:
General-purpose I/O port (default)
TM1:
16-bit timer 1 output
41
L2
I/O
∗1
P12:
General-purpose I/O port (default)
TM2:
16-bit timer 2 output
42
L3
I/O
∗1
P13:
General-purpose I/O port (default)
TM3:
16-bit timer 3 output
43
M1
I/O
∗1
P14:
General-purpose I/O port (default)
TM4:
16-bit timer 4 output
#DMAEND0: HSDMA Ch.0 end-of-transfer signal output
44
M4
I/O
∗1
P15:
General-purpose I/O port (default)
TM5:
16-bit timer 5 output
#DMAEND1: HSDMA Ch.1 end-of-transfer signal output
45
M2
I/O
∗1
P16:
General-purpose I/O port (default)
TM6:
16-bit timer 6 output
#DMAACK0: HSDMA Ch.0 acknowledge signal output
46
M3
I/O
∗1
P17:
General-purpose I/O port (default)
TM7:
16-bit timer 7 output
#DMAACK1: HSDMA Ch.1 acknowledge signal output
124
F14
I/O
∗1
P20:
General-purpose I/O port (default)
SDCKE:
SDRAM clock enable signal output
SIN2:
Serial I/F Ch.2 data input
131
D14
I/O
∗1
P21:
General-purpose I/O port (default)
SDCLK:
SDRAM clock output
SOUT2:
Serial I/F Ch.2 data output
125
G11
I/O
∗1
P22:
General-purpose I/O port (default)
#SDCS:
SDRAM chip enable signal output
#SCLK2:
Serial I/F Ch.2 clock input/output
126
F12
I/O
∗1
P23:
General-purpose I/O port (default)
#SDRAS:
SDRAM row address strobe signal output
#SRDY2:
Serial I/F Ch.2 ready signal input/output
127
E13
I/O
∗1
P24:
General-purpose I/O port (default)
#SDCAS:
SDRAM column address strobe signal output
SIN3:
Serial I/F Ch.3 data input
EPSON
Module
PORT
SIO
PORT
SIO
PORT
SIO
PORT
SIO
PORT
SIO
PORT
SIO
PORT
SIO
PORT
SIO
PORT
T16
PORT
T16
PORT
T16
PORT
T16
PORT
T16
HSDMA
PORT
T16
HSDMA
PORT
T16
HSDMA
PORT
T16
HSDMA
PORT
EBCU
SIO
PORT
EBCU
SIO
PORT
EBCU
SIO
PORT
EBCU
SIO
PORT
EBCU
SIO
9
S1C33401
Pin name
P25
#SDWE
SOUT3
P26
DQML
#SCLK3
P27
DQMH
#SRDY3
P30
#DMAREQ0
T8UF0
EXCL0
P31
#DMAREQ1
T8UF1
EXCL1
P32
#DMAREQ2
CARD2
EXCL2
P33
#DMAREQ3
CARD3
WDT_CLK
P60
#BUSREQ
CARD4
P61
#BUSACK
CARD5
P62
#BUSGET
T8UF2
#ADTRG
P64
#WAIT
P70
AIN0
P71
AIN1
P72
AIN2
P73
AIN3
P80
#DMAACK2
T8UF3
EXCL3
P81
#DMAACK3
T8UF4
EXCL4
P82
#DMAEND2
EXCL5
DBT
P83
#DMAEND3
EXCL6
DTS0
P84
PSC_CLK
CARD2
DTS1
10
Pin No.
I/O Pull-up
Function
QFP
PFBGA
129
E12
I/O
P25:
General-purpose I/O port (default)
∗1
#SDWE:
SDRAM write signal output
SOUT3:
Serial I/F Ch.3 data output
133
D12
I/O
P26:
General-purpose I/O port (default)
∗1
DQML:
SDRAM data (low byte) input/output mask signal output
#SCLK3:
Serial I/F Ch.3 clock input/output
134
C14
I/O
P27:
General-purpose I/O port (default)
∗1
DQMH:
SDRAM data (high byte) input/output mask signal output
#SRDY3:
Serial I/F Ch.3 ready signal input/output
17
F2
I/O
∗1
P30:
General-purpose I/O port (default)
#DMAREQ0:HSDMA Ch.0 request input
T8UF0:
8-bit timer 0 output
EXCL0:
16-bit timer 0 event counter input
18
G3
I/O
∗1
P31:
General-purpose I/O port (default)
#DMAREQ1:HSDMA Ch.1 request input
T8UF1:
8-bit timer 1 output
EXCL1:
16-bit timer 1 event counter input
19
G1
I/O
∗1
P32:
General-purpose I/O port (default)
#DMAREQ2:HSDMA Ch.2 request input
CARD2:
Card I/F signal 2 output (#IORD or #SMRD)
EXCL2:
16-bit timer 2 event counter input
20
G4
I/O
∗1
P33:
General-purpose I/O port (default)
#DMAREQ3:HSDMA Ch.3 request input
CARD3:
Card I/F signal 3 output (#IOWR or #SMWR)
WDT_CLK: Watchdog timer output
21
H3
I/O
∗1
P60:
General-purpose I/O port (default)
#BUSREQ: Bus release request input
CARD4:
Card I/F signal 4 output (#OE or #CFCE1)
22
G2
I/O
∗1
P61:
General-purpose I/O port (default)
#BUSACK: Bus acknowledge output
CARD5:
Card I/F signal 5 output (#WE or #CFCE2)
27
H2
I/O
∗1
P62:
General-purpose I/O port (default)
#BUSGET: Bus status monitor signal output
T8UF2:
8-bit timer 2 output
#ADTRG:
A/D converter trigger input
36
K1
I/O
∗1
P64:
General-purpose I/O port (default)
#WAIT:
Wait cycle request input
47
N1
I
∗1
P70:
General-purpose I/O port (default)
AIN0:
A/D converter Ch.0 input
48
N2
I
∗1
P71:
General-purpose I/O port (default)
AIN1:
A/D converter Ch.1 input
49
P2
I
∗1
P72:
General-purpose I/O port (default)
AIN2:
A/D converter Ch.2 input
50
P3
I
∗1
P73:
General-purpose I/O port (default)
AIN3:
A/D converter Ch.3 input
13
F4
I/O
∗1
P80:
General-purpose I/O port (default)
#DMAACK2: HSDMA Ch.2 acknowledge signal output
T8UF3:
8-bit timer 3 output
EXCL3:
16-bit timer 3 event counter input
14
F1
I/O
∗1
P81:
General-purpose I/O port (default)
#DMAACK3: HSDMA Ch.3 acknowledge signal output
T8UF4:
8-bit timer 4 output
EXCL4:
16-bit timer 4 event counter input
5
D3
I/O
∗1
P82:
General-purpose I/O port (default)
#DMAEND2: HSDMA Ch.2 end-of-transfer signal output
EXCL5:
16-bit timer 5 event counter input
DBT:
DBT signal output for debugging
6
D2
I/O
∗1
P83:
General-purpose I/O port (default)
#DMAEND3: HSDMA Ch.3 end-of-transfer signal output
EXCL6:
16-bit timer 6 event counter input
DTS0:
DTS0 signal output for debugging
7
D1
I/O
∗1
P84:
General-purpose I/O port (default)
PSC_CLK: Prescaler clock output
CARD2:
Card I/F signal 2 output (#IORD or #SMRD)
DTS1:
DTS1 signal output for debugging
EPSON
Module
PORT
EBCU
SIO
PORT
EBCU
SIO
PORT
EBCU
SIO
PORT
HSDMA
T8
T16
PORT
HSDMA
T8
T16
PORT
HSDMA
CARD
T16
PORT
HSDMA
CARD
WDT
PORT
BBCU
CARD
PORT
BBCU
CARD
PORT
BBCU
T8
ADC
PORT
BBCU
PORT
ADC
PORT
ADC
PORT
ADC
PORT
ADC
PORT
HSDMA
T8
T16
PORT
HSDMA
T8
T16
PORT
HSDMA
T16
DBG
PORT
HSDMA
T16
DBG
PORT
PSC
CARD
DBG
S1C33401
Pin name
P85
CMU_CLK
CARD3
DTS2
P86
TM8
CARD0
DTS3
P87
TM9
CARD1
DTS4
P90
SIN2
EXCL7
DTD0
P91
SOUT2
EXCL8
DTD1
P92
#SCLK2
EXCL9
DTD2
P93
#SRDY2
R/W
DTD3
P94
SIN3
ACST
DTD4
P95
SOUT3
ASTB
DTD5
P96
#SCLK3
CARD4
DTD6
P97
#SRDY3
CARD5
DTD7
Pin No.
I/O Pull-up
QFP
PFBGA
8
E3
I/O
P85:
∗1
CMU_CLK:
CARD3:
DTS2:
10
E1
I/O
P86:
∗1
TM8:
CARD0:
DTS3:
11
F3
I/O
P87:
∗1
TM9:
CARD1:
DTS4:
179
A3
I/O
∗1
P90:
SIN2:
EXCL7:
DTD0:
180
B3
I/O
∗1
P91:
SOUT2:
EXCL8:
DTD1:
181
A2
I/O
∗1
P92:
#SCLK2:
EXCL9:
DTD2:
182
B2
I/O
∗1
P93:
#SRDY2:
R/W:
DTD3:
183
C4
I/O
∗1
P94:
SIN3:
ACST:
DTD4:
1
B1
I/O
∗1
P95:
SOUT3:
ASTB:
DTD5:
2
C2
I/O
∗1
P96:
#SCLK3:
CARD4:
DTD6:
3
C1
I/O
∗1
P97:
#SRDY3:
CARD5:
DTD7:
Function
General-purpose I/O port (default)
CMU external clock output
Card I/F signal 3 output (#IOWR or #SMWR)
DTS2 signal output for debugging
General-purpose I/O port (default)
16-bit timer 8 output
Card I/F signal 0 output (#SMRD or #CFCE1)
DTS3 signal output for debugging
General-purpose I/O port (default)
16-bit timer 9 output
Card I/F signal 1 output (#SMWR or #CFCE2)
DTS4 signal output for debugging
General-purpose I/O port (default)
Serial I/F Ch.2 data input
16-bit timer 7 event counter input
DTD0 signal output for debugging
General-purpose I/O port (default)
Serial I/F Ch.2 data output
16-bit timer 8 event counter input
DTD1 signal output for debugging
General-purpose I/O port (default)
Serial I/F Ch.2 clock input/output
16-bit timer 9 event counter input
DTD2 signal output for debugging
General-purpose I/O port (default)
Serial I/F Ch.2 ready signal input/output
Read/Write status output
DTD3 signal output for debugging
General-purpose I/O port (default)
Serial I/F Ch.3 data input
Bus access status output
DTD4 signal output for debugging
General-purpose I/O port (default)
Serial I/F Ch.3 data output
Address strobe output
DTD5 signal output for debugging
General-purpose I/O port (default)
Serial I/F Ch.3 clock input/output
Card I/F signal 4 output (#OE or #CFCE1)
DTD6 signal output for debugging
General-purpose I/O port (default)
Serial I/F Ch.3 ready signal input/output
Card I/F signal 5 output (#WE or #CFCE2)
DTD7 signal output for debugging
Module
PORT
CMU
CARD
DBG
PORT
T16
CARD
DBG
PORT
T16
CARD
DBG
PORT
SIO
T16
DBG
PORT
SIO
T16
DBG
PORT
SIO
T16
DBG
PORT
SIO
BBCU
DBG
PORT
SIO
BBCU
DBG
PORT
SIO
BBCU
DBG
PORT
SIO
CARD
DBG
PORT
SIO
CARD
DBG
Debug Pin List
Pin name
DSIO
DCLK
DST2
DST0
P65
DST1
P66
DPCO
P67
Pin No.
I/O
QFP
PFBGA
169
C5
I/O
176
A4
O (H)
172
D5
O (L)
170
B5
I/O
(H)
171
A5
I/O
(H)
174
B4
I/O
(H)
Pull-up
Function
Pull-up
–
–
∗1
Serial input/output for debugging
DCLK signal output for debugging
DST2 signal output for debugging
DST0: DST0 signal output for debugging (default)
P65: General-purpose I/O port
DST1: DST1 signal output for debugging (default)
P66: General-purpose I/O port
DPCO: DPCO signal output for debugging (default)
P67: General-purpose I/O port
∗1
∗1
EPSON
Module
DBG
DBG
DBG
DBG
PORT
DBG
PORT
DBG
PORT
11
S1C33401
Other Pin List
OSC1
Pin No.
QFP
PFBGA
141
A13
OSC2
OSC3
142
149
A12
A10
O
I
OSC4
VCP
CMU_CLK
P63
BCLK
T8UF5
#RESET
#NMI
TST0
TST1
BURNIN
SCANEN
#STBY
150
144
28
A9
C11
H1
O
O
I/O
155
156
152
153
147
148
140
D8
B8
C9
B9
C10
B10
B13
I
I
I
I
I
I
I
Pin name
I/O
I
PullFunction
up/down
Low speed (OSC1) oscillator input
–
(32 kHz crystal or external clock input with VDD level)
Low speed (OSC1) oscillator output
–
High speed (OSC3) oscillator input
–
(crystal/ceramic or external clock input with VDD level)
High speed (OSC3) oscillator output
–
PLL analog monitor (used for current monitor)
–
CMU_CLK: CMU external clock output (default)
∗1
P63:
General-purpose I/O port
BCLK:
Bus clock output
T8UF5:
8-bit timer 5 output
Pull-up Initial reset input pin
Pull-up NMI request input pin
Pull-down Test input pin 0 (Connect to VSS during normal operation)
Pull-down Test input pin 1 (Connect to VSS during normal operation)
Wafer level burn-in test enable input
–
Pull-down Scan test enable input
Standby input for disabling C33 operation (except RTC)
–
Module
OSC
OSC
OSC
OSC
CMU
CMU
PORT
BBCU
T8
CMU
CMU
–
–
–
–
RTC
∗1: These pins can have pull-ups enabled or disabled by setting the pin control registers. (Pull-ups are enabled by default.)
∗2: These pins come with a bus hold latch.
Notes: • The # prefixed to pin names indicates that input/output signals of the pin are active low.
• The pin names and I/O printed in boldface denote the default pin (signal) name and default input/output direction.
• (H) and (L) for I/O indicate the default output level. This is only indicated for signals whose level is fixed high or low when the chip is
initially reset.
• The input level must be VDD only for the OSC1 and OSC3 pins. Input levels for other pins should be VDDE (AVDD, TMVDD) level.
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson
reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any
inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material
is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted
by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any
patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade
and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2007, All right reserved.
SEIKO EPSON CORPORATION
■ EPSON Electronic Devices Website
SEMICONDUCTOR OPERATIONS DIVISION
IC Sales Dept.
IC International Sales Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-42-587-5814 FAX: +81-42-587-5117
Document code: 410036601
Issue June, 2007
Printed in Japan