S1C88655 8-bit Single Chip Microcomputer ● Original Architecture Core CPU ● Built-in Font Data ROM for Kanji and Hangul (512K bytes) ● Dot-matrix LCD Driver (128 × 64) ■ DESCRIPTION The S1C88655 is an 8-bit microcomputer for portable equipment with an LCD display that has a built-in LCD controller/driver and a font data ROM. The LCD controller/driver contains an LCD drive power supply circuit and can drive a maximum of 128 × 64-dot LCD panel. The S1C88655 has a built-in large-capacity ROM that can store various font data*. This microcomputer features low-voltage (1.8 V) and high-speed (8.2 MHz) operations as well as low-current consumption, for instance, 2 µA in standby mode (HALT mode during 32 kHz operation with crystal oscillation circuit). The S1C88655 is suitable for display modules such as PDAs and data banks that require an general-purpose LCD driver in conventional systems as well as portable CD/MD players and solid audio equipment with low-power and small-footprint. ∗ Fonts supported • 12 × 12-dot Japanese font (JIS level-1 and level-2, other characters) • 12 × 12-dot Korean font (KSX1001) Please contact Seiko Epson for more information on the fonts provided. ■ FEATURES ● Core CPU .............................................. S1C88 (MODEL3) CMOS 8-bit core CPU ● Main (OSC3) oscillation circuit ............. Crystal/ceramic oscillation circuit 8.2MHz (Max.) or CR oscillation circuit 2.2MHz (Max.)∗1 ● Sub (OSC1) oscillation circuit ............... Crystal oscillation circuit 32.768kHz (Typ.) or CR oscillation circuit 200kHz (Max.)∗1 ● Instruction set ........................................ 608 types (usable for multiplication and division instructions) ● Min. instruction execution time ............. 0.244µsec/8.2MHz (2-clock) ● Internal ROM capacity .......................... Program ROM: 48K bytes Font data ROM: 512K bytes (can be used for a program/data ROM) ● Internal RAM capacity ........................... RAM: 8K bytes Display memory: 2K bytes (8192 bits per screen × 2) ● Bus line ................................................. Address bus: 20 bits Data bus: 8 bits _____ CE signal: 4 bits (1MB addressing range × 4) _____ WR signal: 1 bit _____ RD signal: 1 bit (also usable as general output ports when not used for the bus) ● Output port ............................................ 0–3 bits (when the external bus is used) 26 bits (when the external bus is not used) ● I/O port .................................................. 16 bits (when the external bus is used) 24 bits (when the external bus is not used) (CMOS or Schmitt inputs∗1, With or without pull-up resistors∗1) ● Serial interface ...................................... 2 ch. (optional clock synchronous system or asynchronous system) ● Timer ..................................................... Programmable timer: 16 bits (8 bits × 2) 4 ch. (with PWM waveform, SIF and LCD driver clock output functions) Clock timer: 1 ch. ● LCD driver ............................................. Dot matrix type 128 segments × 64 commons Built-in LCD power supply circuit (boosting: ×2, ×3, ×4, and ×5) S1C88655 ● Watchdog timer ..................................... Overflow cycle (1–4 seconds) and output signal (NMI or reset) are selectable∗1 ● Supply voltage detection (SVD) circuit .... 13 value programmable (1.8V to 2.7V) ● Reset voltage detection (RVD) circuit ..... Supply voltage level reset (1.6V, power-on reset function) with enable/disable option∗1 ● Interrupt ................................................. External interrupt: Input port interrupt (with noise rejector) 1 system (8 types) Internal interrupt: Timer interrupt 5 systems (20 types) Serial interface interrupt 2 systems (6 types) ● Supply voltage ...................................... 1.8V to 3.6V (internal voltage VD1 = 1.8V) ● Current consumption (Typ.) .................. SLEEP mode: 0.7µA HALT mode (32kHz OSC1 crystal, LCD OFF): 2µA HALT mode (32kHz OSC1 CR, LCD OFF): 7µA Run mode (32kHz OSC1 crystal, LCD OFF): 5µA Run mode (2MHz OSC3 CR, LCD OFF): 350µA Run mode (8MHz OSC3 ceramic, LCD OFF): 800µA RVD circuit operating current (VDD = 3.6V): 1.5µA SVD circuit operating current (VDD = 3.6V): 5µA LCD circuit operating current (VDD = 3.0V, OSC1 = 32kHz, triple boosted, VC5 = 8V) White screen displayed: 50µA Checker pattern displayed: 120µA ● Supply form ........................................... AU-bump chip or TCM∗2 ∗1: Can be selected with mask option ∗2: TCM (Tape Carrier Module): FPC (Flexible Printed Circuit) modules that include peripheral circuit parts as well as the IC main unit ■ BLOCK DIAGRAM Core CPU S1C88 OSC1, 2 Oscillator Interrupt Controller System Controller I/O Port Reset/Test (Voltage detection & power on reset) Serial Interface Watchdog Timer Programmable Timer OSC3, 4 MCU/MPU BREQ (P24) BACK (P25) RESET TEST Clock Timer External Memory Interface Supply Voltage Detector VDD VSS VD1 VD2 VC1–VC5 CA1P, CA1M, CA2P, CA2M, CA3P, CA4P 2 Output Port Internal & LCD Power Generator P00–P07 (D0–D7) P10 (SIN0) P11 (SOUT0) P12 (SCLK0) P13 (SRDY0) P14 (SIN1) P15 (SOUT1) P16 (SCLK1) P17 (SRDY1) P20 (TOUT0/TOUT1) P21 (TOUT2/TOUT3) P22 (FOUT) P23 (TOUT2/TOUT3) P24 (BREQ/EXCL0) P25 (BACK/EXCL1) P26 (CL/EXCL2) P27 (FR/EXCL3) R00–R07 (A0–A7) R10–R17 (A8–A15) R20–R23 (A16–A19) R24, R25 (RD, WR) R30–R33 (CE0–CE3) SEG0–SEG127 LCD Driver COM0–COM63 ROM 48K bytes Display Data RAM 8192 x 2 bits ROM (for Font Data) 512K bytes RAM 8K bytes S1C88655 ■ PAD LAYOUT DIAGRAM 1 95 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 Upper left alignment mark ( ) CA655Dxxx 300 Die No. 105 295 110 Y 290 115 285 X (0, 0) 120 280 125 3.7 mm 100 90 275 130 270 Lower right alignment mark ( ) 135 140 145 150 155 160 165 170 175 180 185 190 195 200 205 210 215 220 225 230 235 240 245 250 255 260 11.7 mm Chip size) 11.7 × 3.7 mm Chip thickness) 725 µm Pad size) No. 1–98: 82 × 82 µm, No. 99–134: 100 × 54 µm, No. 135–266: 54 × 100 µm, No. 267–302: 100 × 54 µm Bump pitch) No. 1–98: 100 µm (Min.), No. 99–302: 80 µm (Min.) Bump height) 22.5 µm Alignment mark coordinates) Upper left corner: (-5560, 1660), Lower right corner: (5569, -1569) 265 N.C. ■ PIN DESCRIPTION Pad No. Pad name 11, 38, 74 VDD 14, 21, 75, 85 VSS 15 VD1 80, 84 VD2 86–90 VC1–VC5 79, 78, 83, CA1P, CA1M, CA2P, 82, 77, 81 CA2M, CA3P, CA4P 13 OSC1 12 OSC2 17 OSC3 16 OSC4 19 MCU/MPU 47–54 R00–R07/A0–A7 55–62 R10–R17/A8–A15 63–66 R20–R23/A16–A19 67 R24/RD 68 R25/WR 69–72 R30–R33/CE0–CE3 46–39 P00–P07/D0–D7 37 P10/SIN0 36 P11/SOUT0 35 P12/SCLK0 34 P13/SRDY0 33 P14/SIN1 32 P15/SOUT1 31 P16/SCLK1 30 P17/SRDY1 29 P20/TOUT0/TOUT1 28 P21/TOUT2/TOUT3 27 P22/FOUT 26 P23/TOUT2/TOUT3 In/Out – – – – – – Init* – – – – – – I O I O I O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I O I (Pull-up) O (H) O (H) O (H) O (H) O (H) O (H) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) Function Power supply (+) terminal Power supply (GND) terminal Internal logic and oscillation system voltage regulator output terminal LCD circuit power voltage booster output terminal LCD drive voltage output terminals LCD voltage booster capacitor connection terminals OSC1 oscillation input terminal (select crystal/CR oscillation by mask option) OSC1 oscillation output terminal OSC3 oscillation input terminal (select crystal/ceramic/CR oscillation by mask option) OSC3 oscillation output terminal MCU/MPU mode setup terminal Output terminals (R00–R07) or address bus (A0–A7) Output terminals (R10–R17) or address bus (A8–A15) Output terminals (R20–R23) or address bus (A16–A19) Output terminal (R24) or read signal output terminal (RD) Output terminal (R25) or write signal output terminal (WR) Output terminals (R30–R33) or chip enable signal output terminals (CE0–CE3) I/O terminals (P00–P07) or data bus (D0–D7) I/O terminal (P10) or serial I/F Ch. 0 data input terminal (SIN0) I/O terminal (P11) or serial I/F Ch. 0 data output terminal (SOUT0) I/O terminal (P12) or serial I/F Ch. 0 clock I/O terminal (SCLK0) I/O terminal (P13) or serial I/F Ch. 0 ready signal output terminal (SRDY0) I/O terminal (P14) or serial I/F Ch. 1 data input terminal (SIN1) I/O terminal (P15) or serial I/F Ch. 1 data output terminal (SOUT1) I/O terminal (P16) or serial I/F Ch. 1 clock I/O terminal (SCLK1) I/O terminal (P17) or serial I/F Ch. 1 ready signal output terminal (SRDY1) I/O terminal (P20) or programmable timer underflow signal output terminal (TOUT0/TOUT1) I/O terminal (P21) or programmable timer underflow signal output terminal (TOUT2/TOUT3) I/O terminal (P22) or clock output terminal (FOUT) I/O terminal (P23) or programmable timer underflow inverted signal output terminal (TOUT2/TOUT3) 25 I (Pull-up) I/O terminal (P24), bus request signal input terminal (BREQ) P24/BREQ/EXCL0 I/O or programmable timer external clock input terminal (EXCL0) 24 I (Pull-up) I/O terminal (P25), bus acknowledge signal output terminal (BACK) P25/BACK/EXCL1 I/O or programmable timer external clock input terminal (EXCL1) 23 I (Pull-up) I/O terminal (P26), LCD clock output terminal (CL) P26/CL/EXCL2 I/O or programmable timer external clock input terminal (EXCL2) 22 I (Pull-up) I/O terminal (P27), LCD frame signal output terminal (FR) P27/FR/EXCL3 I/O or programmable timer external clock input terminal (EXCL3) O (L) COM0–COM63 LCD common output terminals 132–101, 269–300 O O (L) SEG0–SEG127 LCD segment output terminals 137–264 O I (Pull-up) Initial reset input terminal RESET 20 I I (Pull-up) Test input terminal TEST 18 I ∗ (Pull-up): Pulled up (Hi-Z when Gate Direct is selected by mask option), (H): HIGH level output, (L): LOW level output 3 S1C88655 ■ BASIC EXTERNAL CONNECTION DIAGRAM RCR1 OSC1 COM63 ∗1 CG1 COM0 VSS ∗2 panel 128 x 64 SEG127 SEG0 LCD R00–R07 (A0–A7) R10–R17 (A8–A15) R20–R23 (A16–A19) X'tal1 RCR3 ∗4 ∗3 CG3 OSC2 OSC3 R24 (RD) R25 (WR) R30–R33 (CE0–CE3) X'tal3 or Ceramic CD3 ∗5 C1 C2 C3 C4 C5 C6 Open OSC4 VD1 VD2 CA3P CA1M CA1P CA4P CA2M CA2P VC1 VC2 VC3 VC4 VC5 S1C88655 [The potential of the substrate (back of the chip) is VSS.] RESET ( Cres ) 1.8 V | 3.6 V P00–P07 (D0–D7) P10 (SIN0) P11 (SOUT0) P12 (SCLK0) P13 (SRDY0) P14 (SIN1) Recommended values for external parts Symbol Name Recommended value X'tal1 Crystal oscillator 32.768 kHz CG1 Trimmer capacitor 0–25 pF RCR1 Resistor for 1.5 MΩ CR oscillation X'tal3 Crystal oscillator 4 MHz Ceramic Ceramic oscillator 4 MHz CG3 Gate capacitor 15 pF (Crystal) Drain capacitor RCR3 Resistor for C1 CR oscillation Capacitor between 0.1 µF VSS and VD1 P15 (SOUT1) P16 (SCLK1) P17 (SRDY1) P20 (TOUT0/TOUT1) P21 (TOUT2/TOUT3) P22 (FOUT) P23 (TOUT2/TOUT3) P24 (BREQ/EXCL0) P25 (BACK/EXCL1) C2 C3~C6 CP Cres Capacitor between 1.0–4.7 µF VSS and VD2 Booster capacitor 1.0–4.7 µF Capacitor for 3.3 µF power supply Capacitor for 0.47 µF RESET terminal P26 (CL/EXCL2) P27 (FR/EXCL3) P + C 30 pF (Ceramic) 15 pF (Crystal) 30 pF (Ceramic) 39 kΩ CD3 (Not required when the reset voltage detection circuit is VDD TEST used.) ∗1: OSC1 = Crystal oscillation ∗2: OSC1 = CR oscillation ∗3: OSC3 = Crystal or Ceramic oscillation ∗4: OSC3 = CR oscillation ∗5: Example for VD2 = 5 × VDD (VD2 > VC5) The external circuit configuration depends on the supply voltage and LCD drive voltage values. Note: The above table is simply an example, and is not guaranteed to work. NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. © Seiko Epson Corporation 2006, All right reserved. SEIKO EPSON CORPORATION SEMICONDUCTOR OPERATIONS DIVISION IC Sales Dept. IC International Sales Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone : +81-42-587-5814 FAX : +81-42-587-5117 ■ EPSON Electronic Devices Website http://www.epsondevice.com Document code: 410757901 Issue September, 2006 Printed in Japan L