CY23FS08 Failsafe™ 2.5V/ 3.3V Zero Delay Buffer Features • • • • • • • • • • • • • • Functional Description Internal DCXO for continuous glitch-free operation Zero input-output propagation delay Low jitter (< 35 ps RMS) outputs Low output-output skew (< 200 ps) 1 MHz–200 MHz reference input Supports industry standard input crystals 200 MHz (commercial), 166 MHz (industrial) outputs 5V-tolerant inputs Phase-locked loop (PLL) Bypass Mode Dual Reference Inputs 28-pin SSOP Split 2.5V or 3.3V output power supplies 3.3V core power supply Industrial temperature available The CY23FS08 is a FailSafe™ Zero Delay Buffer with two reference clock inputs and eight phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. Continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS08 is that the DCXO is in fact the primary clocking source, which is synchronized (phase-aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal, which will be connected to the DCXO must be chosen to be an integer factor of the frequency of the reference clock. This factor is set by four select lines: S[4:1]. please see Table 1. The CY23FS08 has three split power supplies; one for core, another for Bank A outputs and the third for Bank B outputs. Each output power supply, except VDDC can be connected to either 2.5V or 3.3V. VDDC is the power supply pin for internal circuits and must be connected to 3.3V. Block Diagram Pin Configuration REF1 REFSEL REF2 DCXO VSSB CLKB1 REF1 4 FailsafeTM REF2 Block PLL CLKA[1:4] 4 CLKB[1:4] FBK S2 S3 VDDB VSSB CLKB3 Decoder FAIL# /SAFE S[4:1] CLKB2 4 CLKB4 VDDB VDDC XIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CY23FS08 XIN XOUT 28 27 26 25 24 23 22 21 20 19 18 17 16 15 REFSEL FBK VSSA CLKA1 CLKA2 S1 S4 VDDA VSSA CLKA3 CLKA4 VDDA FAIL#/SAFE XOUT 28 pin SSOP Cypress Semiconductor Corporation Document #: 38-07518 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised May 12, 2004 CY23FS08 Pin Definitions Pin Number Pin Name Description inputs[4] 1,2 REF1,REF2 5V-tolerant, reference clock 4,5,10,11 CLKB[1:4] Bank B clock outputs.[1,2] 25,24,19,18 CLKA[1:4] Bank A clock outputs.[1,2] 27 FBK Feedback input to the PLL.[1,4] 23,6,7,22 S[1:4] Frequency select pins/PLL and DCXO bypass.[3] 14 XIN Reference crystal input. 15 XOUT Reference crystal output. 16 FAIL#/SAFE Valid reference indicator. A high level indicates a valid reference input. 13 VDDC 3.3V power supply for the internal circuitry. 8,12 VDDB 2.5V or 3.3V power supply for Bank B outputs. 3,9 VSSB Ground. 17,21 VDDA 2.5V or 3.3V power supply for Bank A outputs. 20,26 VSSA Ground. 28 REFSEL Reference select. Selects the active reference clock from either REF1 or REF2. REFSEL = 1, REF1 is selected, REFSEL = 0, REF2 is selected. . Table 1. Configuration Table XTAL (MHz) S[4:1] REF(MHz) OUT(MHz) Max. Min. Max. Min. 1000 8.33 30 16.67 60.00 8.33 30.00 ÷2 0000 Max. REF:OUT ratio Min. REF:XTAL ratio Out:XTAL ratio PLL and DCXO Bypass mode 2 1 1110 9.50 30 57.00 180.00 28.50 90.00 ÷2 6 3 0101 8.50 30 6.80 24.00 1.70 6.00 ÷4 4/5 1/5 1011 8.33 30 25.00 90.00 6.25 22.50 ÷4 3 3/4 0011 8.33 30 2.78 10.00 2.78 10.00 x1 1/3 1/3 1001 8.33 30 8.33 30.00 8.33 30.00 x1 1 1 1111 8.00 25 32.00 100.00 32.00 100.00 x1 4 4 1100 8.00 25 64.00 200.00 64.00 200.00 x1 8 8 0001 8.33 30 1.04 3.75 2.08 7.50 x2 1/8 1/4 0110 8.33 30 4.17 15.00 8.33 30.00 x2 1/2 1 1101 8.33 30 16.67 60.00 33.33 120.00 x2 2 4 0100 8.33 30 4.17 15.00 16.67 60.00 x4 1/2 2 1010 8.33 30 12.50 45.00 50.00 180.00 x4 3/2 6 0010 8.33 30 1.39 5.00 11.11 40.00 x8 1/6 4/3 0111 8.33 30 6.25 22.50 50.00 180.00 x8 3/4 6 Notes: 1. For normal operation, connect either one of the eight clock outputs to the FBK input. 2. Weak pull-downs on all outputs. 3. Weak pull-ups on these inputs. 4. Weak pull-downs on these inputs. Document #: 38-07518 Rev. *A Page 2 of 12 CY23FS08 FailSafe Function The CY23FS08 is targeted at clock distribution applications that could or which currently require continued operation should the main reference clock fail. Existing approaches to this requirement have utilized multiple reference clocks with either internal or external methods for switching between references. The problem with this technique is that it leads to interruptions (or glitches) when transitioning from one reference to another, often requiring complex external circuitry or software to maintain system stability. The technique implemented in this design completely eliminates any switching of references to the PLL, greatly simplifying system design. The CY23FS08 PLL is driven by the crystal oscillator, which is phase-aligned to an external reference clock so that the output of the device is effectively phase-aligned to reference via the external feedback loop. This is accomplished by utilizing a digitally controlled capacitor array to pull the crystal frequency over an approximate range of +300 ppm from its nominal frequency. REF O UT F A IL # /S A F E tF S H tF S L Figure 1. Fail#/Safe Timing for Input Reference Failing Catastrophically t F S L (m a x ) = 2 ( tR E F x n ) + 25ns F n = R E F = 4 ( in a b o v e e x a m p le ) F XTAL t F S H ( m in ) = 12( tR E F x n ) + 25ns Figure 2. Fail#/Safe Timing Formula Table 2. FailSafe Timing Table Parameter Description Conditions tFSL Fail#/Safe Assert Delay Measured at 80% to 20%, Load = 15 pF tFSH Fail#/Safe Deassert Delay Measured at 80% to 20%, Load = 15 pF In this mode, should the reference frequency fail (i.e., stop or disappear), the DCXO maintains its last setting and a flag signal (FAIL#/SAFE) is set to indicate failure of the reference clock. The CY23FS08 provides four select bits, S1 through S4 to control the reference to crystal frequency ratio. The DCXO is internally tuned to the phase and frequency of the external reference only when the reference frequency divided by this Document #: 38-07518 Rev. *A Min. See Figure 2 Max. Unit See Figure 2 ns ns ratio is within the DCXO capture range. If the frequency is out of range, a flag will be set on the FAIL#/SAFE pin notifying the system that the selected reference is not valid. If the reference moves in range, then the flag will be cleared, indicating to the system that the selected reference is valid. Page 3 of 12 CY23FS08 Reference + 300 ppm Reference Reference - 300 ppm Frequency Reference Off Output + 300 ppm Output Output - 300 ppm Volt Fail#/Safe tFSH tFSL Time Figure 3. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range Failsafe typical frequency settling time OUTPUT FREQUENCY DELTA (ppm) Initial valid Ref1=20MHz +100ppm, then switching to REF2=20MHz 150 100 50 0 0 0.45 1.3 2.5 SETTLING TIME (ms) Figure 4. FailSafe Reference Switching Behavior Document #: 38-07518 Rev. *A Page 4 of 12 CY23FS08 Figure 5. FailSafe Effective Loop Bandwidth (min) REF1 REF2 REFSEL 0 ms 0 d eg -1 8 0 d e g 0 ms 1 .4 m s Figure 6. Sample Timing of Muxing Between Two Reference Clocks 180°C Out of Phase and Resulting Output Phase Offset Typical Settling Time (105 MHz) Document #: 38-07518 Rev. *A Page 5 of 12 CY23FS08 190fs/cy 0 0ms 190 fsec/cycle = 0.125 mradian/cycle 1.4 ms Figure 7. Resulting Output Dphase/Cycle Typical Rate of Change (105 MHz) D u ty C y c le - t D C V D D /2 V D D /2 V D D /2 V DD 0V t1 t2 S le w R a te - t (S R ) 80% V DD 80% 20% 20% 0V t S R (O ) t S R (O ) O u tp u t-O u tp u t S k e w - t S K (O ) V D D /2 V D D /2 t S K (O ) P a rt to P a rt S k e w - t S K (P P ) FBK, P a rt 1 V D D /2 FBK, P a rt 2 V D D /2 t S K (P P ) S ta tic P h a s e O ffs e t - t (φ ) REF V D D /2 FBK V D D /2 t (φ ) Document #: 38-07518 Rev. *A Page 6 of 12 CY23FS08 XTAL Selection Criteria and Application Example C1 is the XTAL motional capacitance (10 fF – 30 fF typ). Choosing the appropriate XTAL will ensure the FailSafe device will be able to span an appropriate frequency of operation. Also, the XTAL parameters will determine the holdover frequency stability. Critical parameters are as follows. Our recommendation is to choose: • Low C0/C1 ratio (240 or less) so that the XTAL has enough range of pullability. • Low temperature frequency variation • Low manufacturing frequency tolerance • Low aging. C0 is the XTAL shunt capacitance (3 pF – 7 pF typ.). The capacitive load as “seen” by the XTAL is across its terminals. It is named Clmin (for minimum value), and Clmax (for maximum value).These are used for calculating the pull range. Example:[5] Please note that the Cl range “center” is approximately 20 pF, but we may not want a XTAL calibrated to that load. This is because the pullability is not linear, as represented in the equation above. Plotting the pullability of the XTAL shows this expected behavior as shown in Figure 8. In this example, specifying a XTAL calibrated to 14 pF load provides a balanced ppm pullability range around the nominal frequency. Clmin = (12 pF IC input cap + 0 pF pulling cap+ 6 pF trace cap on board)/2 = 9 pF Clmax = (12 pF IC input cap + 48 pF pulling cap+ 6 pF trace cap on board)/2 = 33 pF Pull Range =(fClmin–fClmax)/fClmin = ((C1)/2)[(1/(C0+Clmin))–(1/(C0+Clmax))] Pull Range in ppm = ((C1)/2)[(1/(C0+Clmin))–(1/(C0+Clmax))] × 106 Pullability Range Vs. Cload (Normalized to 14pF Cload) Delta Freq. from nom 400.00 300.00 200.00 100.00 0.00 C0/C1 = 200 -100.00 C0/C1 = 300 C0/C1 = 400 -200.00 -300.00 -400.00 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 Cload (pF) Figure 8. Frequency vs. Cload Behavior for Example XTAL Notes: 5. The above example shows the maximum range the FailSafe internal capacitor array is capable of (0 to 48.6 pF).Cypress recommends the min./max capacitor array values be programmed to a narrower range such as 6 pF–30 pF, or 7.5 pF–27 pF. This ensures the XTAL operates between series resonance and anti-resonance. Please contact Cypress for choosing these range settings. Document #: 38-07518 Rev. *A Page 7 of 12 CY23FS08 Table 3. Pullability Range from XTAL with Different C0/C1 Ratio Calculating the capture range involves subtracting error tolerances as follows: Parameter ........................................................ f error (ppm) C0/C1 Ratio Cload(min.) Cload(max.) Pullability Range 200 8.0 32.0 –385 333 Temperature stability ..........................................................30 300 8.0 32.0 –256 222 Aging ................................................................................... 3 400 8.0 32.0 –192 166 Board/trace variation ........................................................... 5 Calculated value of the pullability range for the XTAL with C0/C1 ratio of 200, 300 and 400 are shown in Table 3. For this calculation Cl(min) = 8pF and Cl(max)= 32pF has been used. Using a XTAL that has a nominal frequency specified at load capacitance of 14pF, almost symmetrical pullability range has been obtained. Next, it is important to calculate the pullability range including error tolerances. This would be the capture range of the input reference frequency that the FailSafe device and XTAL combination would reliably span. Manufacturing frequency tolerance ...................................15 Total ....................................................................................53 Example: Capture Range for XTAL with C0/C1 Ratio of 200 Negative Capture Range= –385 ppm + 53 ppm = –332 ppm Positive Capture Range = 333 ppm – 53 ppm = +280 ppm It is important to note that the XTAL with lower C0/C1 ratio has wider pullability/capture range as compared to the higher C0/C1 ratio. This will help the user in selecting the appropriate XTAL for use in the FailSafe application. Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD+0.5 VDC TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Commercial Grade 0 70 °C 85 °C TJ Temperature, Junction Functional 125 °C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 36.17 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) 100.6 °C/W UL–94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level Industrial Grade –40 2000 V V–0 1 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Recommended Pullable Crystal Specifications[6] Parameter Name Comments Min. Typ. Max. Unit Parallel resonance, fundamental mode, AT cut 8.00 – 30.00 MHz FNOM Nominal crystal frequency CLNOM Nominal load capacitance – 14 – pF R1 Equivalent series resistance (ESR) Fundamental mode – – 25 Ω R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR Ratio used because typical R1 values are much less than the maximum spec 3 – – DL Crystal drive level No external series resistor assumed – 0.5 2 mW F3SEPLI Third overtone separation from 3*FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 fF Note: 6. Ecliptek ECX-5788-13.500M, ECX-5807-19.440M, ECX-5872-19.53125M, ECX-5806-18.432M, ECX-5808-27.000M, ECX-5884-17.664M, ECX-5883-16.384M,ECX-5882-19.200M,ECX-5880-24.576M meet these specifications. Document #: 38-07518 Rev. *A Page 8 of 12 CY23FS08 Table 4. Operating Conditions for FailSafe Commercial/Industrial Temperature Devices Parameter Description Min. Max. Unit VDDC 3.3V Supply Voltage 3.135 3.465 V VDDA, VDDB 2.5V Supply Voltage Range 2.375 2.625 V 3.3V Supply Voltage Range 3.135 3.465 TA Ambient Operating Temperature, Commercial 0 Ambient Operating Temperature, Industrial CL V 70 –40 °C 85 °C Output Load Capacitance (Fout < 100 MHz) 30 pF Output Load Capacitance (Fout > 100 MHz) 15 pF CIN Input Capacitance (except XIN) 7 pF CXIN Crystal Input Capacitance (all internal caps off) TPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 10 13 pF 500 ms Table 5. Electrical Characteristics for FailSafe Commercial/Industrial Temperature Devices Parameter Description Test Conditions Min. Typ. Max. Unit 0.3xVDD V 50 µA VIL Input Low Voltage VIH Input High Voltage CMOS Levels, 70% of VDD IIL Input Low Current VIN=VSS (100k pull-up only) IIH Input High Current VIN=VDD (100k pull-down only) IOL Output Low Current VOL=0.5V, VDD= 2.5V VOL=0.5V, VDD= 3.3V 20 mA IOH Output High Current VOH=VDD–0.5V, VDD= 2.5V 18 mA VOH=VDD–0.5V, VDD = 3.3V 20 IDDQ Quiescent Current All Inputs grounded, PLL and DCXO in bypass mode, Reference Input = 0 CMOS Levels, 30% of VDD 0.7xVDD V 50 µA 18 mA mA 250 µA Table 6. Switching Characteristics for FailSafe Commercial/Industrial Temperature Devices Parameter[8] fREF fOUT Description Reference Frequency Output Frequency Test Conditions Min. Max. Unit Commercial Grade 1.04 200 MHz Industrial Grade 1.04 166.7 MHz 15-pF Load, Commercial Grade 1.70 200 MHz 15-pF Load, Industrial Grade 1.70 166.7 MHz fXIN DCXO Frequency 8.0 30 MHz tDC Duty Cycle Measured at VDD/2 47 53 % tSR(I) Input Slew Rate Measured on REF1 Input, 30% to 70% of VDD 0.5 4.0 V/ns tSR(O) Output Slew Rate Measured from 20% to 80% of VDD = 3.3V, 15 pF Load 0.8 4.0 V/ns Measured from 20% to 80% of VDD =2.5V, 15 pF Load 0.4 tSK(O) Output to Output Skew All outputs equally loaded, measured at VDD/2 tSK(IB) Intrabank Skew tSK(PP) Part to Part Skew t(φ)[7] tD(φ)[7] tJ(CC) tLOCK 3.0 V/ns 200 ps All outputs equally loaded, measured at VDD/2 75 ps Measured at VDD/2 500 ps Static Phase Offset Measured at VDD/2 250 ps Dynamic Phase Offset Measured at VDD/2 200 ps Cycle-to-Cycle Jitter Load = 15 pF, fOUT ≥ 6.25 MHz 200 ps 35 psRMS 1.0 ms PLL Lock Time Stable power supply, valid clock at REF Note: 7. The t(φ) reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as tSR(I) is maintained. 8. Parameters guaranteed by design and characterization, not 100% tested in production. 9. Includes typical board trace capacitance of 6–7pF each XIN, XOUT. Document #: 38-07518 Rev. *A Page 9 of 12 CY23FS08 Ordering Information Part Number Package Type Product Flow CY23FS08OI 28-pin SSOP Industrial, –40°C to 85°C CY23FS08OIT 28-pin SSOP – Tape and Reel Industrial, –40°C to 85°C CY23FS08OC 28-pin SSOP Commercial, 0°C to 70°C CY23FS08OCT 28-pin SSOP – Tape and Reel Commercial, 0°C to 70°C Document #: 38-07518 Rev. *A Page 10 of 12 CY23FS08 Package Drawing and Dimensions 28-Lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C FailSafe is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07518 Rev. *A Page 11 of 12 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. CY23FS08 Document History Page Document Title: CY23FS08 Failsafe™ 2.5V/ 3.3V Zero Delay Buffer Document #: 38-07518 Rev. *A Issue Date REV. ECN NO. ** 123699 04/23/03 *A 224067 See ECN Document #: 38-07518 Rev. *A Orig. of Change RGL Description of Change New Data Sheet RGL/ZJX Changed the XTAL Specifications table. Page 12 of 12