ADVANCE INFORMATION CY26049-5 FailSafe™ PacketClock™ Global Communications Clock Generator Features Benefits • Fully integrated phase-locked loop (PLL) • FailSafe output • PLL driven by a crystal oscillator that is phase aligned with external reference • 76.8-MHz output from 19.2-MHz input • Low-jitter, high-accuracy outputs • 3.3V ± 5% operation • 16-lead TSSOP • Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external loop filter components • When reference is off, DCXO maintains clock outputs and SAFE pin indicates FailSafe conditions • DCXO maintains continuous operation should the input reference clock fail • Glitch-free transition simplifies system design • Works with commonly available, low-cost 19.2-MHz crystal • Zero-ppm error for all output frequencies • Compatible across industry standard design platforms • Industry standard package with 6.4 × 5.0 mm2 footprint and a height profile of just 1.1 mm Logic Block Diagram e xte rn a l p u lla b le c rysta l (1 9 .2 M H z) X IN XOUT in p u t r e fe re n ce (1 9 .2 M H z) IC L K F A IL S A F E T M CONTROL D IG IT A L C O N TR O LLE D C R YSTAL O S C IL L A T O R PHASE LO C K E D LO O P O U TPU T D IV ID E R CLKA 7 6 .8 M H z SA FE IC L K d e te cte d Cypress Semiconductor Corporation Document #: 38-07485 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 8, 2003 ADVANCE INFORMATION CY26049-5 Pin Configuration CY26049-5 16-pin TSSOP Top View ICLK 1 16 NC NC 2 15 NC NC 3 14 NC NC 4 13 NC VDD 5 12 VDD VSS 6 11 VSS CLKA 7 10 SAFE XIN 8 9 XOUT Pin Description Pin Number Pin Name 1 ICLK Pin Description Reference Input Clock; 19.2 MHz. 2 NC No Connect. 3 NC No Connect. 4 NC 5 VDD 6 VSS 7 CLKA No Connect. Voltage Supply; 3.3V. Ground. Clock Output; 76.8 MHz. 8 XIN 9 XOUT Pullable Crystal Input; 19.2 MHz. Pullable Crystal Output; 19.2 MHz. 10 SAFE High = reference ICLK within range, Low = reference ICLK out of range. 11 VSS Ground. 12 VDD Voltage Supply; 3.3V. 13 NC No Connect. 14 NC No Connect. 15 NC No Connect. 16 NC No Connect. Selector Guide Part Number Input Frequency Range CY26049ZC-5 Reference Input Clock: 19.2 MHz Crystal: 19.2-MHz pullable Crystal per Cypress Specification Description CY26049-5 is a FailSafe frequency synthesizer with a reference clock input and 76.8-MHz output. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The continuous, glitch-free operation is achieved by using a DCXO, which serves as a primary clock source. The FailSafe control circuit synchronizes the DCXO oscillator with the reference as long as the reference is within the pull range of the crystal. Document #: 38-07485 Rev. *A Outputs Output Frequencies 1 76.8 MHz In the event of a reference clock failure the DCXO maintains the last frequency of the reference clock. The unique feature of the CY26049-5 is that the DCXO is in fact the primary clocking source. When the reference clock is restored, the DCXO automatically resynchronizes to the reference. The status of the reference clock input, as detected by the CY26049-5, is reported by the SAFE pin. Page 2 of 6 ADVANCE INFORMATION CY26049-5 Data Retention @ Tj=125°C.................................. >10 Years Absolute Maximum Conditions Package Power Dissipation....................................... 350mW Supply Voltage (VDD) ........................................–0.5 to +7.0V ESD (Human Body Model) MIL-STD-883.................... 2000V DC Input Voltage........................................ –0.5V to VDD+0.5 (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature (Non-Condensing) .... –55°C to +125°C Junction Temperature ................................ –40°C to +125°C Recommended Pullable Crystal Specifications Parameter Name Comments Min. Typ. Max. Unit Parallel resonance, fundamental mode, AT cut – 19.2 – MHz – 14 – pF – – 25 Ω 3 – – 0.5 2 FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) Fundamental mode R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR Ratio used because typical R1 values are much less than the maximum spec DL Crystal drive level No external series resistor assumed – F3SEPLI Third overtone separation from 3*FNOM High side 400 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –200 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 mW fF Recommended Operating Conditions Parameter Description Min. Typ. Max. Unit 3.15 3.3 3.45 V Ambient Temperature (Commercial Temperature) 0 – 70 °C Max Output Load Capacitance – – 15 pF 0.05 – 500 ms Min. Typ. Max. Unit 12 24 – mA VDD Operating Voltage TAC CLOAD tpu Power-up time for all VDD’s to reach minimum specified voltage (power ramps must be monotonic) DC Electrical Specifications (Commercial Temp: 0°to 70°C) Parameter Description Test Conditions IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V (source) IOL Output Low Current VOL = 0.5, VDD = 3.3V (sink) 12 24 – mA VIH Input High Voltage CMOS Levels 0.7 – – VDD VIL Input High Voltage CMOS Levels – – 0.3 VDD IIH Input High Current VIH=VDD – 5 10 µA VIL=0V IIL Input Low Current CIN Input Capacitance IDD Supply Current CLOAD = 15 pF, VDD = 3.45V – 5 10 µA – – 7 pF – – 45 mA AC Electrical Specifications (Commercial Temp: 0° to 70° C) Parameter fICLK-E Description Frequency, Input Clock Range[1] Test Conditions Input Clock Frequency, External Mode LR FailSafe Lock DC = t2/t1 Output Duty Cycle Range of reference ICLK for Safe = High TPJIT1 Clock Jitter; output > 5 MHz Period Jitter, Peak to Peak, 10,000 periods Duty Cycle defined in Figure 1, measured at 50% of VDD RMS Period Jitter, RMS Min. Typ. – 19.2 Max. Unit – MHz –250 – 45 50 +250 ppm 55 – – 250 ps – – 50 ps % Note: 1. Dependent on crystals chosen and crystal specs. Document #: 38-07485 Rev. *A Page 3 of 6 ADVANCE INFORMATION CY26049-5 AC Electrical Specifications (Commercial Temp: 0° to 70° C) (continued) Test Conditions Min. Typ. t6 Parameter PLL Lock Time Description Time for PLL to lock within ± 150 ppm of target frequency – – Max. Unit 3 ms tfs_lock FailSafe Lock Time Time for PLL to lock to ICLK (outputs phase aligned with ICLK and Safe = High) – – 7 s ferror Frequency Synthesis Error Actual mean frequency error vs. target – 0 – ppm ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 2 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 2 V/ns Voltage and Timing Definitions t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definition; DC = t2/t1 t4 t3 80% CLK 20% Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4 Test Circuit ICLK 1 16 2 15 3 14 4 13 5 12 VDD VDD 0.1uF 0.1uF 6 11 7 10 8 9 CLKA CLOAD 19.2MHz Ordering Information Ordering Code Package Type Operating Temperature Range CY26049ZC-5 16-lead TSSOP Commercial 0° to 70°C CY26049ZC-5T 16-lead TSSOP—Tape and Reel Commercial 0° to 70°C Document #: 38-07485 Rev. *A Page 4 of 6 ADVANCE INFORMATION CY26049-5 Package Drawing and Dimensions 16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 51-85091-** FailSafe and PacketClock are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07485 Rev. *A Page 5 of 6 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. ADVANCE INFORMATION CY26049-5 Document History Page Document Title: CY26049-5 FailSafe™ PacketClock™ Global Communications Clock Generator Document Number: 38-07485 ECN No. Issue Date Orig. of Change ** 119591 10/31/02 CKN *A 128091 09/10/03 IJA REV. Document #: 38-07485 Rev. *A Description of Change New Data Sheet Changed name from FailSafe Communications Clock Generator to FailSafe PacketClock Global Communications Clock Generator Changed wording in Features and Benefits and Pin Description table Replaced Recommended Pullable Crystal Specifications table Page 6 of 6