TPS92310 www.ti.com SNVS792 – FEBRUARY 2012 TPS92310 Off-Line Primary Side Sensing Controller With PFC Check for Samples: TPS92310 FEATURES DESCRIPTION • The TPS92310 is an off-line controller specifically designed to drive high power LEDs for lighting applications. With the primary side sensing, constant on-time and quasi-resonant switching techniques, the TPS92310 application circuit gives high Power Factor, good EMI performance and high system efficiency. Also, using this device, low external component count application solutions can be designed easily. Power Factor Correction is inherent if the TPS92310 is operated in the constant on-time mode with an adaptive algorithm. The control algorithm of TPS92310 adjusts the on-time with reference to the primary side inductor peak current and secondary side inductor discharge time dynamically, the response time of which is set by an external capacitor. Also, minimized EMI and switching loss is achieved with quasi-resonant switching. Other supervisory features of the TPS92310 include cycleby-cycle primary side inductor current limit, VCC under-voltage lockout, output over-voltage protection and thermal shutdown. The TPS92310 is available in the VSSOP-10 package. 1 2 • • • • • Regulates LED Current Without Secondary Side Sensing Adaptive ON-Time Control With Inherent PFC Critical-Conduction-Mode (CRM) With ZeroCurrent Detection (ZCD) for Valley Switching Programmable Switch Turn ON Delay Programmable Constant ON-Time (COT) and Peak Current Control Over-Temperature Protection APPLICATIONS • • LED Lamps: A19 (E26/27, E14), PAR30/38, GU10 Solid State Lighting Typical Application D3 T1 CIN D1 LED Stack R1 LP LS COUT VLAUX AC IN R4 D2 R2 *Z1 LAUX Y1 R3 CZCD VSW GND TPS92310 CVCC DZCD CCOMP VCC GATE ZCD ISNS AGND PGND COMP MODE1 DLY MODE2 Q1 RISNS RDLY *Optional Figure 1. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS92310 SNVS792 – FEBRUARY 2012 www.ti.com Connection Diagram Top View VCC GATE ZCD ISNS AGND PGND COMP MODE1 DLY MODE2 Figure 2. 10-Pin VSSOP Pin Descriptions 2 Pin Name Description 1 VCC Power supply input Application Information 2 ZCD Zero crossing detection input 3 AGND Small signal ground 4 COMP Compensation network Output of the error amplifier. Connect a capacitor from this pin to ground to set the frequency response of the LED current regulation loop. 5 DLY Delay control input Connect a resistor from this pin to ground to set the delay between switching ON and OFF periods. 6 MODE2 Mode selection input 2 Select operating mode for isolated or non-isolated mode. 7 MODE1 Mode selection input 1 Select operating mode for peak current mode or constant ON time. 8 PGND Power ground 9 ISNS Current sense voltage feedback 10 GATE Gate driver output This pin provides power to the internal control circuitry and gate driver. Connect a 10µF capacitor from this pin to ground. The pin senses the voltage of the auxiliary winding for zero current detection. Signal ground. Power ground. This pin must be connected to the AGND pin externally for normal operation. This pin has no internal connection to PGND. Switch current sensing input. Gate driving signal to the external switching MOSFET. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 TPS92310 www.ti.com SNVS792 – FEBRUARY 2012 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VCC to GND -0.3V to 40V DLY, COMP, ZCD to GND -0.3V to 7V ISNS to GND -0.3V to 7V GATE to GND -0.3V to 12V (5ns, –5V) MODE1 to GND -0.3V to 7V MODE2 to GND ESD Rating, HBM -0.3V to 7V (3) ±2 kV Machine Model 200V Storage Temperature Range -65°C to +125°C Junction Temperature (1) (2) (3) +150°C Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test conditions, see the Electrical Characteristics. All voltages are with respect to the potential at the GND pin, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. Human Body Model, applicable std. JESD22-A114-C. Operating Conditions Supply Voltage range VCC 13V to 36V Junction Temperature (TJ) Thermal Resistance (θJA) (1) -40°C to +125°C (1) 120°C/W Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX). Electrical Characteristics VCC = 18V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA = TJ = +25°C. Limits appearing in boldface type apply over the full Operating Temperature Range. Data sheet minimum and maximum specification limits are specified by design, test or statistical analysis. Symbol Parameter Conditions Min Typ Max Units VCC Turn on threshold 23.4 / 23 VCCTurn off threshold 11.1 / 10.4 25.6 27.8 / 29 V 13 14.7 / 15.7 V SUPPLY VOLTAGE INPUT (VCC) VCC-UVLO Hysteresis 12.6 ISTARTUP Startup Current VCC=VCC-UVLO–3.0V 10 12.5 14.75 µA IVCC Operating supply current Not switching 0.9 1.2 1.5 mA 65kHz switching, CLOAD = 1nF 2 mA ZERO CROSS DETECT (ZCD) IZCD ZCD bias current VZCD-OVP ZCD over-voltage threshold VZCD= 5V TOVP Over voltage de-bounce time VZCD-ARM ZCD Arming threshold VZCD = Increasing 1.16 VZCD-TRIG ZCD Trigger threshold VZCD = Decreasing 0.48 VZCD-HYS ZCD Hysteresis VZCD-ARM-VZCD-TRIG 4.1 0.1 1 µA 4.3 4.5 V 3 cycle 1.24 1.3 V 0.6 0.77 V 0.64 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 V 3 TPS92310 SNVS792 – FEBRUARY 2012 www.ti.com Electrical Characteristics (continued) VCC = 18V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA = TJ = +25°C. Limits appearing in boldface type apply over the full Operating Temperature Range. Data sheet minimum and maximum specification limits are specified by design, test or statistical analysis. Symbol Parameter Conditions Min Typ Max Units COMPENSATION (COMP) ICOMP-SOURCE Internal reference current for primary side current regulation VCOMP = 2.0V, VISNS = 0V, Measure at COMP pin 27 µA gmISNS ISNS error amp transconductance Δ VISNS to Δ ICOMP @ VCOMP = 2.5V 100 µmho VCOMP COMP operating range 2.0 3.5 V 1.26 V DELAY CONTROL (DLY) VDLY DLY pin internal reference voltage IDLY-MAX DLY source current 1.21 VDLY= 0V 250 1.23 µA CURRENT SENSE (ISNS) VISNS-OCP Over Current Detection Threshold Non isolation mode 0.59 0.64 0.68 V VISNS-OCP Over Current Detection Threshold Isolation mode 3.2 3.4 3.6 V IISNS Current Sense Bias Current VISNS= 5V -1 1 µA TOCP Over current Detection Propagation Delay Measure GATE pulse width at VISNS = 5V 210 ns GATE DRIVER (GATE) VGATE-H GATE high drive voltage IGATE = 50mA source 8 9.4 11.86 V VGATE-L GATE low drive voltage IGATE = 50mA sink 28 80 167 mV TON-MIN Minimum ON time 360 540 720 ns TOFF-MAX Maximum OFF time ZCD = GND 50 72 94 µs tGATE-RISE Rise time CLOAD = 1nF 110 ns tGATE-FALL Fall time CLOAD = 1nF 20 ns Thermal shutdown temperature (1) 165 °C Thermal Shutdown hysteresis 20 °C THERMAL SHUTDOWN TSD (1) 4 Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typ.) and disengages at TJ = 145°C (typ). Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 TPS92310 www.ti.com SNVS792 – FEBRUARY 2012 Typical Performance Characteristics All curves taken at VCC=18V with configuration in typical application for driving seven power LEDs with ILED=350mA shown in this datasheet. TA=25°C, unless otherwise specified. 15.0 VCC-UVLO vs Temperature VCC Startup Voltage vs Temperature 28 VCCSTARTUP VOLTAGE (V) 14.5 VCC-UVLO(V) 14.0 13.5 13.0 12.5 12.0 11.5 11.0 -50 80 27 26 25 24 23 22 -25 0 25 50 75 TEMPERATURE (°C) Figure 3. 100 125 -50 TOFF-MAX vs Temperature 600 -25 0 25 50 75 TEMPERATURE (°C) Figure 4. 100 125 TON-MIN vs Temperature 78 580 74 TON-MIN(ns) TOFF-MAX(us) 76 72 70 68 66 64 560 540 520 500 62 60 -50 1.50 480 -25 0 25 50 75 TEMPERATURE ( °C) Figure 5. 100 125 -50 IVCC-SD vs Temperature 5.2 1.45 100 125 VZCD-OVP vs Temperature 4.8 1.35 VZCD-OVP(V) IVCC-SD(mA) 0 25 50 75 TEMPERATURE (°C) Figure 6. 5.0 1.40 1.30 1.25 1.20 1.15 4.6 4.4 4.2 4.0 1.10 3.8 1.05 1.00 -50 -25 -25 0 25 50 75 TEMPERATURE (°C) Figure 7. 100 125 3.6 -50 -25 0 25 50 75 TEMPERATURE (°C) Figure 8. 100 125 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 5 TPS92310 SNVS792 – FEBRUARY 2012 www.ti.com Typical Performance Characteristics (continued) All curves taken at VCC=18V with configuration in typical application for driving seven power LEDs with ILED=350mA shown in this datasheet. TA=25°C, unless otherwise specified. 1.50 VZCD-ARM vs Temperature 1.45 0.75 0.70 1.35 VZCD-TRIG(V) VZCD-ARM(V) 1.40 1.30 1.25 1.20 1.15 0.60 0.56 0.45 1.05 -25 0 25 50 75 TEMPERATURE (°C) Figure 9. 0.40 -50 100 125 VISNS-OCP (Isolated Mode) vs Temperature 4.2 4.0 0.9 3.8 0.8 3.6 3.4 3.2 0 25 50 75 TEMPERATURE (°C) Figure 10. 100 125 0.7 0.6 0.5 0.4 3.0 0.3 2.8 2.6 -50 -25 VISNS-OCP (Non-Isolated Mode) vs Temperature 1.0 VISNS-OCP(V) VISNS-OCP(V) 0.65 0.50 1.10 1.00 -50 VZCD-TRIG vs Temperature 0.80 0.2 -25 0 25 50 75 TEMPERATURE (°C) Figure 11. 100 125 -50 -25 0 25 50 75 TEMPERATURE (°C) Figure 12. 100 125 VGATE vs Temperature 11.0 10.5 VGATE(V) 10.0 9.5 9.0 8.5 8.0 7.5 7.0 -50 6 -25 0 25 50 75 TEMPERATURE (°C) Figure 13. 100 125 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 TPS92310 www.ti.com SNVS792 – FEBRUARY 2012 GATE SIMPLIFIED INTERNAL BLOCK DIAGRAM VC1 VCC BIAS & VREF VREF UVLO PGND MODE1 MODE Decode TSD MODE2 ZC ZCD LEB ON VTRIG/VARM CONTROL iLimit LEB OVP ISNS OCP TON VC1 TON Control COMP TON Peak Hold VONpk IREF D UVLO AGND DRV COMP ZC OFT DELAY VONpk ON Idly V/I DLY Figure 14. Simplified Block Diagram Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 7 TPS92310 SNVS792 – FEBRUARY 2012 www.ti.com Application Information The TPS92310 is an off-line controller specifically designed to drive LEDs with inherent Power Factor Correction (PFC). This device operates in Critical Conduction Mode (CRM) with adaptive Constant ON-Time control, so that high power factor can be achieved naturally. The TPS92310 can be used in isolated and non-isolated off-line applications that cover most requirements for LED lighting applications. A typical application schematic is shown in Figure 1. On the primary side, the off-line flyback converter consists of a transformer which includes three windings LP, LS and LAUX, an external MOSFET Q1 and inductor current sensing resistor RISNS. On the output side, the LS winding, the output diode D3, the output capacitor COUT and a LED string connected as the load. Additionally, an auxiliary supply circuit to power the TPS92310 after start-up with LAUX output is implemented. The LAUX output voltage, VLAUX is also used to detect the zero crossing point due to the end of a complete switching cycle. During the on-period, Q1 is turned on, the AC line input is rectified by the input bridge rectifier D1 and input capacitor CIN and current flows through LP, Q1 and RISNS to ground, input energy is stored in the primary inductor LP. Simultaneously, the ISNS pin of the device monitors the voltage of the current sensing resistor RISNS to perform the cycle-by-cycle inductor current limit function. While the MOSFET Q1 turned off, current flow in LP ceased and the energy stored during the on cycle is released to output and auxiliary circuits. The current in the secondary winding LS charges the output capacitor COUT through D3 and supplies the LED load, the COUT also responsible to supply current to LED load during subsequent on-period. The current flows through LAUX powers the TPS92310 through D2 and CVCC in steady state operation. The voltage across LAUX, VLAUX is fed back to the ZCD pin through a resistor divider network formed by R2 and R3 to perform zero crossing detection of VLAUX, which determines the end of the off-period of a switching cycle. The next on-period of a new cycle will be initiated after an inserted delay of 2 x tDLY, the tDLY is programmable by a single resistor connecting the DLY pin and ground. The setting of the delay time, tDLY will be described in separate paragraph. During steady state operation, the duration of the on-period tON can be determined with two different modes: the Constant On-Time (COT) mode and the Peak Current Mode (PCM), which are configured by setting the MODE1 and MODE2 pins. For the COT mode, tON is generated by comparing an internal fixed saw-tooth wave with the voltage on the COMP pin, VCOMP. Since VCOMP is slow varying, tON is nearly constant within an AC line cycle. For the PCM, the on-period is terminated when the voltage of the ISNS pin, VISNS reaches a threshold determined by VCOMP. Since the instantaneous input voltage (AC voltage) varies, tON varies accordingly within an AC line cycle. The duration of the off-period tOFF is determined by the rate of discharging of LS, which is governed by ILS-PEAK and VLED. Also, ILS-PEAK equals to n × ILP-PEAK where n is the turn ratio of LP and LS. Figure 15 shows the typical waveforms in normal operation. VSW 2xtDLY t ILP VCOMP t tON ILS ILED VZCD tOFF t VZCD-OVP VZCD-PEAK VZCD-ARM VZCD-TRIG tDLY t Figure 15. Primary and Secondary Side Current Waveforms 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 TPS92310 www.ti.com SNVS792 – FEBRUARY 2012 Startup Bias and UVLO During startup, the TPS92310 is in the startup state. It is powered from the AC line through R1 and D1 (Figure 1). In the startup state, most of the internal circuits of the TPS92310 shut down so that the quiescent current is minimized. When VCC (voltage on the VCC pin) reaches the rising threshold of the VCC-UVLO (typically 25.6V), the TPS92310 is in the low frequency state, where tON and tOFF are fixed to 1.5μs and 72μs. When VZCD–PEAK is higher than VZCD-ARM, the TPS92310 enters normal operation. VSW Low Freq state Steady state Startup state t VCC 25.6V 13V t VZCD VZCD-OVP VZCD-ARM t Figure 16. Start up Bias Waveforms Mode Decoder The TPS92310 can operate in the Peak Current Mode (PCM) or Constant On-Time (COT) mode if an isolated topology is used. The TPS92310 can also use a non-isolated topology. In this case, only the COT mode can be selected. The COT mode gives a high power factor. The PCM can achieve a lower output current ripple. The COT mode using a non-isolated topology can achieve a higher efficiency and good load regulation. The above modes can be selected by setting the MODE1 and MODE2 pins according to Table 1. For normal operation of the TPS92310, the MODE1 and MODE2 pins cannot be connect to ground at the same time. And these pin were biased by an internal 1μA pull up, forcing any voltage into these pins are not allowed. The MODE decoder status will latch-in only when VCC voltage reaches the VCC-UVLO turn on threshold during start-up. Table 1. MODE Configuration MODE1 MODE2 Mode of operation OPEN OPEN COT mode using isolated topology GND OPEN PCM using isolated topology OPEN GND COT mode using non-isolated topology GND GND Reserved Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 9 TPS92310 SNVS792 – FEBRUARY 2012 www.ti.com Zero Crossing Detection To minimized the switching loss of the external MOSFET, a zero crossing detection circuit is embedded in the TPS92310. VLAUX is AC voltage coupled from VSW by means of the transformer, with the lower part of the waveform clipped by DZCD. VLAUX is fed back to the ZCD pin to detect a zero crossing point through a resistor divider network which consists of R2 and R3. The next turn on time of Q1 is selected VSW is the minimum, an instant corresponding to a small delay after the zero crossing occurs. (Figure 17) The actual delay time depends on the drain capacitance of the Q1 and the primary inductance of the transformer (LP). Such delay time is set by a single external resistor as described in Delay Setting section. During the off-period at steady state, VZCD reaches its maximum VZCD-PEAK (Figure 14), which is scalable by the turn ratio of the transformer and the resistor divider network R2 and R3. It is recommended that VZCD-PEAK is set to 3V during normal operation. n u VLED +VIN n u VLED VSW tDLY Figure 17. Switching Node Waveforms Delay Time Setting In order to reduce EMI and switching loss, the TPS92310 can insert a delay between the off-period and the onperiod. The delay time is set by a single resistor which connects across the DLY pin and ground, and their relationship is shown in Figure 18. The optimal delay time depends on the resonance frequency between LP and the drain to source capacitance of Q1 (CDS). Circuit designers should optimize the delay time according to the following equation. (1) (2) After determining the delay time, tDLY can be implemented by setting RDLY according to the following equation: (3) where KDLY = 32MΩ/ns is a constant. 60 RDLY(k ) 50 40 30 20 10 0 0 400 800 1200 1600 DELAY TIME (ns) 2000 Figure 18. Delay Time Setting 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 TPS92310 www.ti.com SNVS792 – FEBRUARY 2012 Protection Features Output Open Circuit Protection If the LED string is disconnected, VLED increases and thus VZCD-PEAK increases. When VZCD-PEAK is larger than VZCD-OVP for 3 continues switching cycles, the Over Voltage Protection (OVP) feature is triggered such that the TPS92310 becomes Over-Voltage (OV) state. In this case, the switching of Q1 is stopped, and VCC decreases owing to the power consumption of the internal circuits of the TPS92310. When VCC drops below the falling threshold of VCC-UVLO, the TPS92310 restarts, and re-enter into startup state (Figure 20). Output Short Circuit Protection If the LED string is shorted, VZCD-PEAKdrops. If VZCD-PEAK drops below VZCD-TRIG, the TPS92310 will under low frequency operation. In this case, the power supplied from LAUX is not enough to maintain VCC, then VCC decreases. If the short is removed during low frequency state, the TPS92310 will restore to steady state. If the short sustains till VCC drops below the falling threshold of VCC-UVLO, the TPS92310 restarts, and becomes startup state again. (Figure 19) VSW Steady state Low freq state Low freq state t VCC 25.6V 13V t VZCD VZCD-OVP VZCD-ARM t VLED t Figure 19. Output Short Circuit waveforms Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 11 TPS92310 SNVS792 – FEBRUARY 2012 www.ti.com Over Current Protection The Over Current Protection (OCP) limits the drain current of the external MOSFET Q1 and prevent inductor / transformer saturation. When VISNS reaches a threshold, the OCP is triggered and the output of the GATE pin is low immediately. The threshold is typically 3.4V and 0.64V when the TPS92310 is using an isolated topology and a non-isolated topology respectively. Thermal Protection Thermal protection is implemented by an internal thermal shutdown circuit, which activates at 160°C (typically) to shut down the TPS92310. In this case, the GATE pin outputs low to turn off the external MOSFET, and hence no power from the VAUX winding to VCC. Capacitor CVCC will discharge until UVLO. When the junction temperature of the TPS92310 falls back below 130°C, the TPS92310 resumes normal operation. Steady state Startup state Low Freq state VSW OV state Steady state Disconnect LED Reconnect LED Steady state Startup state Startup state Startup state Low Freq state VCC 25.6V 13V VZCD VZCD-OVP VZCD-ARM VLED ILED Steady state Force output short circuit Steady state Figure 20. Auto Restart Operation 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 TPS92310 www.ti.com SNVS792 – FEBRUARY 2012 Design Example The following design example illustrates the procedures to calculate the external component values for the TPS92310 isolated single stage fly-back LED driver with PFC. Design Specifications: Input voltage range, VAC_RMS = 85VAC – 132VAC Nominal input voltage, VAC_RMS(NOM) = 110VAC Number of LED in serial =7 LED current, ILED = 350mA Forward voltage drop of single LED = 3.0V Forward voltage of LED stack, VLED = 21V Key operating Parameters: Converter minimum switching frequency, fSW = 75kHz Output rectifier maximum reverse voltage, VD3(MAX) = 100V Power MOSFET rating, VQ1(MAX) = 800V (2.5A/3.8Ω) Power MOSFET Output Capacitance, CDS = 37pF (estimated) Nominal output power, POUT = 8W Start Up Bias resistor During start up, the VCC will be powered by the rectified line voltage through external resistor, R1. The VCC start up current, IVCC(SU) must set in the range IVCC(MIN)>IVCC(SU)>ISTARTUP(MAX) to ensure proper restart operation during OVP fault. In this example, a value of 0.55mA is suggested. The resistance of R1 can be calculated by dividing the nominal input voltage in RMS by the start up current suggested. So, R1 = 110V/0.55mA = 200KΩ is recommended. Transformer Turn Ratio The transformer winding turn ratio, n is governed by the MOSFET Q1 maximum rated voltage, (VQ3(MAX)), highest line input peak voltage (VAC-PEAK) and output diode maximum reverse voltage rating (VD3(MAX)). The output diode rating limits the lower bound of the turn ratio and the MOSFET rating provide the upper bound of the turn ratio. The transformer turn ratio must be selected in between the bounds. If the maximum reverse voltage of D3 (VD3(MAX)) is 100V. the minimum transformer turn ratio can be calculated with the equation in below. (4) In operation, the voltage at the switching node, VSW must be small than the MOSFET maximum rated voltage VQ1(MAX) , For reason of safety, 10% safety margin is recommended. Hence, 90% of VQ1(MAX) is used in the following equation. (5) (6) where VOS is the maximum switching node overshoot voltage allowed, in this example, 50V is assumed. As a rule of thumb, lower turn ratio of transformer can provide a better line regulation and lower secondly side peak current. In here, turn ratio n = 3.8 is recommended. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 13 TPS92310 SNVS792 – FEBRUARY 2012 www.ti.com Switching Frequency Selection TPS92310 can operate at high switching frequency in the range of 60kHz to 150kHz. In most off-line applications, with considering of efficiency degradation and EMC requirements, the recommended switching frequency range will be 60kHz to 80kHz. In this design example, switching frequency at 75kHz is selected. Switching On Time The maximum power switch on-time, tON depends on the low line condition of 85VAC. At 85VAC the switching frequency was chosen at 75kHz. This transformer design will follow the formulae as shown below. (7) Transformer Primary Inductance The primary inductance, LP of the transformer is related to the minimum operating switching frequency fSW, converter output power POUT, system efficiency η and minimum input line voltage VAC_RMS(MIN). For CRM operation, the output power, POUT can be described by the equation in below. (8) By re-arranging terms, the transformer primary inductance required in this design example can be calculated with the equation follows: (9) The converter minimum switching frequency is 75kHz, tON is 5.3µs, VAC_RMS(MIN) = 85V and POUT = 8W, assume the system efficiency, η = 85%. Then, (10) From the calculation in above, the inductance of the primary winding required is 0.81mH. Calculate The Current Sensing Resistor After the primary inductance and transformer turn ratio is determined, the current sensing resistor, RISNS can be calculated. The resistance for RISNS is governed by the output current and transformer turn ratio, the equation in below can be used. (11) where VREF is fixed to 0.14V internally. Transformer turn ratio, NP : NS is 3.8 : 1 and ILED = 0.35A (12) 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 TPS92310 www.ti.com SNVS792 – FEBRUARY 2012 TPS92310 GATE Q1 ISNS RISNS PGND PGND Figure 21. RISNS Resistor Interface D2 VCC L3 R2 ZCD CZCD PGND R3 PGND DZCD PGND Figure 22. Auxiliary Winding Interface to ZCD Auxiliary Winding Interface To ZCD In Figure 22, R2 and R3 forms a resistor divider which sets the thresholds for over voltage protection of VLED, VZCD-OVP, and VZCD-PEAK. Before the calculation, we need to set the voltage of the auxiliary winding, VLAUX at open circuit. For example : Assume the nominal forward voltage of LED stack (VLED) is 21V. To avoid false triggering ZCDOVP voltage threshold at normal operation, select ZCDOVP voltage at 1.3 times of the VLED is typical in most applications. In case the transformer leakage is higher, the ZCDOVP threshold can be set to 1.5 times of the VLED. In this design example, open circuit AUX winding OVP voltage threshold is set to 30V. Assume the current through the AUX winding is 0.4mA typical. As a result, R2 is 66kΩ and R3 is 11kΩ. Also, for suppressing high frequency noise at the ZCD pin, a 15pF capacitor connects the ZCD pin to ground is recommended. Auxiliary Winding Vcc Diode Selection The VCC diode D2 provides the supply current to the controller, low temperature coefficient , low reverse leakage and ultra fast diode is recommended. Compensation Capacitor And Delay Timer Resistor Selection To achieve PFC function with a constant on time flyback converter, a low frequency response loop is required. In most applications, a 2.2µF CCOMP capacitor is suitable for compensation. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 15 TPS92310 SNVS792 – FEBRUARY 2012 www.ti.com TPS92310 CVCC VCC DZCD ZCD AGND CCOMP COMP RDLY DLY PGND Figure 23. Compensation and DLY Timer connection The resistor RDLY connecting the DLY pin to ground is used to set the delay time between the ZCD trigger to gate turn on. The delay time required can be calculated with the parasitic capacitance at the drain of MOSFET to ground and primary inductance of the transformer. Equation in below can be used to find the delay time and Figure 18 can help to find the resistance once the delay time is calculated (13) For example, using a transformer with primary inductance LP = 1mH, and power MOSFET drain to ground capacitor CDS=37pF, the tDLY can be calculated by the upper equation. As a result, tDLY=302ns and RDLY is 6.31kΩ. The delay time may need to change according to the primary inductance of the transformer. The typical level of output current will shift if inappropriate delay time is chosen. Output Flywheel Diode Selection To increase the overall efficiency of the system, a low forward voltage schottky diode with appropriate rating should be used. Primary Side Snubber Design The leakage inductance can induce a high voltage spike when power MOSFET is turned off. Figure 24 illustrate the operation waveform. A voltage clamp circuit is required to protect the MOSFET. The voltage of snubber clamp (VSN) must be higher than the sum of over shoot voltage (VOS), LED open load voltage multiplied by the transformer turn ratio (n). In this examples, the VOS is 50V and LED maximum voltage, VLED(MAX) is 30V, transformer turn ratio is 3.8. The snubber voltage required can be calculated with following equations. VOS VSN VMOS_BV n u VLED VAC_PEAK Vsw Figure 24. Snubber Waveform (14) where n is the turn ratio of the transformer. (15) At the same time, sum of the snubber clamp voltage and VAC peak voltage (VAC_PEAK) must be smaller than the MOSFET breakdown voltage (VMOS_BV). By re-arranging terms, equation in below can be used. 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 TPS92310 www.ti.com SNVS792 – FEBRUARY 2012 (16) In here, snubber clamp voltage, VSN = 250V is recommended. Output Capacitor The capacitance of the output capacitor is determined by the equivalent series resistance (ESR) of the LED, RLED and the ripple current allowed for the application. The equation in below can be used to calculate the required capacitance. (17) Assume the ESR of the LED stack contains 7 LEDs and is 2.6Ω, AC line frequency fAC is 60Hz. In this example, LED current ILED is 350mA and output ripple current is 30% of ILED: (18) Then, COUT = 480μF. In here, a 470μF output capacitor with 10μF ceramic capacitor in parallel is suggested. PCB Layout Considerations The performance of any switching power supplies depend as much upon the layout of the PCB as the component selection. Good layout practices are important when constructing the PCB. The layout must be as neat and compact as possible, and all external components must be as close as possible to their associated pins. High current return paths and signal return paths must be separated and connect together at single ground point. All high current connections must be as short and direct as possible with thick traces. The gate pin of the switching MOSFET should be connected close to the GATE pin with short and thick trace to reduce potential electro-magnetic interference. For off-line applications, one more consideration is the safety requirements. The clearance and creepage to high voltage traces must be complied to all applicable safety regulations. L1 NP : NS : NAUX = 3.8 : 1 : 1 LED+ 3.3 mH 0.5A 600V 0.5A R1a 100 kQ CIN 0.1 PF 250V 90-135 VAC LP 1A 600V R1b 100 kQ CAC VR1 T1 C1 0.1 PF D1 47 nF R4 D3 1A 100V LS COUTa COUTb 10 PF 470 PF D2 BAV20 6±7 LED RAC 20Q *Z1 35V 22Q CZCD 15 pF CVCC 10 PF CDSU4148 2.2 PF 6.34 kQ DZCD CCOMP RDLY *Optional R2 66 kQ LAUX R3 11 kQ LED2200 pF U1 1 2 3 4 5 10 VCC GATE 9 ISNS ZCD 8 AGND PGND 7 COMP MODE1 6 DLY MODE2 Q1 STD3NK80Z RISNS 1.52Q TPS92310 Figure 25. Isolated topology schematic Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 17 TPS92310 SNVS792 – FEBRUARY 2012 www.ti.com L1 3.3 mH 0.5A 600V C1 0.1 PF CIN 0.1 PF 0.5A D1 NP:NAUX = 1:1 R1 200 k: 90-135 VAC VR1 LP = LS CAC 47 nF R4 D2 20Q 0.1A 600V T1 RAC *Z1 22: LAUX R3 11 k: CZCD 15 pF 3 4 CCOMP 2.2 PF 5 RDLY 6.34 k: * Optional 1 2 DZCD CDSU4148 VCC GATE ZCD ISNS AGND PGND COMP MODE1 DLY MODE2 6-7 LED 470 PF R2 68 k: 35V CVCC 10 PF COUT 10 D3 1A 600V Q1 9 8 7 6 RISNS 0.4: TPS92310 Figure 26. Non-isolated topology schematic 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92310 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TPS92310DGS/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SL1B TPS92310DGSR/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SL1B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS92310DGS/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS92310DGSR/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS92310DGS/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 TPS92310DGSR/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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