SMR101 Preliminary Information 1 (See Last Page) FEATURES & APPLICATIONS INTRODUCTION • Two Programmable Reset Outputs, SOFT_RST# And HARD_RST# • De-Bounced Push-Button Reset Input With a Programmable Delay Up To 40 Seconds Prior To Reset Assertion • 8 Programmable Settings For Both SOFT_RST# And HARD_RST# Delay • Programmable Voltage Monitor With 8 Voltage Settings To Trigger SOFT_RST# Output • Programmable Reset Output Duration From 1200ms • Built-In 15us Voltage Glitch Filtering And Input “De-Bouncing” TM • 6 Ball Ultra CSP (Chip-Scale) Package • 8 Lead SOIC Package Applications • PDAs, Handheld PCs, Cameras, Camcorders • Handheld GPS Equipment • Satellite And Cable-TV Set-Top Box The SMR101 is a programmable reset controller especially designed for embedded consumer electronics. The device provides dual outputs that can be used to implement “soft” and “hard” system resets. Both resets can be triggered by an external reset input, and an internal voltage monitor can trigger the soft reset. Typically a “soft” reset applies to volatile registers in an embedded controller while a hard reset is equivalent to a full power cycle without the associated power-up delays. The SMR101 receives an external push-button input using an internal programmable debounced timer. The push button input hold down time is programmable up to 40 seconds with an internal on-chip timer. A “short” hold down time (0.125-10 sec) asserts the SOFT_RST# pin while a long hold down time (0.540 sec) asserts the HARD_RST# pin. Both reset outputs have programmable output durations from 1200ms. Additionally, voltage monitoring is provided via a programmable threshold detector (2.30V – 4.50V) on the VDD pin. This voltage detector asserts the SOFT_RST# pin for the same 1-200ms output duration as above. A 15us glitch filter avoids nuisance tripping that can result in unnecessary system resets. The SMR101 is factory programmed, to default values; however, multiplexed programming pins are also provided for in-system programming for prototype purposes. SIMPLIFIED APPLICATIONS DRAWING 2.7V _ 5.5V 0.1μf 3.3V VDD Manual Reset Switch RESET_IN# TRIM_C AP FILT_CAP SOFT_RST# SMR101 GND PROG HARD_RST# μP Figure 1 – Applications schematic using the SMR101 to supervise an embedded controller. As shown, the SMR101 implements a two-level RESET function including external manual input. © SUMMIT Microelectronics, Inc. 2006 • 757 North Mary Avenue • Sunnyvale CA 94085 • Phone 408 523-1000 • FAX 408 523-1266 http://www.summitmicro.com 2099 2.4 7/20/2010 1 SMR101 Preliminary Information GENERAL DESCRIPTION The SMR101 is a programmable reset controller that monitors the power supply in µP and digital systems for under voltage conditions The integrated feature set provides excellent circuit reliability and low cost by eliminating external components while the programmable settings allow “on the fly” adjustments necessary for modern control techniques. The device performs several functions: it first asserts a “soft” reset signal whenever the VDD supply voltage declines below a preset threshold, keeping it asserted for a programmable time period after VDD has risen above the reset threshold. The part also provides a push button input with two programmable delays for hierarchical manual system reset. The open-drain SOFT_RST# and HARD_RST# outputs have on-chip 100K pull-up resistors and do not require external pull-up resistors unless more drive current is needed (see figure 3). The SOFT_RST# comparator is designed to ignore fast transients on VDD, and the output is guaranteed to be in the correct logic state for VDD down to 1V. Low supply current makes the SMR101 ideal for use in portable equipment. The RESET_IN# input includes a programmable hold-down delay timer for use with a push button switch for consumer equipment such as set-top boxes and PCs. A microprocessor’s (µP’s) reset input starts the µP in a known state. The SMR101 asserts a SOFT_RST# to prevent code execution errors during power-up, power-down, or UnderVoltage (UV) conditions whenever the VDD supply voltage declines below a programmed limit (VMON). There are 8 programmable voltage settings to trigger the SOFT_RST# output. SOFT_RST# stays asserted for a programmable period after VDD has risen above the reset threshold. The SOFT_RST# signal is also asserted whenever the RESET_IN# input is asserted for a programmed delay. There are 8 programmable timing settings (TRESET_SR) to trigger SOFT_RST# output. The HARD_RST# signal is also asserted whenever the RESET_IN# input is asserted for a separate programmed delay. There are 8 programmable timing settings (TRESET_HR) to trigger the HARD_RST# output. It is recommended that the soft reset time be of a shorter duration than that of the HARD_RST#. In addition to issuing a reset to the µP during powerup, power-down, and brownout conditions, the SMR101 is immune to short-duration VDD transients (glitches) due to an internal glitch filter. A external 0.1µF bypass capacitor mounted as close as possible to the VDD pin provides additional transient immunity. Since the SOFT_RST# and HARD_RST# outputs are open drain, the device interfaces easily with µPs that have bidirectional-reset pins. Connecting the SOFT_RST# output directly to the µP’s RESET pin allows either the µP or the SMR101 to assert a reset. . VMON VDD TGLITCH TRESET TRESET TRESET_SR TRESET TRESET TRESET_SR SOFT_RST# TRESET_HR HARD_RST# RESET_IN# Push-Button Input Push-Button Push-Button Engaged Released Push-Button Released Push-Button Engaged Figure 2 – SMR101 Operation and timing diagram. Summit Microelectronics, Inc 2099 2.4 7/20/2010 2 SMR101 Preliminary Information INTERNAL BLOCK DIAGRAM 2.7V_5.5V z VDD z z z z SOFT_RST at 2.30V-4.5V z z + 100k SOFT_RST# Glitch Filter z Programmable Duration Reset Output Vref z 2 PROG z User Reset Pushbutton Programmable Hold-Down Time, 0.125 to 40 Sec 100k z z z z z z z z z z RESET _IN# MSB Reset Input Up Count 8 KHz Ring Oscillator, +/-10% accurate z 100k Programmable Delay Generator/ Logic z HARD_RST# GND Figure 3 – SMR101 Internal Block Diagram. Register Value 000 001 010 011 100 101 110 111 Pushbutton Input delay (seconds) HARD_RST# Register SOFT_RST# Value 0.5 000 0.125 1 001 0.25 2 010 0.5 4 011 1 8 100 2 16 101 4 32 110 8 40 111 10 Voltage Monitor Threshold (V) Register Value Voltage 000 001 010 011 100 101 110 111 4.50 4.25 2.97 2.81 2.70 2.55 2.43 2.30 RESET Timeout Period (ms) Register Value Time 00 01 10 11 1 25 100 200 Figure 4 – SMR101 Register Maps. The SMR101 is user programmable using the SMX3199 Programmer and the SMR101 Windows GUI. Summit Microelectronics, Inc 2099 2.4 7/20/2010 3 SMR101 Preliminary Information PACKAGE PACKAGEAND ANDPIN PINCONFIGURATION CONFIGURATION 6 Ball Ultra CSPTM 8 Lead SOIC Top View Bottom View PROG A1 A2 VDD GND B1 B2 HARD_RST# RESET_IN# C1 C2 SOFT_RST# PROG 1 8 VDD NC 2 7 NC RESET_IN# 3 6 SOFT_RST# GND 4 5 HARD_RST# PIN DESCRIPTIONS CSP SOIC Ball Number Lead Number A1 1 I A2 8 B1 Pin Type Pin Name Pin Description PROG High voltage programming pin. Connected to ground during normal operation. PWR VDD Positive supply voltage. 4 PWR GND Ground pin. B2 5 O HARD_RST# C1 3 I RESET_IN# C2 6 O SOFT_RST# NA 2,7 NC Summit Microelectronics, Inc NC Open Drain active low Hard Reset Out indicator. Internally connected to VDD through a 100KΩ resistor. De-bounced push button switch input. Internally connected to VDD through a 100KΩ resistor. Also used as the Data input programming pin. Open Drain active low Soft Reset Out indicator. Internally connected to VDD through a 100KΩ resistor. No Connect 2099 2.4 7/20/2010 4 SMR101 Preliminary Information ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATION CONDITIONS Temperature Under Bias .......................-55°C to +125°C Storage Temperature.............................-65°C to +125°C Terminal Voltage with Respect to GND: VDD ……………………………...….-0.3V to +6.0V PROG, RESET_IN#.................... -0.3V to +16.0V All Others .......................................... VDD + 0.7V Output Short Circuit Current .....................100mA Reflow Solder Temperature (30 secs)....................260°C ESD Rating per JEDEC……………………………...2000V Latch-Up testing per JEDEC………… ... …......…±100mA Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. Temperature Range (Commercial). ……….0°C to +70°C Supply Voltage1………………………………..3.3V +/-10% Note 1 – The device can operate over a supply range of 2.7V to 5.5V. Package Thermal Resistance (ΘJA) 8 Lead SOIC.………………….……….………….…23oC/W 6 Ball UltraCSP™ ...……………………….………TBDoC/W Moisture Classification Level 1 (MSL 1) per J-STD- 020 RELIABILITY CHARACTERISTICS Data Retention………………...……………..…..100 Years Endurance…………………...…….……….100,000 Cycles DC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min. Typ. Max Unit VDD IDD tGLITCH Supply Voltage Range Power Supply Current 2.7 5.5 40 50 55 65 15 18 μs VDD V 0.1xVDD V 0 0.4 V 0 1.0 mA VDD = 3.3V, no RESET in progress. VDD = 5.5V, no RESET in progress. Glitch filter time VIH Input High Voltage VDD = 3.3V VIL Input Low Voltage VDD = 3.3V VOL Open Drain Outputs (HARD_RST#, SOFT_RST#) ISINK = 1mA IOL Output Low Current VMON 3.3 Voltage Monitor Threshold1 Programmed Default = 2.97V 0.9xVD D V μA 4.41 4.5 4.59 V 4.16 4.25 4.34 V 2.91 2.97 3.03 V 2.75 2.81 2.87 V 2.64 2.7 2.76 V 2.5 2.55 2.6 V 2.38 2.43 2.48 V 2.25 2.3 2.35 V Note 1 - Voltage monitor threshold accuracies are relative to factory programmed setting; deviation from this setting can result in errors exceeding those stated above. Summit Microelectronics, Inc 2099 2.4 7/20/2010 5 SMR101 Preliminary Information AC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min. Typ. Max Unit 0.80 1 1.20 ms TRESET TRESET_SR TRESET_HR Reset Output Timeout period Programmable Reset HoldDown Delay times (soft reset) Programmable Reset HoldDown Delay times (hard reset) Summit Microelectronics, Inc Programmed Default = 100ms Programmed Default = 0.25s Programmed Default = 4s 2099 2.4 7/20/2010 20 25 30 ms 80 100 120 ms 160 200 240 ms 0.10 0.125 0.15 s 0.20 0.25 0.30 s 0.40 0.5 0.60 s 0.80 1 1.20 s 1.60 2 2.40 s 3.20 4 4.80 s 6.40 8 9.60 s 8 10 12 s 0.40 0.5 0.60 s 0.80 1 1.20 s 1.60 2 2.40 s 3.20 4 4.80 s 6.40 8 9.60 s 12.80 16 19.20 s 25.60 32 38.40 s 32 40 48 s 6 SMR101 Preliminary Information PACKAGE OUTLINE 8 Lead SOIC Package Ref. JEDEC MS-012 0.150 - 0.157 (3.80 - 4.00) 1 Inches (Millimeters) 0.189 - 0.196 (4.80 - 5.00) 0.053 - 0.069 (1.35 - 1.75) 0.013 - 0.020 (0.33 - 0.51) Summit Microelectronics, Inc 0.010 - 0.020 ×45º (0.25 - 0.50) 0.004 - 0.010 (0.10 - 0.25) 0.016 - 0.050 (0.40 - 1.27) .05 (1.27) TYP. 2099 2.4 7/20/2010 0.228 - 0.244 (5.80 - 6.20) 8 Pin SOIC 7 SMR101 Preliminary Information PACKAGE OUTLINE (CONTINUED) 6 Ball Ultra CSPTM – Chip Scale Package 0.5 (Typical) 1.15 +/- 0.04 1.76 +/- 0.04 0.5 (Typical) TOP VIEW A1 A2 B1 B2 C1 C2 BOTTOM VIEW 0.24 +/- 0.02 0.31 +/- 0.02 Notes: 1) All Dimensions in [mm] 2) Drawing not to scale 0.559 +/- 0.03 SIDE VIEW Summit Microelectronics, Inc 2099 2.4 7/20/2010 8 SMR101 Preliminary Information PART MARKING 8 Lead SOIC 6 Ball Ultra CSPTM Summit Part Number SUMMIT SS SMR101S XX is the sequential number per wafer (i.e. 01 for the first wafer, 02 for the second wafer, 03 for the third wafer, etc.) Status Tracking Code (01, 02,...) (Summit Use) Ball A1 Identifier Date Code (YYWW) Pin 1 Lot tracking code (Summit use) 100% Sn, RoHS compliant Part Number suffix (Contains Customer specific ordering requirements) Drawing not to scale Drawing not to scale Product Tracking Code (Summit use) 101 V SS XXA YWW Annn L AYYWW Summit Part Number 96.8% Sn, 2.6% Ag, 0.6% Cu, RoHS compliant Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) Date Code Y = Single digit year (4=2004, 5=2005, etc) ORDERING INFORMATION SMR101 Summit Part Number E nnn V Package E = 6 Ball Ultra CSPTM S = 8 Lead SOIC V is the Lead-Free Attribute for the CSP (E Package), L is for the SOIC (S package) Part Number Suffix Customer specific requirements are contained in the suffix such as Hex code, Hex code revision, etc. The default device ordering number is SMR101E-316 and is programmed as described in the DC/AC Operating Characteristics tables on page 5 and 6 and tested over the commercial temperature range. NOTICE NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 2.4 - This document supersedes all previous versions. Please check the Summit Microelectronics Inc. web site at http://www.summitmicro.com for data sheet updates. © Copyright 2006 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE POWER FOR A DIGITAL WORLD™ TM Ultra CSP is a registered name of FlipChip International, LLC. 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