SUMMIT SMM105

SMM105
Preliminary Information 1 (See Last Page)
Single-Channel Supply Voltage Marginer and Active DC Output Controller
FEATURES & APPLICATIONS
INTRODUCTION
• Extremely accurate (±0.1%) Active
DC Output Control (ADOCTM)
The SMM105 actively controls the output voltage level
of a DC/DC converter that uses a Trim or VADJ/FB pin
to adjust the output. An Active DC Output Control
(ADOCTM) feature is used during normal operation to
maintain extremely accurate settings of supply
voltages and, during system test, to control margining
of the supplies using I2C commands. Total accuracy
with a ±0.1% external reference is ±0.2%, and ±0.5%
using the internal reference. The device can margin
supplies with either positive or negative trim pin control
within a range of 0.3V to VDD. The SMM105 supply
can be from 12V, 8V, 5V or 3.3V to as low as 2.7V to
accommodate any intermediate bus supply.
The voltage settings (margin high/low and nominal)
are programmed into nonvolatile memory through the
industry standard I2C 2-wire data bus. The I2C bus is
also used to enable margin high, margin low, ADOC or
normal operation. When margining, the SMM105 will
check the voltage output of the converter and make
adjustments to the trim pin via a feedback loop to bring
the voltage to the margin setting. A margining status
register is set to indicate that the system is ready for
test. The SMM105 ADOC will continue to monitor and
adjust the channel output at the specified level.
• ADOC Automatically adjusts supply output
voltage level under all DC load conditions
• Capable of margining supplies with trim inputs
using either positive or negative trim pin control
• Wide Margin/ADOC range from 0.3V to VDD
• Uses either an internal or external VREF
• Operates from any intermediate bus supply
from 8V to 15V and from 2.7V to 5.5V
• Programmable START and READY pins
• Two programmable general purpose monitor
sensors – UV and OV with FAULT Output Flag
• General Purpose 1k EEPROM with Write Protect
• I2C 2-wire serial bus for programming
configuration and monitoring status.
• 28 pad QFN or 25 ball Ultra CSPTM (Chip-Scale)
package
Applications
• In-system test and control of Point-of-Load
(POL) Power Supplies for Multi-voltage
Processors, DSPs and ASICs
• Enterprise and edge routers, servers, Storage
Area Networks
SIMPLIFIED APPLICATIONS DRAWING
VDD
WP#
12VIN
12VIN (6V to 15V)
3.3/5Vin (2.7V to 5.5V)
TRIM_CAP
SDA
VIN
FILT_CAP
DC/DC
Converter
SCL
A2
I2C
BUS
TRIM
A1
TRIM
V-
GND
VM
VDD_CAP
COMP1
SMM105
COMP2
VREF_CNTL
OV
uP/
DSP/
FPGA/
ASIC
UV
GND
READY
START
POWER GOOD
1.2 VIN
ON/OFF
A0
Internal or
External
Voltage
Reference
V+
FAULT#
FAULT#
READY
Figure 1 – Applications Schematic using the SMM105 Controller to actively control the DC output level
(ADOC) of a DC/DC Converter as well as margin control. The SMM105 can operate over a wide supply range
Note: This is an applications example only. Some pins, components and values are not shown.
© SUMMIT Microelectronics, Inc. 2005 • 1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897
2068 1.8 09/20/05
www.summitmicro.com
1
SMM105
Preliminary Information
Figure 2 – Example Power Supply Margining using the SMM105. The waveform on the left is margin low to
high from 1.6V to 2.0V and the waveform on the right is margin high to nominal from 2.0V to 1.8V. The ADOC
function guarantees the output level to be within ±0.2% with a ±0.1% external reference. The bottom
waveform is the READY signal indicating margin is complete.
GENERAL DESCRIPTION
The SMM105 is capable of controlling and margining
the DC output voltage of LDOs or DC/DC converters
that use a trim/adjust pin and to automatically change
the level using a unique Active DC Output Control
(ADOCTM). The ADOC function is programmable over
a standard 2-wire I2C serial data interface and can be
used to set the nominal DC output voltage as well as
the margin high and low settings. The part actively
controls the programmed set levels to maintain tight
control over load variations and voltage drops at the
point of load. The margin range will vary depending on
the supply manufacturer and model but the normal
range is 10% adjustment around the nominal output
setting. However, the SMM105 has the capability to
margin from VREF_CNTL to VDD.
The user can set the desired voltage settings
(nominal, margin high and margin low) into the EE
memory array for the device. Then, volatile registers
are used to select one of these settings. The registers
are accessed over the I2C bus.
In normal operation, Active DC Output Control is set to
adjust the nominal output voltage of the converter.
Typical converters have ±2% accuracy ratings for their
output voltage. Using the Active DC Output Control
feature of the SMM105 can increase the accuracy to
±0.1%. This high accuracy control of the converter
output voltage is extremely important in low voltage
applications where deviations in power supply voltage
can result in lower system performance. Active DC
Output Control can also be used for margining a
supply during system test or may be turned off by deselecting the function in the Control Select Register.
The margin high and margin low voltage settings can
range from 0.3V to VDD around the converters’
Summit Microelectronics, Inc
nominal output voltage setting depending on the
specified margin range of the DC-DC converter.
When the SMM105 receives the command to margin,
the Active DC Output Control will adjust the supply to
the selected margin voltage. Once the supply has
reached its margined set point, the Ready bit in the
status register will set and the READY pin will go
active. If Active DC Control is disabled, a margined
supply can return to its nominal voltage by writing to
the margin command register.
In order to obtain maximum accuracy, the SMM105
requires an external voltage reference. An external
reference with ±0.1% accuracy will enable an overall
±0.2% accuracy for the device. A configuration option
also exists so that an internal voltage reference can be
used, but with less accuracy. Total accuracy using the
internal reference is ±0.5%. The SMM105 can be
powered from either a 12V or 8V input via an internal
regulator or the VDD input (Figure 3).
The SMM105 has two additional input pins and one
additional output pin. The input pins, COMP1 and
COMP2, are high impedance inputs, each connected
to a comparator and compared against the
VREF_CNTL input or the internal reference (VREF).
Each comparator can be independently programmed
to monitor for UV or OV. When either of the COMP1
or COMP2 inputs are in fault the open-drain FAULT#
output will be pulled low. A configuration option exists
to disable the FAULT# output during margining.
Programming of the SMM105 is performed over the
industry standard I2C 2-wire serial data interface. A
status register is available to read the state of the part
and a Write Protect (WP#) pin is available to prevent
writing to the configuration registers and EE memory.
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SMM105
Preliminary Information
INTERNAL BLOCK DIAGRAM
VREF_CNTL
R EADY
MUX
V R EF
FA ULT#
V+
CO MP1
O V/UV
CO MP2
V-
O utput
Control
Trim
Drive
TRIM
TRIM _CAP
O V/UV
S TA RT
W P#
I 2 C Serial
Interface
A0
A1
A2
SD A
Input Voltage
Sensing and
Signal
Conditioning
SCL
12V IN
3.6/5V
Regulator
EE
Configuration
Registers
& M em ory
Supply
Arbitration
V DD
VDD_C AP
VM
Figure 3 – SMM105 Controller Internal Block Diagram.
PACKAGE AND PIN CONFIGURATION
28 Pin QFN
25 Ball Ultra CSPTM
Bottom View
SDA
NC
NC
NC
NC
VDD_CAP
12VIN
Top View
Pin 1
Pin 1
28 27 26 25 24 23 22
SCL
A2
START
A1
READY
A0
GND
1
21
2
20
3
19
SMM105
4
18
5
17
6
16
7
15
9 10 11 12 13 14
Summit Microelectronics, Inc
A2
A1
A2
A3
A4
A5
START
A1
NC
VDD
TRIM
B1
B2
B3
B4
B5
READY
A0
NC
C1
C2
C3
SDA VDD_CAP 12VIN
COMP1 TRIM_CAP
GND VREF_CNTL FAULT#
D1
D2
D3
WP# FILT_CAP COMP2
WP#
VREF_CNTL
FILT_CAP
FAULT#
COMP2
NC
VM
8
VDD
TRIM
COMP1
TRIM_CAP
NC
NC
NC
SCL
E1
2068 1.8 09/20/05
E2
E3
C4
C5
NC
NC
D4
D5
VM
NC
E4
E5
3
SMM105
Preliminary Information
PIN DESCRIPTIONS
QFN
Pad
Number
Ultra
CSPTM
Ball
Number
Pin
Type
28
1
2
4
6
A3
A1
A2
B2
C2
DATA
CLK
I
I
I
SDA
SCL
A2
A1
A0
8
E1
I
WP#
Write Protect active low input. When asserted, writes to the
configuration registers and general purpose EE are not allowed.
10
E2
CAP
FILT_CAP
External capacitor input used to filter the VM input.
18
C5
CAP
TRIM_CAP
External capacitor input used for Active Control and margining.
20
B5
O
TRIM
14
E4
I
VM
9
D2
I
VREF_CNTL
21
B4
PWR
VDD
7
D1
GND
GND
22
A5
PWR
12VIN
3
B1
I
START
5
C1
I/O
READY
23
A4
CAP
19
C4
12
Pin Name
Pin Description
I2C Bi-directional data line
I2C clock input.
The address pins are biased either to VDD_CAP or GND. When
communicating with the SMM105 over the 2-wire bus these pins
provide a mechanism for assigning a unique bus address.
Output voltage used to control and/or margin converter voltages.
Connect to the converter trim input.
Voltage monitor input. Connect to the DC-DC converter positive
sense line or its’ +Vout pin.
Voltage reference input used for DC output control and margining.
VREF_CNTL can be programmed to output the internal 1.25V
reference. Pin should be left open if using VREF internal
Power supply of the part.
Ground of the part. The SMM105 ground pin should be connected
to the ground of the device under control or to a star point ground.
PCB layout should take into consideration ground drops.
12V power supply input internally regulated to either 3.6V or 5.5V.
When using the 3.6V internal regulator option, the 12VIN input can
be as low as 8V. It can be as high as 15V using the 5.5V internal
regulator.
Programmable active high/low input. The START input is used
solely for enabling Active Control and/or margining. There is also
a programmable start delay time, TSTART to delay ADOC/Margin
control.
Programmable active high/low open drain output indicates that VM
is at its set point. When programmed as an active high output,
READY can also be used as an input. When pulled low, it will latch
the state of the comparator inputs.
VDD_CAP
External capacitor input used to filter the internal supply rail.
I
COMP1
E3
I
COMP2
11
D3
O
FAULT#
COMP1 and COMP2 are high impedance inputs, each connected
internally to a comparator and compared against the VREF_CNTL
input. Each comparator can be independently programmed to
monitor for UV or OV. The monitor level is set externally with a
resistive voltage divider.
When either of the COMP1 or COMP2 inputs are in fault the opendrain FAULT# output will be pulled low. A configuration option
exists to disable the FAULT# output while the device is margining.
13,15,16
17,24-27
B3,C3,
D4,D5,
E5
NC
Summit Microelectronics, Inc
NC
No Connect. Leave floating; do not connect anything to the NC
pins.
2068 1.8 09/20/05
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SMM105
Preliminary Information
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Temperature Under Bias ...................... -55°C to 125°C
Storage Temperature QFN ................... -65°C to 150°C
Terminal Voltage with Respect to GND:
VDD Supply Voltage ..........................-0.3V to 6.0V
12VIN Supply Voltage......................-0.3V to 15.0V
All Others ................................-0.3V to VDD + 0.7V
Output Short Circuit Current ............................... 100mA
Junction Temperature.........................…….....…...125°C
ESD Rating per JEDEC……………………..……..2000V
Latch-Up testing per JEDEC………..……......…±100mA
Temperature Range (Industrial) .......... –40°C to +85°C
(Commercial)............ –5°C to +70°C
VDD Supply Voltage.................................. 2.7V to 5.5V
12VIN Supply Voltage (1)........................ 8.0V to 14.0V
VIN.............................................................GND to VDD
VOUT.......................................................GND to 15.0V
Package Thermal Resistance (θJA)
28 Pad QFN…………….…………………….…80oC/W
25 Ball Ultra CSPTM………..………….…….…TBDoC/W
Note - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of the specification is
not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability. Devices are
ESD sensitive. Handling precautions are recommended.
Moisture Classification Level 1 (MSL 1) per J-STD- 020
Note 1 – Range depends on internal regulator set to 3.6V or 5.5V, see
12VIN specification below.
DC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min.
Typ.
Max
Unit
VDD
Supply Voltage
12VIN
Supply Voltage
VM
Positive Sense Voltage
VADOC
Power Supply Current from
VDD
Power Supply Current from
12VIN
TRIM output current
through 100Ω to 1.0V
Margin Control/ADOC
Range
VIH
Input High Voltage
VIL
Input Low Voltage
IDD
I12VIN
ITRIM
OV/UV
Programmable Open Drain
Output (READY)
Monitor Voltage Range
VHYST
Base DC Hysteresis
VOL
2.7
3.3
5.5
V
V
Internally regulated to 5.5V
10
15
Internally regulated to 3.6V
6
14
-0.3
VDD
V
VM pin
All TRIM pins and 12VIN floating
3
5
mA
All TRIM pins and VDD floating
3
5
mA
TRIM Sourcing Max Current
TRIM Sinking Max Current
Depends on Trim range of DCDC Converter
VDD = 2.7V
VDD = 5.0V
VDD = 2.7V
VDD = 5.0V
1.5
1.5
VREF_CNTL
VDD
0.9xVDD
0.7xVDD
VDD
VDD
0.1xVDD
0.3xVDD
ISINK = TBD
COMP1 and COMP2 pins
COMP1 and COMP2 pins,
VTH-VTL – Note 1
mA
mA
0.2
-0.3
3
V
V
V
VDD
10
V
V
mV
Note 1 – The Base DC Hysteresis voltage is measured with a 1.25V external voltage source. The resulting value is determined by subtracting
Threshold Low from Threshold High, VTH-VTL while monitoring the FAULT# pin state. Base DC Hysteresis is measured with a 1.25V input. Actual DC
Hysteresis is derived from the equation: (VIN/VREF)(Base Hysteresis). For example, if VIN=2.5V and VREF=1.25V then Actual DC Hysteresis=
(2.5V/1.25V)(0.003V)=6mV.
Summit Microelectronics, Inc
2068 1.8 09/20/05
5
SMM105
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min.
Typ.
Max
Unit
VREF
1.25VREF Output Voltage
VREF_CNTL
External VREF Voltage
Range
ADOCACC
RLOAD = 2KΩ to GND
1.24
1.25
0.25
1.26
V
VDD
V
External VREF=1.25V, ±0.1%
-0.2
±0.1
+0.2
%
ADOC trimmed to internal VREF
-0.5
±0.3
+0.5
%
ADOC/Margin Accuracy
AC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min.
Typ.
Max
Unit
tDC_CONTROl
Tsettling
TTRIM
Tstart
Active DC Control sampling period
Update period for Active
DC Control
1.7
ms
Settling Time
+ 10% change in voltage
with 0.1% ripple
100
ms
Fast Margin, nom to high,
TRIM_CAP=1µF
20
ms
Slow Margin, nom to high,
TRIM_CAP=1µF
200
ms
0.2
ms
12.8
ms
25.6
ms
51.2
ms
Trim Speed
Programmable Start Time
Summit Microelectronics, Inc
ADOC/Margining Start
time delay after Start pin is
enabled
2068 1.8 09/20/05
6
SMM105
Preliminary Information
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100/400kHz
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 4 Timing Diagram.
Conditions
Symbol
Description
fSCL
SCL Clock Frequency
tLOW
Clock Low Period
tHIGH
Clock High Period
100kHz
Min
Typ
0
Before New Transmission
- Note 1/
400kHz
Max
Min
100
0
Typ
Max
Units
400
KHz
4.7
1.3
µs
4.0
0.6
µs
4.7
1.3
µs
tBUF
Bus Free Time
tSU:STA
Start Condition Setup Time
4.7
0.6
µs
tHD:STA
Start Condition Hold Time
4.0
0.6
µs
tSU:STO
Stop Condition Setup Time
4.7
0.6
µs
tAA
Clock Edge to Data Valid
SCL low to valid
SDA (cycle n)
0.2
tDH
Data Output Hold Time
SCL low (cycle n+1)
to SDA change
0.2
tR
SCL and SDA Rise Time
Note 1/
1000
1000
ns
tF
SCL and SDA Fall Time
Note 1/
300
300
ns
tSU:DAT
Data In Setup Time
250
150
ns
tHD:DAT
Data In Hold Time
0
0
ns
TI
Noise Filter SCL and SDA
tWR
Write Cycle Time
Noise suppression
3.5
0.2
0.9
0.2
100
µs
µs
100
5
ns
5
ms
Note: 1/ - Guaranteed by Design.
TIMING DIAGRAMS
tR
tF
tSU:SDA
t HD:SDA
t W R (For W rite O peration Only)
tHIGH
t LOW
SCL
SDA
tSU:DAT
tSU:STO
tBUF
(IN)
tAA
SDA
tHD:DAT
t DH
(OUT)
Figure 4 . Basic I2C Serial Interface Timing
Summit Microelectronics, Inc
2068 1.8 09/20/05
7
SMM105
Preliminary Information
APPLICATIONS INFORMATION
DEVICE OPERATION
POWER SUPPLY
The SMM105 can be powered by either an 8V to 15V
input through the 12VIN pin or by a 2.7V to 5.5V input
through the VDD pin (Figure 5). The 12VIN pin feeds
an internal programmable regulator that internally
generates either 5.5V or 3.6V. The internal regulator
must be set to 3.6V if using an 8V supply. A voltage
arbitration circuit allows the device to be powered by
the highest voltage from either the regulator output or
the VDD input.
This voltage arbitration circuit
continuously checks for these voltages to determine
which will power the SMM105. The resultant internal
power supply rail is connected to the VDD_CAP pin
that allows both filtering and hold-up of the internal
power supply.
VOLTAGE REFERENCE
The SMM105 can operate using either an internal or
external voltage reference, VREF. The internal VREF
is set to 1.25V. Total accuracy with a ±0.1% external
reference is ±0.2% and ±0.5% using the internal
reference.
MODES OF OPERATION
The SMM105 has two basic modes of operation: UV
and OV monitoring mode and supply margining mode
,and one key feature, Active DC Output Control
(ADOCTM). A detailed description of each mode and
feature follows.
ACTIVE DC OUTPUT CONTROL (ADOCTM)
The SMM105 can control the DC output voltage of
bricks or DC/DC converters that have a trim pin. The
TRIM pin on the SMM105 is connected to the trim
input pin on the power supply converter. A sense line
from the channel’s point-of-load connects to the VM
input. The Active DC Control function cycles every
1.7ms making slight adjustments to the voltage on the
TRIM output pin based on the voltage input on the VM
pin. This voltage adjustment allows the SMM105 to
control the output voltage of the power supply
converter to within ±0.2% when using a ±0.1%
external voltage reference.
Summit Microelectronics, Inc
The voltage on the TRIM_CAP pins is buffered and
applied to the TRIM pin. The voltage adjustments on
the TRIM pin cause a slight ripple of less than 1mV on
the power supply voltage. The amplitude of this ripple
is a function of the TRIM_CAP capacitor and the trim
gain of the converter. Calculation of the TRIM_CAP
capacitor to achieve a desired minimum ripple is
detailed in Application Note 37.
The device can be programmed to either enable or
disable the ADOC function. When disabled or not
active, the TRIM pin on the SMM105 is a high
impedance input. The voltage on the TRIM pin is
buffered and applied to the TRIM_CAP pin charging
the capacitor. This allows a smooth transition from the
converter’s nominal voltage to the SMM105 controlling
that voltage to the ADOC nominal setting.
There are programmable Start times, TSTART, which are
used to delay the ADOC function to allow the
controlled supply to turn fully on before changing the
output voltage level. There is also a programmable
Speed-Up Convergence option.
This option
decreases the time required to bring a supply voltage
from the converter’s nominal output voltage to the
Active DC Output Control nominal voltage setting.
MONITORING
The SMM105 monitors the COMP1 and COMP2
inputs as well as the VM pin. COMP1 and COMP2
are high impedance inputs, each connected internally
to a comparator and compared against the
VREF_CNTL input.
Each comparator can be
independently programmed to monitor for either UV or
OV. The monitor level is set externally with a resistive
voltage divider. The part can be programmed to trigger
the FAULT# pin when either COMPx comparator has
exceeded the UV or OV range. The READY and
FAULT# outputs of the SMM105 are active as long as
the triggering limit remains in a fault condition. The
READY pin is programmable active high/low open
drain output indicates that VM is at its’ set point.
When programmed as an active high output, READY
can also be used as an input. When pulled low, it will
latch the state of the comparator inputs. When either
of the COMP1 or COMP2 inputs are in fault, the opendrain FAULT# output will be pulled low.
A
configuration option exists to disable the FAULT#
output while the device is margining mode.
2068 1.8 09/20/05
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SMM105
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
STATUS REGISTER
A status register exists for I2C polling of the status of
the COMP1 and COMP2 inputs. Two bits in this
status register reflect the current state of the inputs (1
= fault, 0 = no fault). Two additional bits show the
state of the inputs latched by one of two events
programmed in the configuration. The first event
option is the FAULT# output going active. The second
event option is the READY pin going low. The READY
pin is an I/O. As an output, the READY output pin
goes active when the DC controlled voltages are at
their set point. As an input programmed to active high,
it can be pulled low externally and latch the state of
the COMP inputs. This second event option allows
the state of the COMP inputs on multiple devices to be
latched at the same time while a host monitors their
FAULT# outputs.
MARGINING
The SMM105 has two additional Active DC Output
Control voltage settings: margin high and margin low.
The margin high and margin low settings can be as
much as ±10% of the nominal setting depending on
the manufacturer. The SMM105 range can be as
large as VREF_CNTL to VDD. These settings are
stored in the configuration registers and are loaded
into the Active DC Output Control voltage setting by
margin commands issued via the I2C bus. The device
must be enabled for Active DC Output Control in order
to enable margining.
The margin command registers contain two bits that
decode the commands to margin high, margin low, or
control to the nominal setting. Once the SMM105
receives the command to margin the supply voltage, it
begins adjusting the supply voltage to move toward
the desired setting. When this voltage setting is
reached, a bit is set in the margin status registers and
the READY signal becomes active. (Figure 5)
Note: Configuration writes or reads of registers 00HEX
to 03HEX should not be performed while the SMM105 is
margining.
WRITE PROTECTION
Write protection for the SMM105 is located in a volatile
register where the power-on state is defaulted to write
protect. There are separate write protect modes for the
configuration registers and memory. In order to
remove write protection, the code 55HEX is written to
the write protection register. Other codes will enable
write protection. For example, writing 59HEX will allow
writes to the configuration register but not to the
memory, while writing 35HEX will allow writes to the
memory but not to the configuration registers. The
SMM105 also features a Write Protect pin (WP# input)
which, when asserted, prevents writing to the
configuration registers and EE memory. In addition to
these two forms of write protection there is a
configuration register lock bit which, once
programmed, does not allow the configuration
registers to be changed.
F
Figure 5 – SMM105 margin example. The nominal setting is 1.8V. The device margins the DC-DC converter
from nominal to high, 2.0V then to nominal, then to low, 1.6V. Next it margins to nominal then high and then
from high to low and to high again. The READY signals goes low when margining and high when complete.
Summit Microelectronics, Inc
2068 1.8 09/20/05
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SMM105
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
VDD (+2.7V to +5.5V)
The SMM105 and the DC-DC Converter
Can Operate with either 12V or VDD
If 12V is used, VDD can be left floating
If VDD is used, 12V can be left floating
C8
0.1uF
Vdd
C2
0.1uF
C4
0.1uF
C7
0.01uF
J1
U4
5
LM4121
VOut
Ext VRef
1
Ref
13
15
16
17
24
25
26
27
FILT_CAP
WP#
2
18
20
14
19
12
VOUT
U2
C10
10 0.01uF
8
C9
0.01uF
SCL
SDA
A0
A1
A2
SMM105
NC
NC
NC
NC
NC
NC
NC
NC
1
28
6
4
2
TRIM_CAP
TRIM
VM
COMP1
COMP2
GND
FAULT#
START
READY
FAULT#
Gnd
SCL
Gnd3
SDA
Rsrv5
MR
+10V Rsrv8
+5V Rsrv10
RT2
~10K
t t
7
8
11
9
DC-DC Converter
+Vout
+Vout
+Vout
Sense
+Vin
+Vin
Enable
+Vin
C5
0.02uF
R1
10K
J1
1
3
5
7
9
3
C1 1uF
7
3
5
11
READY
EN
9
U1
START
VREF_CNTL
R9
10K
VDD
VDD_CAP
12VIN
R8
10K
21
23
22
C6
0.1uF
VIn
Vdd
4
Gnd
Gnd
C3
0.01uF
R2
10K
Trim
1
2
4
3
10
5
6
DIODE
If the SMM105 internal VREF
is used, the VREF_CNTL pin
becomes an output
~10K RT1
D1
Gnd
+12VIN (+10V to +15V)
Supply J2
DC-DC ENABLE
2
4
6
8
10
SMX3200 I2C Programming
Connector 10 pin Header
Figure 6 – SMM105 Applications schematic. The accuracy of the external (U4) or internal reference sets the
accuracy of the ADOC function. Total accuracy with a ±0.1% external reference is ±0.2% and ±0.5% with the
internal reference. The 12V supply can go as low as 8V if the internal regulator is set to 3.6V.
Summit Microelectronics, Inc
2068 1.8 09/20/05
10
SMM105
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
+12VIN (+10V to +15V)
C7
0.1uF
0.01uF
C8
0.1uF
For Example:
If Vout=3.3V, R4=63.4K, 15% of Vout=0.5V
ITRIM=8uA, RTRIM=62.5K
Therefore Rtrim standard 1% value down from 62.
R2 10K
1
28
6
4
2
SCL
SDA
A0
A1
A2
9
SMM105
NC
NC
NC
NC
NC
NC
NC
NC
R1 10K
D1
13
15
16
17
24
25
26
27
DIODE
TRIM_CAP
TRIM
VM
COMP1
COMP2
FILT_CAP
WP#
GND
FAULT#
START
READY
FAULT#
C1 1uF
18
20
14
19
12
R3
RTRIM
VOUT
U2
Switching Regulator
+Vin
10
8
R4
RSET1
+Vout
PGOOD
C5
0.02uF
VADJ (VREF)
R5
20k
START
7
3
5
11
READY
VREF_CNTL
U1
R8 10K
START
VDD
VDD_CAP
12VIN
R7 10K
21
23
22
R6 10K
Gnd
C4
RTRIM(R3) is calculated as follows:
VTRIMlow=0.3V, Regulator VREF=0.8V
The current through R3 is ITRIM=(0.8-0.3)/RTRIM
(ITRIM)(R4) > 15% of VOUT
RTRIMmax should be < the calculated value
J1
1
3
5
7
9
Gnd
SCL
Gnd3
SDA
Rsrv5
MR
+10V Rsrv8
+5V Rsrv10
2
4
6
8
10
SMX3200 I2C Programming
Connector 10 pin Header
R1 and R2 need only be
placed once on the I2C bus
The SMM105 START pin must be inactive during power-up so
that the TRIM pin is high impedence. Once power is nominal,
the START pin can be active to start margin and ADOC
functions
Figure 7 – SMM105 Applications schematic for an adjustable switching regulator (Full regulator circuit not
shown).
Summit Microelectronics, Inc
2068 1.8 09/20/05
11
SMM105
Preliminary Information
DEVELOPMENT HARDWARE & SOFTWARE
The Windows GUI software will generate the data and
send it in I2C serial bus format so that it can be directly
downloaded to the SMM105 via the programming
Dongle and cable. An example of the connection
interface is shown in Figure 8.
The end user can obtain the Summit SMX3200
programming
system
for
device
prototype
development. The SMX3200 system consists of a
programming Dongle, cable and WindowsTM GUI
software. It can be ordered on the website or from a
local representative. The latest revisions of all
software and an application brief describing the
SMX3200
is
available
from
the
website
(www.summitmicro.com).
The SMX3200 programming Dongle/cable
directly between a PC’s parallel port and
application. The device is then configured
via an intuitive graphical user interface
drop-down menus.
When design prototyping is complete, the software
can generate a HEX data file that should be
transmitted to Summit for approval. Summit will then
assign a unique customer ID to the HEX code and
program production devices before the final electrical
test operations.
This will ensure proper device
operation in the end application.
interfaces
the target
on-screen
employing
Top view of straight 0.1" x 0.1 closed-side
connector. SMX3200 interface cable connector.
D1
Positive
Supply
Pin 10, Reserved
Pin 8, Reserved
Pin 6, MR#
Pin 4, SDA
Pin 2, SCL
1N4148
VDD_CAP
SMM105
W P#
SDA
SCL
10
8
6
4
2
9
7
5
3
1
Pin 9, 5V
Pin 7, 10V
Pin 5, Reserved
Pin 3, GND
Pin 1, GND
C1
0.1 µ F
GND
Com m on
Ground
Figure 8– SMX3200 Programmer I2C serial bus connections to program the SMM105. The SMM105 has a
Write Protect pin (WP# input) which when, asserted, prevents writing to the configuration registers and EE
memory. In addition, there is a configuration register lock bit which, once programmed, does not allow the
configuration registers to be changed.
Summit Microelectronics, Inc
2068 1.8 09/20/05
12
SMM105
Preliminary Information
I2C PROGRAMMING INFORMATION
SERIAL INTERFACE
Access to the configuration registers, general-purpose
memory and command and status registers is carried
out over an industry standard 2-wire serial interface
(I2C). SDA is a bi-directional data line and SCL is a
clock input. Data is clocked in on the rising edge of
SCL and clocked out on the falling edge of SCL. All
data transfers begin with the MSB. During data
transfers SDA must remain stable while SCL is high.
Data is transferred in 8-bit packets with an intervening
clock period in which an Acknowledge is provided by
the device receiving data. The SCL high period (tHIGH)
is used for generating Start and Stop conditions that
precede and end most transactions on the serial bus.
A high-to-low transition of SDA while SCL is high is
considered a Start condition while a low-to-high
transition of SDA while SCL is high is considered a
Stop condition.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
unique device addressing.
The address byte is
comprised of a 4-bit device type identifier (slave
address) and a 3-bit bus address. The remaining bit
indicates either a read or a write operation. Refer to
Table 1 for a description of the address bytes used by
the SMM105.
The device type identifier for the memory array, the
configuration registers and the command and status
registers are accessible with the same slave address.
It can be programmed to any four bit number 0000BIN
through 1111BIN.
The bus address bits A[2:0] are hard wired only
though address pins 2, 4 and 6 (A2, A1 and A0). The
bus address accessed in the address byte of the serial
data stream must match the setting on the SMM105
address pins.
Summit Microelectronics, Inc
WRITE
Writing to the memory or a configuration register is
illustrated in Figures 9, 10, 11, 13, 14 and 16. A Start
condition followed by the address byte is provided by
the host; the SMM105 responds with an Acknowledge;
the host then responds by sending the memory
address pointer or configuration register address
pointer; the SMM105 responds with an acknowledge;
the host then clocks in one byte of data. For memory
and configuration register writes, up to 15 additional
bytes of data can be clocked in by the host to write to
consecutive addresses within the same page. After
the last byte is clocked in and the host receives an
Acknowledge, a Stop condition must be issued to
initiate the nonvolatile write operation.
READ
The address pointer for the configuration registers,
memory, command and status registers and ADC
registers must be set before data can be read from the
SMM105. This is accomplished by issuing a dummy
write command, which is simply a write command that
is not followed by a Stop condition. The dummy write
command sets the address from which data is read.
After the dummy write command is issued, a Start
command followed by the address byte is sent from
the host. The host then waits for an Acknowledge and
then begins clocking data out of the slave device. The
first byte read is data from the address pointer set
during the dummy write command. Additional bytes
can be clocked out of consecutive addresses with the
host providing an Acknowledge after each byte. After
the data is read from the desired registers, the read
operation is terminated by the host holding SDA high
during the Acknowledge clock cycle and then issuing a
Stop condition. Refer to Figures 12, 15 and 17 for an
illustration of the read sequence.
WRITE PROTECTION
The SMM105 powers up into a write protected mode.
Writing a code to the volatile write protection register
(write only) can disable the write protection. The write
protection register is located at address 42HEX. Writing
to the write protection register is shown in Figure 9.
Writing 0101BIN to bits [7:4] of the write protection
register allow writes to the general-purpose memory
while writing 0101BIN to bits [3:0] allow writes to the
configuration registers. The write protection can be reenabled by writing other codes (not 0101BIN) to the
write protection register.
2068 1.8 09/20/05
13
SMM105
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
CONFIGURATION REGISTERS
The majority of the configuration registers are grouped
with the general-purpose memory. Writing and reading
the configuration registers is shown in Figures 10, 11
and 12.
Note: Configuration writes or reads of registers 00HEX
to 03HEX should not be performed while the SMM105
is margining.
GENERAL-PURPOSE MEMORY
The 1k-bit general-purpose memory is located at any
slave address. The bus address bits are hard wired
by the address pins A2, A1 and A0. Memory writes
and reads are shown in Figures 13, 14 and 15.
Slave Address
ANY
Bus Address
A2 A1 A0
COMMAND AND STATUS REGISTERS
Writes and reads of the command and status registers
are shown in Figures 16 and 17.
GRAPHICAL USER INTERFACE (GUI)
Device configuration utilizing the Windows based
SMM105 graphical user interface (GUI) is highly
recommended. The software is available from the
Summit website (www.summitmicro.com). Using the
GUI in conjunction with this datasheet and Application
Note 38, simplifies the process of device prototyping
and the interaction of the various functional blocks. A
programming Dongle (SMX3200) is available from
Summit to communicate with the SMM105. The
Dongle connects directly to the parallel port of a PC
and programs the device through a cable using the I2C
bus protocol. See figure 8 and the SMX3200 Data
Sheet.
Register Type
Configuration Registers are located in
00 HEX thru 45HEX
General-Purpose Memory is located in
80 HEX thru FFHEX
Table 1 - Address bytes used by the SMM105.
Summit Microelectronics, Inc
2068 1.8 09/20/05
14
SMM105
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
M aster
S
T
A
R
T
Configuration
Register Address = 42 HEX
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
W
1
0
A
C
K
Slave
0
0
0
0
4 HEX
S
T
O
P
Data = 55 HEX
1
0
0
1
0
1
0
1
0
1
A
C
K
2 HEX
A
C
K
W rite Protection
Register Address
5 HEX Unlocks
General Purpose
EE
5 HEX Unlocks
Configuration
Registers
Figure 9 – Write Protection Register Write
M aster
S
T
A
R
T
Configuration
Register Address
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
C
6
C
7
W
C
5
C
4
C
3
Data
C
2
C
1
C
0
D
7
A
C
K
Slave
S
T
O
P
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 10 – Configuration Register Byte Write
M aster
S
T
A
R
T
Configuration
Register Address
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
D
7
D
6
D
7
D
6
D
5
D
4
D
3
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
S
T
O
P
Data (16)
Data (2)
M aster
Slave
C
7
W
Data (1)
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
A
C
K
D
0
D
7
D
6
D
5
D
4
A
C
K
D
3
D
2
D
1
D
0
A
C
K
Figure 11 – Configuration Register Page Write
Summit Microelectronics, Inc
2068 1.8 09/20/05
15
SMM105
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
M aster
S
T
A
R
T
Configuration
Register Address
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
S
T
A
R
T
A
0
C
7
W
C
6
C
5
C
4
C
3
C
2
C
1
S
A
3
C
0
A
C
K
Slave
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
A
2
S
A
0
A
2
A
1
A
0
R
A
C
K
A
C
K
D
0
S
A
1
A
C
K
A
C
K
Data (1)
M aster
Bus Address
D
7
D
6
D
5
D
2
D
1
N
A
C
K
Data (n)
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
Slave
Figure 12 - Configuration Register Read
M aster
S
T
A
R
T
Configuration
Register Address
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
C
6
C
7
W
C
5
C
4
C
3
Data
C
2
C
1
C
0
D
7
A
C
K
Slave
S
T
O
P
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 13 – General Purpose Memory Byte Write
M aster
S
T
A
R
T
Configuration
Register Address
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
D
7
D
6
D
7
D
6
D
5
D
4
D
3
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Data (2)
M aster
Slave
C
7
W
Data (1)
S
T
O
P
Data (16)
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
A
C
K
D
0
D
7
D
6
D
5
D
4
A
C
K
D
3
D
2
D
1
D
0
A
C
K
Figure 14 - General Purpose Memory Page Write
Summit Microelectronics, Inc
2068 1.8 09/20/05
16
SMM105
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
M aster
S
T
A
R
T
Configuration
Register Address
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
S
T
A
R
T
C
7
W
C
6
C
5
C
4
C
3
C
2
C
1
M aster
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
S
A
1
S
A
0
A
2
A
1
A
0
R
A
C
K
A
C
K
D
7
S
A
2
A
C
K
A
C
K
Data (1)
S
A
3
C
0
A
C
K
Slave
Bus Address
D
6
D
5
D
2
D
1
D
0
N
A
C
K
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
Slave
Figure 15 - General Purpose Memory Read
M aster
S
T
A
R
T
Command and Status
Register Address
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
C
7
W
C
6
C
5
C
4
C
3
C
2
Data
C
1
C
0
A
C
K
Slave
S
T
O
P
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 16 – Command and Status Register Write
M aster
S
T
A
R
T
Command and Status
Register Address
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
S
T
A
R
T
C
7
W
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
M aster
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
S
A
1
S
A
0
A
2
A
1
A
0
R
A
C
K
A
C
K
D
7
S
A
2
A
C
K
A
C
K
Data (1)
Bus Address
S
A
3
D
6
D
5
D
2
D
1
D
0
N
A
C
K
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
Slave
Figure 17 - Command and Status Register Read
Summit Microelectronics, Inc
2068 1.8 09/20/05
17
SMM105
Preliminary Information
DEFAULT CONFIGURATION REGISTER SETTINGS – SMM105NC-160
Register
R00
R01
Contents
02
C7
R04
25
R05
05
R06
03
R08
R0C
R0D
R20
R21
R30
R31
R40
R41
R42
R44
00
12
50
02
A1
02
F0
80
03
FF
00
Function
Nominal Voltage is set to 1.800V (MSB)
Nominal Voltage is set to 1.800V (LSB)
ADOC is enabled, Trim polarity is inverse, Fast Convergence, VREF External, Fault
Latched by a Fault Condition
Slave address is 0101, Start Delay set to 0.2ms
No Write Command Required to Activate ADOC, Internal Regulator set to 3.6V,
Fault Output Enabled While Margining, Configuration Registers Unlocked, COMP1
and COMP2 are set to sense OV
Margin Command Bits
Stores VREF_CNTL value set to 1.25
Stores VREF_CNTL value set to 1.25
Margin High Voltage is set to 1.902V (MSB)
Margin High Voltage is set to 1.902V (LSB)
Margin Low Voltage is set to 1.702V (MSB)
Margin Low Voltage is set to 1.702V (LSB)
Margin Command Status Bits
READY and START pin Polarities set to Active High
Write Protect
Fault Status Bits
RC1
The default device ordering number is SMM105NC-160, is programmed as described above
and tested over the commercial temperature range. Application Note 38 contains a
complete description of the Windows GUI and the default settings of each of the 16
individual Configuration Registers.
Summit Microelectronics, Inc
2068 1.8 09/20/05
18
SMM105
Preliminary Information
PACKAGE
28 Pad QFN
Summit Microelectronics, Inc
2068 1.8 09/20/05
19
SMM105
Preliminary Information
PACKAGE (CONTINUED)
25 Ball Ultra CSPTM
Summit Microelectronics, Inc
2068 1.8 09/20/05
20
SMM105
Preliminary Information
PART MARKING
25 Ball Ultra CSPTM
28 Pad QFN
SUMMIT
SS
Ball A1
Identifier
Status Tracking Code
(Blank, MS, ES, 01, 02,...)
(Summit Use)
SMMX05V
XSSYWW
SMM105N
X is the sequential letter per wafer
(i.e. A for the first wafer, B for the second wafer,
C for the third wafer, etc.)
Summit
Part Number
Annn L AYYWW
Date Code (YYWW)
Pin 1
Lot tracking code (Summit use)
100% Sn, RoHS compliant, Green
Part Number suffix
(Contains Customer specific
ordering requirements)
Drawing not
to scale
Drawing not
to scale
Summit Part Number
100% Sn, RoHS
compliant, Green
Date Code
Y = Single digit year
(4=2004, 5=2005, etc)
Product Tracking Code (Summit use)
ORDERING INFORMATION
Summit
nnn
SMM105 N
V
C
Part
Number
Package
Temp Range
C=Commercial
N=28 Pad QFN
E=25 Ball Ultra CSPTM Blank=Industrial
V is the Lead-Free Attribute for the CSP
(E Package), L is for the QFN (N package)
Part Number Suffix (see page 18)
Customer specific requirements are contained
in the suffix such as Hex code, Hex code
revision, etc.
NOTICE
NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization.
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,
performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license
under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained
herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this
publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or
omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or
malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness.
Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that:
(a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc.
is adequately protected under the circumstances.
Revision 1.8 - This document supersedes all previous versions.
Please check the Summit Microelectronics, Inc. web site at
http://www.summitmicro.com/prod_select/summary/SMM105/SMM105.htm for data sheet updates.
© Copyright 2005 SUMMIT MICROELECTRONICS, Inc.
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is a trademark of Summit Microelectronics Inc.
Summit Microelectronics, Inc
PROGRAMMABLE POWER FOR A DIGITAL WORLD™
I2C is a trademark of Philips Corporation.
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