NCP432, NCP433 1.5A Ultra-Small Controlled Load Switch with Auto-Discharge Path The NCP432 and NCP433 are a low Ron MOSFET controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. Indeed, due to a current consumption optimization with PMOS structure, leakage currents are eliminated by isolating connected IC’s on the battery when not used. Output discharge path is also embedded to eliminate residual voltages on the output (NCP433 only). Proposed in wide input voltage range from 1.0 V to 3.6 V, and a very small 0.76 x 0.76 mm WLCSP4, 0.4 mm pitch. http://onsemi.com MARKING DIAGRAM WLCSP4 CASE 567FJ XX = AV or AT PINOUT Features • • • • • • • XX 1 V – 3.6 V Operating Range 50 mW P MOSFET at 1.8 V DC Current up to 1.5 A Output Auto−discharge (NCP433) Active High EN Pin WLCSP4 0.76 x 0.76 mm These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 1 2 A OUT IN B GND EN Typical Applications • • • • • Mobile Phones Tablets Digital Cameras GPS Portable Devices (Top View) ORDERING AND MARKING INFORMATION See detailed ordering and shipping information on page 6 of this data sheet. V+ LS NCP433 DCDC Converter A2 or LDO B2 IN OUT EN GND A1 Platform IC’n B1 ENx EN 0 Figure 1. Typical Application Circuit © Semiconductor Components Industries, LLC, 2013 December, 2013 − Rev. 1 1 Publication Order Number: NCP432/D NCP432, NCP433 PIN FUNCTION DESCRIPTION Pin Name Pin Number Type IN A2 POWER Load−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as close as possible to the IC. Description GND B1 POWER Ground connection. EN B2 INPUT OUT A1 OUTPUT Enable input, logic high turns on power switch. Load−switch output; connect a 1 mF ceramic capacitor from OUT to GND as close as possible to the IC is recommended. BLOCK DIAGRAM Figure 2. Block Diagram http://onsemi.com 2 NCP432, NCP433 MAXIMUM RATINGS Rating IN, OUT, EN, Pins: From IN to OUT Pins: Input/Output Symbol Value Unit VEN, VIN, VOUT −0.3 to + 4.0 V VIN, VOUT 0 to + 4.0 V TJ −40 to + 125 °C Maximum Junction Temperature TSTG −40 to + 150 °C Human Body Model (HBM) ESD Rating are (Notes 1 and 2) Storage Temperature Range ESD HBM 7000 V Machine Model (MM) ESD Rating are (Notes 1 and 2) ESD MM 250 V ESD CDM 2000 V Charge Device Model (CDM) ESD Rating are (Notes 1 and 2) Latch−up protection (Note 3) − Pins IN, OUT, EN LU Moisture Sensitivity (Note 4) MSL mA 100 Level 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. According to JEDEC standard JESD22−A108. 2. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±7.0 kV per JEDEC standard: JESD22−A114 for all pins. Machine Model (MM) ±250 V per JEDEC standard: JESD22−A115 for all pins. Charge Device Model (CDM) ±2.0 kV per JEDEC standard: JESD22−C101 for all pins. 3. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II. 4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020. OPERATING CONDITIONS Symbol Parameter VIN Operational Power Supply VEN Enable Voltage TA Ambient Temperature Range CIN Conditions Min Max Unit 1.0 3.6 V 0 3.6 −40 Decoupling input capacitor 1 COUT Decoupling output capacitor 1 RqJA Thermal Resistance Junction to Air IOUT Maximum DC current PD Power Dissipation Rating (Note 6) WLCSP package (Note 5) Typ 25 +85 °C mF mF 150 °C/W 1.5 A TA ≤ 25°C WLCSP package 0.5 W TA = 85°C WLCSP package 0.2 W 5. The RqJA is dependent of the PCB heat dissipation and thermal via. 6. The maximum power dissipation (PD) is given by the following formula: http://onsemi.com 3 NCP432, NCP433 ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C for VIN between 1.0 V to 3.6 V (Unless otherwise noted). Typical values are referenced to TA = + 25 °C and VIN = 3.3 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit POWER SWITCH TA = 25 °C, I = 200 mA (Note 8) VIN = 3.6 V TA = 85°C RDS(on) 55 TA = 25°C, I = 200 mA VIN = 3.3 V Static drain−source on− state resistance 35 37 TA = 85°C 60 TA = 25°C, I = 200 mA VIN = 1.8 V 50 TA = 85°C VIN = 1.2 V 80 TA = 25°C, I = 200 mA 100 TA = 85°C RDIS Output discharge path mW 150 VIN = 1.1 V TA = 25°C, I = 100 mA EN = low VIN = 3.3 V, NCP433 only 40 120 65 90 W TR Output rise time CLOAD = 1 mF, RLOAD = 25 W (Note 7) from 10% to 90% of VOUT 5 20 40 ms TF Output fall time CLOAD = 1 mF, RLOAD = 25 W (Note 7) 20 56 80 ms Ton Gate turn on Gate turn on + Output rise time 20 47 115 ms Ten Enable time From EN low to high to VOUT 10% 15 30 75 ms Tdis Disable time From EN high to low to VOUT = 90% of fully on 2 11 20 ms VIH High−level input voltage VIL Low−level input voltage VIN = 3.6 V 0.9 V 0.5 V QUIESCENT CURRENT IQ Current consumption VIN = 3.3 V, EN = low, No load 0.01 0.6 mA VIN = 3.3 V, EN = high, No load 0.2 0.6 mA 7. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground 8. Guaranteed by design and characterization, not production tested. TIMINGS VIN EN VOUT TEN TR TDIS TON TF TOFF Figure 3. Enable, Rise and Fall Time http://onsemi.com 4 NCP432, NCP433 TYPICAL CHARACTERISTICS 160 1.2 Temp = −40°C Temp = 25°C Temp = 85°C 140 120 1.0 0.8 IIN (mA) 100 IIN (mA) Temp = −40°C Temp = 25°C Temp = 85°C 80 60 0.6 0.4 40 0.2 20 0 0 0 1 2 VIN (V) 3 0 4 Figure 4. Standby Current versus Temperature 2 VIN (V) 3 4 Figure 5. Quiescent Current versus Temperature 300 350 ILOAD = 100 mA −40°C 0°C 50°C ILOAD = 100 mA 300 250 −25°C 25°C 85°C 250 200 RDS(on) (mW) RDS(on) (mW) 1 150 100 200 150 100 50 50 0 0 1 2 VIN (V) 3 0 4 0 Figure 6. RDS(on) versus VIN, 255C, 100 mA Load 1 2 VIN (V) 3 4 Figure 7. RDS(on) versus Temperature, 100 mA Load FUNCTIONAL DESCRIPTION Overview The auto−discharge is activated when EN pin is set to low level (disable state). The discharge path ( Pull down NMOS) stays activated as long as EN pin is set at low level and VIN > 1.0 V. In order to limit the current across the internal discharge N−MOSFET, the typical value is set at 65 W. The NCP432 – NCP433 are high side P channel MOSFET power distribution switch designed to isolate ICs connected on the battery in order to save energy. The part can be turned on, with a range of battery from 1.0 V to 3.6 V. Enable Input Enable pin is an active high. The path is opened when EN pin is tied low (disable), forcing P MOS switch off. The IN/OUT path is activated with a minimum of Vin of 1.0 V and EN forced to high level. Cin and Cout Capacitors IN and OUT, 1 mF, at least, capacitors must be placed as close as possible the part for stability improvement. Auto Discharge (NCP433 only) NMOS FET is placed between the output pin and GND, in order to discharge the application capacitor connected on OUT pin. http://onsemi.com 5 NCP432, NCP433 APPLICATION INFORMATION Power Dissipation TJ RqJA TA Main contributor in term of junction temperature is the power dissipation of the power MOSFET. Assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: P D + R DS(on) PD RDS(on) IOUT ǒIOUTǓ PCB Recommendations The NCP432 – NCP433 integrate an up to 1.5 A rated PMOS FET, and the PCB design rules must be respected to properly evacuate the heat out of the silicon. By increasing PCB area, especially around IN and OUT pins, the RqJA of the package can be decreased, allowing higher power dissipation. 2 = Power dissipation (W) = Power MOSFET on resistance (W) = Output current (A) TJ + PD = Junction temperature (°C) = Package thermal resistance (°C/W) = Ambient temperature (°C) R qJA ) T A ORDERING INFORMATION Marking Package Shipping† NCP432FCT2G AV WLCSP4 (Pb−Free) 3000 / Tape & Reel NCP433FCT2G AT WLCSP4 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NCP432, NCP433 PACKAGE DIMENSIONS WLCSP4, 0.76x0.76 CASE 567FJ ISSUE O A D PIN A1 REFERENCE 2X 0.05 C 2X ÈÈ NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. B E DIM A A1 A2 b D E e 0.05 C TOP VIEW A2 0.05 C A RECOMMENDED SOLDERING FOOTPRINT* 0.05 C NOTE 3 4X A1 0.05 C A B 0.03 C C SIDE VIEW e b MILLIMETERS MIN MAX 0.57 0.63 0.18 0.23 0.40 REF 0.24 0.28 0.76 BSC 0.76 BSC 0.40 BSC SEATING PLANE A1 4X 0.40 PITCH e B A PACKAGE OUTLINE 0.40 PITCH 0.20 DIMENSIONS: MILLIMETERS 1 2 BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP432/D