ONSEMI CM1205

8-Channel ESD Protection Array
in Chip Scale Package
CM1205
Features
Product Description
•
The CM1205 transient voltage suppressor array
provides a very high level of protection for sensitive
electronic components that may be subjected to
ESD.
•
•
•
•
•
Functionally and pin compatible with CMD’s
PACDN1408 ESD protection device
Eight transient voltage suppressors in a
single package
Optiguard coated for improved reliability at
assembly
In-system Electrostatic Discharge (ESD)
protection to +25kV contact discharge per IEC
61000-4-2 international standard
Compact Chip Scale Package (0.65mm pitch)
format saves board space and eases layout in
space critical applications compared to discrete
solutions and traditional wire bonded packages
RoHS compliant (lead-free) 10-bump CSP
TM
Applications
•
•
•
•
•
•
•
•
ESD protection for sensitive electronic equipment
I/O port, keypad and button circuitry protection for
portable devices
Wireless Handsets
Handheld PCs / PDAs
MP3 Players
Digital Cameras and Camcorders
Notebooks
Desktop PCs
The CM1205 will safely dissipate ESD strikes at
levels well beyond the maximum requirements set
forth in the IEC 61000-4-2 international standard
(Level 4, +8kV contact discharge). All I/Os are rated
at +25kV using the IEC 61000-4-2 contact discharge
method. Using the MIL-STD-883D (Method 3015)
specification for Human Body Model (HBM) ESD, all
pins are protected for contact discharges to greater
than +30kV.
The Chip Scale Package format of this device
enables extremely small footprints that are necessary
in portable electronics such as cellular phones,
PDAs, internet appliances and PCs. The large solder
bumps allow for standard attachment to laminate
boards without the use of underfill.
The CM1205 features OptiGuard
coating for
improved reliability at assembly and is available with
RoHS compliant lead-free finishing.
TM
Block Diagram
©2010 SCILLC. All rights reserved.
April 2010 – Rev. 3
Publication Order Number:
CM1205/D
CM1205
Ordering Information
PART NUMBERING INFORMATION
1
Bumps
Package
Ordering Part Number
Part Marking
10
CSP
CM1205-08CP
120508
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Storage Temperature Range
RATING
UNITS
-65 to +150
°C
STANDARD OPERATING CONDITIONS
PARAMETER
Operating Temperature Range
Rev. 3 | Page 2 of 8 | www.onsemi.com
RATING
UNITS
-40 to +85
°C
CM1205
ELECTRICAL OPERATING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VREV
Reverse Standoff Voltage
IDIODE=10µA
ILEAK
Leakage Current
VIN=3.3V DC
VSIG
Signal Clamp Voltage
Positive Clamp
Negative Clamp
ILOAD = 10mA
In-system ESD Withstand Voltage
a) Human Body Model, MIL-STD-883,
Method 3015
b) Contact Discharge per IEC 61000-4-2
Level 4
Note 2
Clamping Voltage during ESD Discharge
MIL-STD-883 (Method 3015), 8kV
Positive Transients
Negative Transients
Note 2
Channel Capacitance
At 2.5V DC, f = 1MHz,
VESD
VCL
C
MIN
TYP
1
MAX
6.0
5.6
-1.2
6.8
-0.8
UNITS
V
100
nA
8.0
-0.4
V
V
+30
kV
+25
kV
+12
-8
39
V
V
47
pF
Note 1: TA=25°C unless otherwise specified. GND in this document refers to the lower supply voltage.
Note 2: ESD applied to channel pins with respect to GND, one at a time. All other channels are open. All GND pins tied to
ground.
Rev. 3 | Page 3 of 8 | www.onsemi.com
CM1205
Application Information
Refer to Application Note AP-217, "The Chip Scale Package", for a detailed description of Chip Scale Packages
offered by California Micro Devices.
PRINTED CIRCUIT BOARD RECOMMENDATIONS
PARAMETER
VALUE
Pad Size on PCB
0.275mm
Pad Shape
Round
Pad Definition
Non-Solder Mask defined pads
Solder Mask Opening
0.325mm Round
Solder Stencil Thickness
0.125mm - 0.150mm
Solder Stencil Aperture Opening (laser cut, 5% tapered walls)
0.330mm Round
Solder Flux Ratio
50/50 by volume
Solder Paste Type
No Clean
Pad Protective Finish
OSP (Entek Cu Plus 106A)
Tolerance — Edge To Corner Ball
+50µm
Solder Ball Side Coplanarity
+20µm
Maximum Dwell Time Above Liquidous
60 seconds
Maximum Soldering Temperature
260ûC
Figure 3. Recommended Non-Solder Mask Defined Pad Illustration
Rev. 3 | Page 4 of 8 | www.onsemi.com
CM1205
Figure 4. Lead-free (SnAgCu) Solder Ball Reflow Profile
Rev. 3 | Page 5 of 8 | www.onsemi.com
CM1205
Mechanical Details
The CM1205 is offered in a custom Chip Scale
Package (CSP). Dimensions are presented below.
PACKAGE DIMENSions
Package
Custom CSP
Bumps
10
Dim
Millimeters
Min
Nom
Max
Inches
Min
Nom
Max
A1
1.109 1.154 1.199 0.0437 0.0454 0.0472
A2
3.059 3.104 3.149 0.1204 0.1222 0.1240
B1
0.645 0.650 0.655 0.0254 0.0256 0.0258
B2
0.645 0.650 0.655 0.0254 0.0256 0.0258
C1
0.202 0.252 0.302 0.0080 0.0099 0.0119
C2
0.202 0.252 0.302 0.0080 0.0099 0.0119
D1
0.612 0.682 0.751 0.0241 0.0268 0.0296
D2
0.368 0.419 0.470 0.0145 0.0165 0.0185
# per tape and
reel
Package Dimensions for CM1205 Chip Scale
Package
3500 pieces
Controlling dimension: millimeters
Rev. 3 | Page 6 of 8 | www.onsemi.com
CM1205
CSP Tape and Reel Specifications
POCKET SIZE (mm) TAPE WIDTH
B0 X A0 X K0
W
PART NUMBER
CHIP SIZE (mm)
CM1205-08CP
3.104 X 1.154 X 0.682
3.28 X 1.32 X 0.81
8mm
Figure 5. Tape and Reel Mechanical Data
Rev. 3 | Page 7 of 8 | www.onsemi.com
REEL
DIAMETER
QTY
PER
REEL
P0
P1
178mm (7")
3500
4mm
4mm
CM1205
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
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Rev. 3 | Page 8 of 8 | www.onsemi.com
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