SCAS185A − AUGUST 1990 − REVISED APRIL 1993
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DW OR N PACKAGE
Inputs Are TTL-Voltage Compatible
Contains Six D-Type Flip-Flops
Clock Enable Latched to Avoid False
Clocking
Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin VCC and GND Pin Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages, and Standard
Plastic 300-mil DIPs
(TOP VIEW)
1Q
2Q
3Q
GND
GND
GND
GND
4Q
5Q
6Q
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
CLKEN
1D
2D
3D
VCC
VCC
4D
5D
6D
CLK
description
These circuits are positive-edge-triggered D-type flip-flops with a clock-enable input. Information at the D inputs
meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse
if the clock-enable input (CLKEN) is low.
Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the
positive-going pulse. When the clock inputs are at either the high or low level, the data (D) input signal has no
effect at the output. The circuits are designed to prevent false clocking by transitions at the clock-enable
(CLKEN) input.
The 74ACT11378 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
D
OUTPUT
Q
X
X
QO
↑
H
H
CLKEN
CLK
H
L
L
↑
L
L
X
L
X
QO
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
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• DALLAS, TEXAS 75265
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POST OFFICE BOX 655303
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1
SCAS185A − AUGUST 1990 − REVISED APRIL 1993
logic symbol†
CLKEN
CLK
1D
2D
3D
4D
5D
6D
20
11
19
G1
1C2
1
2D
18
2
17
3
14
8
13
9
12
10
1Q
2Q
3Q
4Q
5Q
6Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram (positive logic)
CLKEN
CLK
20
11
C1
1D
19
C1
2D
18
17
5D
14
2
8
1D
C1
13
9
1D
C1
6D
3
1D
C1
4D
2
1D
C1
3D
1
1D
12
1D
•
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
10
1Q
2Q
3Q
4Q
5Q
6Q
SCAS185A − AUGUST 1990 − REVISED APRIL 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±150 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
MIN
NOM
MAX
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t/∆v
High-level input voltage
2
UNIT
V
V
0.8
V
VCC
VCC
V
High-level output current
−24
mA
Low-level output current
24
mA
0
10
ns/V
−40
85
°C
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 2: Unused or floating inputs must be held high or low.
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = − 50 µA
A
VOH
II
ICC
∆ICC§
MIN
4.5 V
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.8
IOH = − 24 mA
5.5 V
4.94
4.8
IOH = − 75 mA‡
5.5 V
IOL = 50 µA
A
VOL
TA = 25°C
MIN
TYP
MAX
IOL = 24 mA
IOL = 75 mA‡
VI = VCC or GND
VI = VCC or GND,
One input at 3.4 V,
Other inputs at VCC or GND
•
V
4.5 V
0.1
5.5 V
0.1
0.1
4.5 V
0.36
0.44
5.5 V
0.36
0.44
0.1
V
1.65
5.5 V
± 0.1
±1
µA
5.5 V
8
80
µA
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5V
4.5
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
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•
UNIT
3.85
5.5 V
IO = 0
MAX
pF
3
SCAS185A − AUGUST 1990 − REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
tw
Clock frequency
0
Pulse duration
tsu
Setup time, before CLK↑
th
Hold time, after CLK↑
100
MIN
MAX
UNIT
0
100
MHz
CLK high or low
5
5
Data
5
5
CLKEN high or low
4.5
4.5
Data
0.5
0.5
1
1
CLKEN high or low
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
CLK
Any Q
MIN
TA = 25°C
TYP
MAX
MIN
MAX
100
130
100
2.8
5.9
6.8
2.8
9
3.7
7.3
9.2
3.7
10.7
UNIT
MHz
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
•
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f = 1 MHz
TYP
UNIT
31
pF
SCAS185A − AUGUST 1990 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
3V
Timing Input
(see Note B)
From Output
Under Test
1.5 V
0
th
tsu
CL = 50 pF
(see Note A)
500 Ω
3V
Data
Input
1.5 V
1.5 V
0
SETUP AND HOLD TIMES
LOAD CIRCUIT
3V
Input
(see Note B)
1.5 V
1.5 V
0
3V
High-Level
Input
1.5 V
tPLH
1.5 V
0
In-Phase
Output
tw
Low-Level
Input
tPHL
50% VCC
3V
1.5 V
tPLH
tPHL
1.5 V
0
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
PROPAGATION DELAY TIMES
PULSE DURATION
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. For testing
fmax and pulse duration: tr = 1 to 3 ns, tf = 1 to 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
•
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