TI CSD17381F4

CSD17381F4
www.ti.com
SLPS411A – APRIL 2013 – REVISED JULY 2013
30-V, N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD17381F4
PRODUCT SUMMARY
FEATURES
1
•
•
•
•
2
•
•
•
•
Ultra Low On Resistance
Ultra Low Qg and Qgd
Low Threshold Voltage
Ultra Small Footprint (0402 Case Size)
– 1.0 mm x 0.6 mm
Ultra Low Profile
– 0.35 mm Height
Integrated ESD Protection Diode
– Rated > 4kV HBM
– Rated > 2kV CDM
Pb and Halogen Free
RoHS Compliant
VDS
Drain to Source Voltage
Qg
Gate Charge Total (4.5V)
Qgd
Gate Charge Gate to Drain
RDS(on)
VGS(th)
•
•
pC
VGS = 1.8V
160
VGS = 2.5V
110
VGS = 4.5V
90
Threshold Voltage
mΩ
0.85
V
Qty
Media
CSD17381F4
3,000
7-Inch
Reel
CSD17381F4R
18,000
13-Inch
Reel
Package
Ship
Femto(0402) 1.0mm x
0.6mm SMD Lead Less
Tape and
Reel
Text Added For Spacing
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
DESCRIPTION
The FemtoFET™ MOSFET technology has been
designed and optimized to minimize the footprint in
many handheld and mobile applications. This
technology is capable of replacing standard small
signal MOSFETs while providing at least a 60%
reduction in footprint size.
On Resistance vs. Gate Voltage
VALUE
UNIT
VDS
Drain to Source Voltage
30
V
VGS
Gate to Source Voltage
12
V
ID
Continuous Drain Current, TA = 25°C(1)
3.1
A
IDM
Pulsed Drain Current, TA = 25°C(2)
10
A
PD
Power Dissipation(1)
500
mW
4
kV
2
kV
–55 to 150
°C
2.7
mJ
Human Body Model (HBM)
ESD
Rating Charged Device Model (CDM)
TJ,
TSTG
Operating Junction and Storage
Temperature Range
EAS
Avalanche Energy, single pulse ID = 7.4A,
L = 0.1mH, RG = 25Ω
(1) Typical RθJA = 90°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB.
(2) Pulse duration ≤300μs, duty cycle ≤2%
160
RDS(on) - On-State Resistance (mΩ)
133
Drain to Source On Resistance
Device
Optimized for Load Switch Applications
Optimized for General Purpose Switching
Applications
Single Cell Battery Applications
Handheld and Mobile Applications
Top View
TC = 25°C Id = 0.5A
TC = 125ºC Id = 0.5A
150
V
pC
Text Added For Spacing
ORDERING INFORMATION
APPLICATIONS
•
•
30
1040
140
D
130
120
110
100
90
80
70
60
G
0
2
4
6
8
10
VGS - Gate-to- Source Voltage (V)
S
12
G001
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FemtoFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD17381F4
SLPS411A – APRIL 2013 – REVISED JULY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, IDS = 250μA
IDSS
Drain to Source Leakage Current
VGS = 0V, VDS = 24V
IGSS
Gate to Source Leakage Current
VDS = 0V, VGS = 10V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, IDS = 250μA
RDS(on)
gfs
Drain to Source On Resistance
Transconductance
30
0.65
V
1
μA
100
nA
0.85
1.10
V
VGS = 1.8V, IDS =0.5A
160
250
mΩ
VGS = 2.5V, IDS =0.5A
110
143
mΩ
VGS = 4.5V, IDS = 0.5A
90
117
mΩ
VGS = 8V, IDS =0.5A
84
109
mΩ
VDS = 15V, IDS = 0.5A
4.8
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
150
195
pF
44
57
pF
Crss
RG
Reverse Transfer Capacitance
2.2
2.9
pF
Series Gate Resistance
23
Qg
Gate Charge Total (4.5V)
1350
pC
Qgd
Gate Charge Gate to Drain
Qgs
Gate Charge Gate to Source
Qg(th)
Gate Charge at Vth
Qoss
Output Charge
td(on)
tr
td(off)
Turn Off Delay Time
tf
Fall Time
VGS = 0V, VDS = 15V,
f = 1MHz
1040
Ω
133
pC
226
pC
150
pC
1110
pC
Turn On Delay Time
3.4
ns
Rise Time
1.4
ns
10.8
ns
3.6
ns
VDS = 15V, IDS = 0.5A
VDS = 15V, VGS = 0V
VDS = 0V, VGS = 4.5V,
IDS = 0.5A,RG = 2Ω
Diode Characteristics
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
ISD = 0.5A, VGS = 0V
VDS= 15V, IF = 0.5A, di/dt = 300A/μs
0.73
0.9
V
1500
pC
5.6
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
RθJA
(1)
(2)
2
Thermal Resistance Junction to Ambient
Typical Values
(1)
Thermal Resistance Junction to Ambient (2)
2
UNIT
90
°C/W
250
°C/W
2
Device mounted on FR4 material with 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu.
Device mounted on FR4 material with minimum Cu mounting area.
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Product Folder Links: CSD17381F4
CSD17381F4
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SLPS411A – APRIL 2013 – REVISED JULY 2013
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
5
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
8
7
6
5
4
3
2
VGS =8V
VGS =4.5V
1
0
0
0.1
VGS =2.5V
VGS =1.8V
0.2 0.3 0.4 0.5 0.6 0.7 0.8
VDS - Drain-to-Source Voltage (V)
0.9
1
VDS = 5V
4
3
2
TC = 125°C
TC = 25°C
TC = −55°C
1
0
0
G001
Figure 2. Saturation Characteristics
0.4
0.8
1.2
1.6
VGS - Gate-to-Source Voltage (V)
2
Product Folder Links: CSD17381F4
G001
Figure 3. Transfer Characteristics
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Copyright © 2013, Texas Instruments Incorporated
2.4
3
CSD17381F4
SLPS411A – APRIL 2013 – REVISED JULY 2013
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
ID = 0.5A
VDS =15V
9
8
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
100
10
2
1
0
0
0.2
0.4
0.6
0.8 1 1.2 1.4 1.6
Qg - Gate Charge (nC)
1.8
2
1
2.2
0
3
6
G001
Figure 4. Gate Charge
TEXT ADDED FOR SPACING
G001
TEXT ADDED FOR SPACING
RDS(on) - On-State Resistance (mΩ)
VGS(th) - Threshold Voltage (V)
30
160
ID = 250uA
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
−75
−25
25
75
125
TC - Case Temperature (ºC)
TC = 25°C Id = 0.5A
TC = 125ºC Id = 0.5A
150
140
130
120
110
100
90
80
70
60
175
0
2
G001
Figure 6. Threshold Voltage vs. Temperature
TEXT ADDED FOR SPACING
G001
TEXT ADDED FOR SPACING
ID =0.5A
1.3
1.2
1.1
1
0.9
0.8
0.7
−75
12
10
VGS = 1.8V
VGS = 8V
ISD − Source-to-Drain Current (A)
1.4
4
6
8
10
VGS - Gate-to- Source Voltage (V)
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
1.5
Normalized On-State Resistance
27
Figure 5. Capacitance
1.2
−25
25
75
125
TC - Case Temperature (ºC)
175
TC = 25°C
TC = 125°C
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
Figure 8. Normalized On-State Resistance vs. Temperature
4
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
1
G001
Figure 9. Typical Diode Forward Voltage
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: CSD17381F4
CSD17381F4
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SLPS411A – APRIL 2013 – REVISED JULY 2013
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
1ms
10ms
100ms
1s
DC
10
1
0.1
Single Pulse
Typical RthetaJA =250ºC/W(min Cu)
0.01
0.01
TC = 25ºC
TC = 125ºC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
100
0.1
1
10
VDS - Drain-to-Source Voltage (V)
10
1
0.1
0.001
50
0.01
0.1
TAV - Time in Avalanche (mS)
G001
Figure 10. Maximum Safe Operating Area
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
IDS - Drain- to- Source Current (A)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−50
Typical RthetaJA =90ºC/W(max Cu)
−25
0
25
50
75
100 125
TA - AmbientTemperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs. Temperature
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Product Folder Links: CSD17381F4
5
CSD17381F4
SLPS411A – APRIL 2013 – REVISED JULY 2013
www.ti.com
MECHANICAL DATA
0402 Mechanical Dimensions
(1)
All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994)
(2)
This drawing is subject to change without notice
(3)
This package is a PB-Free solder land design
Recommended Minimum PCB Layout
(1)
6
All dimensions are in millimeters.
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Product Folder Links: CSD17381F4
CSD17381F4
www.ti.com
SLPS411A – APRIL 2013 – REVISED JULY 2013
Recommended Stencil Pattern
(1)
All dimensions are in millimeters.
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: CSD17381F4
7
CSD17381F4
SLPS411A – APRIL 2013 – REVISED JULY 2013
www.ti.com
CSD17381F4 Embossed Carrier Tape Dimensions
(1)
Pin 1 will be oriented in the top right quadrant of the tape enclosure (Quadrant 2), closest to the carrier tape sprocket
holes.
spacer
REVISION HISTORY
Changes from Original (April 2013) to Revision A
Page
•
Added ESD info to Features ................................................................................................................................................. 1
•
Included Jumbo Real Ordering Information .......................................................................................................................... 1
•
Added ESD Rating Info to Absolute Maximum Table ........................................................................................................... 1
•
Added Circuit Schematic to PinOut View ............................................................................................................................. 1
8
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Product Folder Links: CSD17381F4
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CSD17381F4
Package Package Pins
Type Drawing
SPQ
PICOST
AR
3000
YJC
3
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
0.7
B0
(mm)
K0
(mm)
P1
(mm)
1.1
0.46
4.0
W
Pin1
(mm) Quadrant
8.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD17381F4
PICOSTAR
YJC
3
3000
210.0
185.0
35.0
Pack Materials-Page 2
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