CSD18531Q5A www.ti.com SLPS321B – JUNE 2012 – REVISED OCTOBER 2012 60V N-Channel NexFET™ Power MOSFETs Check for Samples: CSD18531Q5A FEATURES 1 • • • • • • • • 2 PRODUCT SUMMARY Ultra Low Qg and Qgd Low Thermal Resistance Avalanche Rated Logic Level Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package Typical Values at 25°C unless otherwise stated TYPICAL VALUE UNIT VDS Drain to Source Voltage 60 V Qg Gate Charge Total (4.5V) 18 nC Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance VGS(th) Threshold Voltage 5.9 nC VGS = 4.5V 4.4 mΩ VGS = 10V 3.5 mΩ 1.8 V ORDERING INFORMATION APPLICATIONS • • • DC-DC Conversion Secondary Side Synchronous Rectifier Battery Motor Control Figure 1. Top View Qty Ship CSD18531Q5A SON 5-mm × 6-mm Plastic Package 13-Inch Reel 2500 Tape and Reel 8 1 VALUE UNIT VDS Drain to Source Voltage 60 V VGS Gate to Source Voltage ±20 V Continuous Drain Current (Package limited), TC = 25°C 100 Continuous Drain Current (Silicon limited), TC = 25°C 134 ID Continuous Drain Current, TA = 25°C(1) 19 Pulsed Drain Current, TA = 25°C(2) 122 A 3.1 W S 2 7 D PD Power Dissipation(1) S 3 6 D TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C G 4 5 D EAS Avalanche Energy, single pulse ID = 67A, L = 0.1mH, RG = 25Ω 224 mJ (1) Typical RθJA = 40°C/W on a 1-inch2, 2-oz. Cu pad on a 0.06inch thick FR4 PCB. (2) Pulse duration ≤300μs, duty cycle ≤2% P0093-01 RDS(on) vs VGS 12 GATE CHARGE 10 10 VGS - Gate-to-Source Voltage (V) TC = 25°C Id = 22A TC = 125ºC Id = 22A 8 6 4 2 0 A IDM D D RDS(on) - On-State Resistance - mΩ Media ABSOLUTE MAXIMUM RATINGS The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications. 0 Package TA = 25°C unless otherwise stated DESCRIPTION S Device 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage - V 18 20 G001 ID = 22A VDS = 30V 8 6 4 2 0 0 5 10 15 20 25 Qg - Gate Charge - nC (nC) 30 33 G001 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated CSD18531Q5A SLPS321B – JUNE 2012 – REVISED OCTOBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250μA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 48V IGSS Gate to Source Leakage Current VDS = 0V, VGS = 20V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250μA RDS(on) Drain to Source On Resistance gfs Transconductance 60 1.5 V 1 μA 100 nA 1.8 2.3 V 4.4 5.8 mΩ VGS = 10V, ID = 22A 3.5 4.6 mΩ VDS = 30V, ID = 22A 128 VGS = 4.5V, ID = 22A S Dynamic Characteristics Ciss Input Capacitance 3200 3840 pF Coss Output Capacitance Crss Reverse Transfer Capacitance 380 456 pF 11 14 RG pF Series Gate Resistance 1.2 2.4 Ω Qg Gate Charge Total (4.5V) 18 22 Qg Gate Charge Total (10V) 36 43 Qgd Gate Charge Gate to Drain Qgs Qg(th) Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 30V, f = 1MHz VDS = 30V, ID = 22A nC 5.9 nC Gate Charge Gate to Source 6.9 nC Gate Charge at Vth 5.2 nC 32 nC 4.4 ns 7.8 ns 20 ns 2.7 ns VDS = 30V, VGS = 0V VDS = 30V, VGS = 10V, IDS = 22A, RG = 0Ω Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = 22A, VGS = 0V 0.8 VDS= 30V, IF = 22A, di/dt = 300A/μs 100 1 nC V 40 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER RθJC Thermal Resistance Junction to Case (1) RθJA Thermal Resistance Junction to Ambient (1) (2) (1) (2) 2 MIN TYP MAX UNIT 1 °C/W 50 °C/W RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: CSD18531Q5A CSD18531Q5A www.ti.com SLPS321B – JUNE 2012 – REVISED OCTOBER 2012 GATE GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2oz. (0.071-mm thick) Cu. Source Max RθJA = 121°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) Figure 2. Transient Thermal Impedance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 140 VDS = 5V 180 IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A 200 160 140 120 100 80 60 VGS =10V VGS =6.5V VGS =4.5V 40 20 0 0 0.5 1 VDS - Drain-to-Source Voltage - V 1.5 120 100 80 60 40 TC = 125°C TC = 25°C TC = −55°C 20 0 0 G001 Figure 3. Saturation Characteristics 1 2 3 4 VGS - Gate-to-Source Voltage - V Product Folder Links: CSD18531Q5A G001 Figure 4. Transfer Characteristics Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated 5 3 CSD18531Q5A SLPS321B – JUNE 2012 – REVISED OCTOBER 2012 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 50000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd ID = 22A VDS = 30V 10000 8 C − Capacitance − pF VGS - Gate-to-Source Voltage (V) 10 6 4 1000 100 2 0 0 5 10 15 20 25 Qg - Gate Charge - nC (nC) 30 10 33 0 10 20 30 40 50 VDS - Drain-to-Source Voltage - V G001 Figure 5. Gate Charge TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 12 RDS(on) - On-State Resistance - mΩ VGS(th) - Threshold Voltage - V ID = 250uA 2.3 2 1.7 1.4 1.1 0.8 0.5 −75 −25 25 75 125 TC - Case Temperature - ºC TC = 25°C Id = 22A TC = 125ºC Id = 22A 10 8 6 4 2 0 175 0 2 G001 Figure 7. Threshold Voltage vs. Temperature TEXT ADDED FOR SPACING 18 20 G001 TEXT ADDED FOR SPACING VGS = 4.5V VGS = 10V ID =22A 1.8 1.5 1.2 0.9 0.6 0.3 −75 6 8 10 12 14 16 VGS - Gate-to- Source Voltage - V 100 ISD − Source-to-Drain Current - A 2.1 4 Figure 8. On-State Resistance vs. Gate-to-Source Voltage 2.4 Normalized On-State Resistance G001 Figure 6. Capacitance 2.5 −25 25 75 125 TC - Case Temperature - ºC 175 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage - V G001 Figure 9. Normalized On-State Resistance vs. Temperature 4 60 1 G001 Figure 10. Typical Diode Forward Voltage Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: CSD18531Q5A CSD18531Q5A www.ti.com SLPS321B – JUNE 2012 – REVISED OCTOBER 2012 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 1ms 10ms 100ms 1s DC 100 10 1 0.1 Single Pulse Typical RthetaJA =97ºC/W(min Cu) 0.01 0.01 TC = 25ºC TC = 125ºC − IAV - Peak Avalanche Current- A IDS - Drain-to-Source Current - A 2000 1000 0.1 1 10 VDS - Drain-to-Source Voltage - V 100 10 0.01 0.1 TAV - Time in Avalanche - mS G001 Figure 11. Maximum Safe Operating Area 1 G001 Figure 12. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING − IDS - Drain- to- Source Current - A 120 100 80 60 40 20 0 −50 −25 0 25 50 75 100 125 TC - Case Temperature - ºC 150 175 G001 Figure 13. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: CSD18531Q5A 5 CSD18531Q5A SLPS321B – JUNE 2012 – REVISED OCTOBER 2012 www.ti.com MECHANICAL DATA Q5A Package Dimensions L E2 H K 7 D2 3 4 b 4 5 5 6 3 6 e D1 7 2 2 8 8 1 1 q L1 Top View Bottom View Side View c A q E1 E Front View M0135-01 DIM 6 MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 e 1.17 1.27 1.37 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 θ 0° Submit Documentation Feedback 12° Copyright © 2012, Texas Instruments Incorporated Product Folder Links: CSD18531Q5A CSD18531Q5A www.ti.com SLPS321B – JUNE 2012 – REVISED OCTOBER 2012 Figure 14. Recommended PCB Pattern DIM F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 F8 F4 F10 M0139-01 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: CSD18531Q5A 7 CSD18531Q5A SLPS321B – JUNE 2012 – REVISED OCTOBER 2012 www.ti.com REVISION HISTORY Changes from Original (June 2012) to Revision A • Page Added "Typical Values at 25°C unless otherwise stated" to the Product Summary table .................................................... 1 Changes from Revision A (June 2012) to Revision B Page • Changed the Transconductance TYP value From: 177 S To: 128 S. .................................................................................. 2 • Changed the Turn On and Turn Off Delay Time, Rise and Fall Time Test Conditions From: IDS = 22A, RG = 2Ω To: IDS = 22A, RG = 0Ω ............................................................................................................................................................... 2 • Changed the Qrr Reverse Recovery Charge TYP value From: 68 nC To: 100 nC .............................................................. 2 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: CSD18531Q5A PACKAGE OPTION ADDENDUM www.ti.com 15-Aug-2012 PACKAGING INFORMATION Orderable Device CSD18531Q5A Status (1) ACTIVE Package Type Package Drawing SON DQJ Pins Package Qty 8 2500 Eco Plan (2) Pb-Free (RoHS Exempt) Lead/ Ball Finish CU SN MSL Peak Temp (3) Samples (Requires Login) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD18531Q5A Package Package Pins Type Drawing SON DQJ 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.3 B0 (mm) K0 (mm) P1 (mm) 5.3 1.2 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD18531Q5A SON DQJ 8 2500 340.0 340.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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