INTEGRATED CIRCUITS 74LVC374A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) Product specification 1998 Jul 29 Philips Semiconductors Product specification Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) 74LVC374A Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. FEATURES • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Supply voltage range of 2.7V to 3.6V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • Direct interface with TTL levels • High impedance when VCC = 0V • 8-bit positive edge-triggered register • Independent register and 3-State buffer operation The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus-oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. DESCRIPTION The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The ’374’ is functionally identical to the ’574’, but the ’574’ has a different pin arrangement. QUICK REFERENCE DATA GND = 0V; Tamb =25°C; tr = tf 2.5ns PARAMETER SYMBOL CONDITIONS CL = 50pF VCC = 3.3V TYPICAL UNIT tPHL/tPLH Propagation delay CP to Qn fmax maximum clock frequency 150 MHz CI Input capacitance 5.0 pF CPD Power dissipation capacitance per flip-flop 20 pF 4.8 Notes 1 and 2 ns NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C 74LVC374A D 74LVC374A D SOT163-1 20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C 74LVC374A DB 74LVC374A DB SOT339-1 20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C 74LVC374A PW 7LVC374APW DH SOT360-1 PACKAGES 1998 Jul 29 2 853-1861 19802 Philips Semiconductors Product specification Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) PIN CONFIGURATION 74LVC374A LOGIC SYMBOL (IEEE/IEC) 11 1 C1 OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 3 D1 4 17 D6 4 5 Q1 5 16 Q6 7 6 Q2 6 15 Q5 8 D2 7 14 D5 13 12 D3 8 13 D4 14 15 Q3 9 12 Q4 17 16 11 CP 18 19 GND 10 EN1 9 SA00389 SA00391 FUNCTIONAL DIAGRAM PIN DESCRIPTION PIN NUMBER SYMBOL 1 OE 3, 4, 7, 8, 13, 14, 17, 18 2, 5, 6, 9, 12, 15, 16, 19 2 1D FUNCTION Output enable input (active-Low) 3 D0 Q0 2 D0-D7 Data inputs 4 D1 Q1 5 7 D2 Q2 6 Q0-Q7 3-state flip-flop outputs 8 D3 Q3 9 Q4 12 Clock input (LOW-to-HIGH, edge-triggered) 11 CP 10 GND 20 VCC Ground (0V) Positive supply voltage LOGIC SYMBOL FF1 to FF8 3-State OUTPUTS 13 D4 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 11 CP 1 OE 11 SA00392 3 D0 CP Q0 2 5 4 D1 Q1 7 D2 Q2 6 8 D3 Q3 9 13 D4 Q4 12 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 OE 1 SA00390 1998 Jul 29 3 Philips Semiconductors Product specification Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) 74LVC374A LOGIC DIAGRAM D0 D1 D D2 D Q CP D Q CP FF1 D3 D Q CP FF2 D4 D Q CP FF3 D5 D Q CP FF4 D6 D Q CP FF5 D7 D Q CP FF6 Q CP FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SA00393 FUNCTION TABLE INPUTS OPERATING MODES H h L l Z ° OUTPUTS INTERNAL FLIP-FLOPS OE LE Dn Load and read register L L ° ° l h L H L H Load register and disable outputs H H ° ° l h L H Z Z = HIGH voltage level = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition = High impedance OFF-state = LOW-to-HIGH clock transition 1998 Jul 29 4 Q0 to Q7 Philips Semiconductors Product specification Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) 74LVC374A RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VI VO PARAMETER CONDITIONS UNIT MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 DC input voltage range 0 5.5 DC output voltage range; output HIGH or LOW state 0 VCC DC output voltage range; output 3-State 0 5.5 –40 +85 °C 0 0 20 10 ns/V V Tamb Operating ambient temperature range in free-air tr, tf Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V V V ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) PARAMETER SYMBOL VCC CONDITIONS UNIT –0.5 to +6.5 V IIK DC input diode current VI t0 –50 mA VI DC input voltage Note 2 –0.5 to +6.5 V IOK DC output diode current VO uVCC or VO t 0 "50 mA DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5 DC output voltage; output 3-State Note 2 –0.5 to 6.5 DC output source or sink current VO = 0 to VCC VO IO IGND, ICC Tstg PTOT DC supply voltage RATING DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K V "50 mA "100 mA –65 to +150 °C 500 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jul 29 5 Philips Semiconductors Product specification Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) 74LVC374A DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 TYP1 V VCC = 1.2V GND V VCC = 2.7 to 3.6V HIGH level output voltage 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –18mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*0.8 VCC V VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage UNIT MAX 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND 0.20 VCC = 3.0V; VI = VIH or VIL; IO = 24mA V 0.55 "0 1 "0.1 "5 µA IOZ 3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND 0.1 "10 µA Ioff Power off leakage supply VCC = 0.0V; VI or VO = 5.5V 0.1 "10 µA ICC Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA II ∆ICC Input leakage current2 VCC = 3 3.6V; 6V; VI = 5 5.5V 5V or GND NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state. AC CHARACTERISTICS GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL tPHL tPLH tPZH tPZL tPHZ tPLZ tW tSU th fmax PARAMETER Propagation delay CP to Qn 3-State output enable time OE to Qn 3-State output disable time OE to Qn Clock pulse width HIGH or LOW Setup time Dn to CP Hold time Dn to CP maximum clock pulse frequency WAVEFORM VCC = 3.3V ±0.3V VCC = 1.2V UNIT TYP1 MAX MIN MAX TYP 1, 4 1.5 4.8 7.0 1.5 8.0 21 ns 2, 4 1.5 4.8 7.5 1.5 8.5 22 ns 2, 4 1.5 4.3 6.0 1.5 7.0 15 ns 1 3.0 1.5 – 3.0 – – ns 3 2.0 0 – 2.0 – – ns 3 1.5 0.6 – 1.5 – – ns 1 100 – – 80 – – MHz NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C. 1998 Jul 29 VCC = 2.7V MIN 6 Philips Semiconductors Product specification Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) 74LVC374A AC WAVEFORMS VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V VI VM nOE INPUT GND 1/fmax tPLZ VI VM CP INPUT VM Qn OUTPUT LOW-to-OFF OFF-to-LOW GND tw tPHL VM VM VX tPLH VOH Qn OUTPUT tPZL VCC VM VOL VM tPHZ VOL tPZH VOH Qn OUTPUT HIGH-to-OFF OFF-to-HIGH SA00394 Waveform 1. Clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. VY VM GND outputs enabled outputs enabled outputs disabled SW00207 VI CP INPUT Waveform 3. 3-State enable and disable times. VM TEST CIRCUIT GND tsu tsu S1 VCC ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ th th VI Dn INPUT VM PULSE GENERATOR VI 2 x VCC Open GND 500Ω VO D.U.T. GND RT 50pF CL 500Ω VOH Qn OUTPUT VM Test VOL NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SW00107 Waveform 2. Data setup and hold times for the Dn input to the CP input. S1 VCC VI tPLH/tPHL Open t 2.7V VCC tPLZ/tPZL 2 x VCC 2.7V – 3.6V 2.7V tPHZ/tPZH GND SY00003 Waveform 4. Load circuitry for switching times. 1998 Jul 29 7 Philips Semiconductors Product specification Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) SO20: plastic small outline package; 20 leads; body width 7.5 mm 1998 Jul 29 8 74LVC374A SOT163-1 Philips Semiconductors Product specification Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1998 Jul 29 9 74LVC374A SOT339-1 Philips Semiconductors Product specification Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1998 Jul 29 10 74LVC374A SOT360-1 Philips Semiconductors Product specification Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) NOTES 1998 Jul 29 11 74LVC374A Philips Semiconductors Product specification Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State) 74LVC374A Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 08-98 9397-750-04507