INTEGRATED CIRCUITS 74LVC16374A/74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) Product specification Supersedes data of 1997 Aug 22 IC24 Data Handbook 1998 Mar 17 Philips Semiconductors Product specification 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) FEATURES 74LVC16374A/ 74LVCH16374A PIN CONFIGURATION • 5 volt tolerant inputs/outputs for interfacing with 5V logic • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple power and ground pins for minimum 1OE 1 48 1CP 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 noise and ground bounce • Direct interface with TTL levels • All data inputs have bus hold (74LVCH16374A only) • High impedance when VCC = 0 GND 10 39 GND 1Q6 11 38 1D6 DESCRIPTION 1Q7 12 37 1D7 The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. The 74LVC16374A consists of 2 sections of eight positive edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment. 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2CP The 74LVCH16374A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs. SW00074 QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT 3.8 ns tPHL/tPLH Propagation delay Cp to Qn CL = 50pF VCC = 3.3V fMAX Maximum clock frequency 150 MHz CI Input capacitance 5.0 pF CPD Power dissipation capacitance per flip-flop 30 pF VCC = 3.3V1 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 48-Pin Plastic SSOP Type III –40°C to +85°C 74LVC16374A DL VC16374A DL SOT370-1 48-Pin Plastic TSSOP Type II –40°C to +85°C 74LVC16374A DGG VC16374A DGG SOT362-1 48-Pin Plastic SSOP Type III –40°C to +85°C 74LVCH16374A DL VCH16374A DL SOT370-1 48-Pin Plastic TSSOP Type II –40°C to +85°C 74LVCH16374A DGG VCH16374A DGG SOT362-1 1998 Mar 17 2 853-2028 19111 Philips Semiconductors Product specification 74LVC16374A/ 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) PIN DESCRIPTION PIN NUMBER 1 SYMBOL 1OE 2, 3, 5, 6, 8, 9, 11, 12 4, 10, 15, 21, 28, 34, 39, 45 1Q0 to 1Q7 GND 7, 18, 31, 42 13, 14, 16, 17, 19, 20, 22, 23 24 VCC 2Q0 to 2Q7 2OE 25 2CP 36, 35, 33, 32, 30, 29, 27, 26 47, 46, 44, 43, 41, 40, 38, 37 48 LOGIC SYMBOL 2D0 to 2D7 1D0 to 1D7 1CP NAME AND FUNCTION 1 24 1OE 2OE Output enable input (active LOW) 47 1D0 1Q0 2 46 1D1 1Q1 3 44 1D2 1Q2 5 43 1D3 1Q3 6 41 1D4 1Q4 8 40 1D5 1Q5 9 38 1D6 1Q6 11 37 1D7 1Q7 12 Output enable input (active LOW) 36 2D0 2Q0 13 35 2D1 2Q1 14 Clock input 33 2D2 2Q2 16 32 2D3 2Q3 17 30 2D4 2Q4 19 29 2D5 2Q5 20 27 2D6 2Q6 22 26 2D7 2Q7 23 3-State flip-flop outputs Ground (0V) Positive supply voltage 3-State flip-flop outputs Data inputs Data inputs Clock input 1CP 2CP 48 25 SW00075 LOGIC DIAGRAM D 1D0 Q 1Q0 2D0 CP D Q 2Q0 CP FF1 FF9 1CP 2CP 1OE 2OE TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS SW00076 FUNCTION TABLE INPUTS OPERATING MODES INTERNAL FLIP-FLOPS OUTPUTS nOE nCP nDx Load and read register L L l h L H L H Load register and disable outputs H H l h L H Z Z H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition Z = high impedance OFF-state = LOW-to-HIGH CP transition 1998 Mar 17 3 Q0 to Q7 Philips Semiconductors Product specification 74LVC16374A/ 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) LOGIC SYMBOL (IEEE/IEC) 1OE 1CLK 1 48 2OE 24 2CLK 25 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 47 BUS HOLD CIRCUIT VCC 1EN C1 2EN C2 2 1Q0 46 3 1Q1 44 5 1Q2 43 6 1Q3 41 8 1Q4 40 9 38 11 1Q6 37 12 1Q7 13 2Q0 35 14 2Q1 33 16 2Q2 32 17 2Q3 30 19 2Q4 29 20 2Q5 27 22 2Q6 26 23 36 1∇ 1D 2∇ 2D Data Input To internal circuit 1Q5 SW00044 2Q7 SW00077 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf 1998 Mar 17 PARAMETER CONDITIONS LIMITS UNIT MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 DC input voltage range 0 5.5 DC input voltage range; output HIGH or LOW state 0 VCC DC output voltage range; output 3-State 0 5.5 –40 +85 °C 0 0 20 10 ns/V Operating free-air temperature range VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V Input rise and fall times 4 V V V Philips Semiconductors Product specification 74LVC16374A/ 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC PARAMETER CONDITIONS RATING –0.5 to +6.5 V IIK DC input diode current VI t 0 –50 mA VI DC input voltage Note 2 –0.5 to +6.5 V IOK DC output diode current VO uVCC or VO t 0 "50 mA DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5 DC output voltage; output 3-State Note 2 –0.5 to 6.5 DC output source or sink current VO = 0 to VCC VO IO IGND, ICC Tstg PTOT DC supply voltage UNIT Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) "50 mA "100 mA –65 to +150 °C 500 500 mW DC VCC or GND current Storage temperature range V above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage VIL LOW level Input voltage VOH O VOL VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 GND V VCC = 2.7 to 3.6V HIGH level output voltage LOW level output voltage 0.8 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5 0V; VI = VIH or VIL; IO = –100µA 100µA VCC = 3 3.0V; 02 VCC*0.2 VCC = 3.0V; VI = VIH or VIL; IO = –18mA VCC*0.6 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC*0.8 V 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100µA 0.20 VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.55 IOZ 3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND Ioff Power off leakage supply VCC = 0.0V; VI or VO = 5.5V ICC Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 1998 Mar 17 VCC VCC = 2.7V; VI = VIH or VIL; IO = 12mA VCC = 3.6V; VI = 5.5V or GND6 ∆ICC MAX V VCC = 1.2V Input leakage current II TYP1 UNIT 5 V "0.1 "5 µA 0.1 "5 µA "10 µA 0.1 20 µA 5 500 µA Philips Semiconductors Product specification 74LVC16374A/ 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) DC ELECTRICAL CHARACTERISTICS (Continued) Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN TYP1 UNIT MAX IBHL Bus hold LOW sustaining current VCC = 3.0V; VI = 0.8V2, 3, 4 75 µA IBHH Bus hold HIGH sustaining current VCC = 3.0V; VI = 2.0V2, 3, 4 IBHLO IBHHO Bus hold LOW overdrive current Bus hold HIGH overdrive current –75 µA VCC = 3.6V2, 3, 5 500 µA VCC = 3.6V2, 3, 5 –500 µA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. Valid for data inputs of bus hold parts (LVCH16-A) only. 3. For data inputs only, control inputs do not have a bus hold circuit. 4. The specified sustaining current at the data input holds the input below the specified VI level. 5. The specified overdrive current at the data input forces the data input to the opposite logic input state. 6. For bus hold parts, the bus hold circuit is switched off when Vi exceeds VCC allowing 5.5V on the input terminal. AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM VCC = 2.7V VCC = 1.2V MIN TYP1 MAX MIN MAX MAX UNIT tPHL tPLH Propagation delay CP to Qn 1, 4 1.5 3.8 5.4 1.5 6.4 17 ns tPZH tPZL 3-State output enable time OE to Qn 2, 4 1.5 3.6 5.6 1.5 6.6 20 ns tPHZ tPLZ 3-State output disable time OE to Qn 2, 4 1.5 3.9 5.5 1.5 6.5 12 ns tW CP pulse width HIGH or LOW 1 3.0 1.5 – 3.0 – – ns tsu Set-up time Dn to CP 3 2.0 0.3 – 1.9 – – ns th Hold time Dn to CP 3 1.5 –0.3 – 1.1 – – ns Maximum clock pulse frequency 1 100 – – 80 – – MHz fmax NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 1998 Mar 17 6 Philips Semiconductors Product specification 74LVC16374A/ 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) AC WAVEFORMS VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V VI 1/fMAX CP INPUT VI CP INPUT VM GND VM tsu tsu GND tw tPHL VOH Qn OUTPUT ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ th th tPLH VI Dn INPUT VM VM GND VOL SW00078 VOH Qn OUTPUT Waveform 1. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency VM VOL NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VI OE INPUT VM SW00079 VM Waveform 3. Data set-up and hold times for the Dn input to the CP input GND tPLZ TEST CIRCUIT tPZL VCC S1 VCC OUTPUT LOW-to-OFF OFF-to-LOW 2<VCC Open GND VM VX RL=500 Ω VOL VOUT VIN tPHZ PULSE GENERATOR tPZH D.U.T. VOH RT VY OUTPUT HIGH-to-OFF OFF-to-HIGH RL=500 Ω CL VM GND outputs enabled outputs disabled Test Circuit for 3-State Outputs outputs enabled SWITCH POSITION SWITCH VCC VIN tPLH/tPHL Open tPLZ/tPZL 2<VCC t 2.7V 2.7 – 3.6V VCC 2.7V tPHZ/tPZH GND TEST SW00072 Waveform 2. 3-State enable and disable times DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. SW00047 Waveform 4. Load circuitry for switching times 1998 Mar 17 7 Philips Semiconductors Product specification 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm 1998 Mar 17 8 74LVC16374A/ 74LVCH16374A SOT370-1 Philips Semiconductors Product specification 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm 1998 Mar 17 9 74LVC16374A/ 74LVCH16374A SOT362-1 Philips Semiconductors Product specification 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) 74LVC16374A/ 74LVCH16374A DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 10 Date of release: 05-96 9397-750-04534