MB85RDP16LX

FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00031-1v1-J
FRAM
Data-Processing FRAM
16 K (2 K 8)
Dual SPI
MB85RDP16LX

MB85RDP16LX 2,048
8
FRAM
43
46
CMOS
FRAM (Ferroelectric Random Access Memory
)
SRAM
13
10
/
MB85RDP16LX Serial Peripheral interface (SPI)
Dual SPI
FRAM
,
,
46
43

•
: 2,048
×8
•
(for POS0/1/2/3)
: 43
(42
+
)
•
(for DIBC/DDBC)
: 46
(45
+
)
•
:
•
: SPI (Serial Peripheral Interface) / Dual SPI
SPI
0 (0, 0)
3 (1, 1)
: 15 MHz (Max for SPI) / 7.5 MHz (Max for Dual SPI)
: 1013 /
: 10 (+105 ℃)
: 1.65 V 1.95 V
:
0.7 mA (Max @15 MHz)
11
μA (Max @+105℃), 1 μA (+25℃)
: 40℃
+105℃
:
SON, 8
(LCC-8P-M04)
RoHS
•
•
•
•
•
•
•
Copyright 2014-2015 FUJITSU SEMICONDUCTOR LIMITED
2015.6
MB85RDP16LX

(TOP VIEW)
__
CS
SO
(IO1)
__
WP
VSS
1
8
2
7
VDD
___
RST
3
6
SCK
4
5
SI
(IO0)
(LCC-8P-M04)

CS‘‘H’’ , (
1
CS
3
WP
7
RST
6
SCK
), SO SI
CS‘‘L’’
High-Z ,
CS
, (),
WPWPEN(
)
■
,,
RST‘‘L’’ ,
RST‘‘L’’
, ,
SCK
, SCK
(
5
■
SI (IO0) , ,
0)
FRAM
High-Z
(
2
1)
SO (IO1) FRAM,
Hi
(
2
8
VDD
4
VSS
) Dual SPI SI
gh-Z
SO
IO0
IO1
DS501-00031-1v1-J
MB85RDP16LX

DS501-00031-1v1-J
3
MB85RDP16LX
 SPI
MB85RDP16LX
SPI
0 (CPOL
0, CPHA
0)
SPI
3 (CPOL
1, CPHA
1)
CS
SCK
SI
7
6
5
MSB
4
3
2
1
0
LSB
SPI Mode 0
CS
SCK
SI
7
6
5
4
3
2
1
0
MSB
LSB
SPI Mode 3

(SPI)
Standard SPI
MB85RDP16LX
SI
SCK
SO
SPI
Standard SPI SCK
Dual SPI
MB85RDP16LX “Read Dual I/O (RDIO, B3h)”
Dual SPI
Dual SPI
IO1
4
“Write Dual I/O (WDIO, B2h)”
SI
SO
IO0
DS501-00031-1v1-J
MB85RDP16LX

WP
(FRAM)WPEN
7
6 4
3
WPEN
⎯
WRSR
RDSR
BP1
WRITE
(
)WRSR
2
WDIO
■
RDSR
BP0
FRAM
WREN WRDI
WRSR
1
■)
(
WRSRRDSR
RDSR
WEL
WEL
WRDI
WRSR
WRITE
WDIO
0
DS501-00031-1v1-J
0
CS
CS
CS
“0”
5
MB85RDP16LX

MB85RDP16LX
WRTSd
WREN
RDID
7
RDIO
12
8
CS
WREN
0000 0110B
WRDI
0000 0100B
RDSR
0000 0101B
WRSR
0000 0001B
READ
0000 0011B
WRITE
0000 0010B
RDID
ID
1001 1111B
RDIO
I/O
1011 0011B
WDIO
I/O
1011 0010B
POS0
SPI_DIR&SPI_PP = 00
0011 0000B
POS1
SPI_DIR&SPI_PP = 01
0011 0001B
POS2
SPI_DIR&SPI_PP = 10
0011 0010B
POS3
SPI_DIR&SPI_PP = 11
0011 0011B
DIBC
(+1)
0011 1100B
DDBC
(-1)
0011 1110B
RDTSs
RDTSd
WRTSs
WRTSd
0x000
SO
0x000
IO
0x000
SI
0x000
IO
0011 1000B
0111 1000B
0011 1111B
0111 1111B
()
1-1. Standard SPI
(2 )
SI= X, X, X, X, X, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0
(
5
=
)
1-2. Dual SPI
(2 )
IO0 = X, X, A9, A7, A5, A3, A1, X
IO1 = X, X, A10, A8, A6, A4, A2, A0
(
4
1
=)
2-1. Standard SPI
SI (or SO) = (D7, D6, D5, D4, D3, D2, D1, D0)
2-2. Dual SPI
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
6
DS501-00031-1v1-J
MB85RDP16LX

• WREN
WREN WEL (
WRITE
)
WDIO )
(WRSR
WREN
WEL
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
0
0
0
0
0
1
1
Invalid
0
High-Z
SO
• WRDI
WRDI WEL (
(WRITE WRSR
)
WEL
WDIO)
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
0
0
0
0
0
1
0
0
Invalid
High-Z
SO
DS501-00031-1v1-J
7
MB85RDP16LX
• RDSR
RDSR
SCK 8 SI
SI
RDSR
SO SCK
CSSCK
RDSR
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
Invalid
1
Data Out
High-Z
SO
Invalid
MSB
LSB
• WRSR
WRSRSI
WRSR
WRSR 1
8
WEL ( )
SI
0
WRSR
“0” 0
WP
SI
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Instruction
SI
0
0
0
0
0
Data In
0
0
1
7
MSB
High-Z
6
5
4
3
2
1
0
LSB
SO
8
DS501-00031-1v1-J
MB85RDP16LX
• READ
READ FRAM
16 5
SO
SI READ
SCK8
SCKSI
CSREAD
CSSCK
8
0
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
16-bit address
OP-CODE
SI
0 0
0 0 0 0 1 1 X X X X X 10
5
4
3
2
1
0
Invalid
Data Out
LSB MSB
MSB
LSB
High-Z
SO
7
6
5
4
3
2
1
0
Invalid
• WRITE
WRITE FRAM
16
8
8
SI
WRITE
5
CS
FRAM
CS8
WRITE
0
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
OP-CODE
SI
0 0
16-bit address
0 0 0 0 1 0 X X X X X 10
MSB
SO
DS501-00031-1v1-J
5
4
Data In
3
2
1
0
7
6
LSB MSB
5
4
3
2
1
0
LSB
High-Z
9
MB85RDP16LX
• RDID
RDID ID
SI RDID
32 SISO
ManufacturerID (8bit) / Continuation code (
(2nd Byte) RDID
32
ID
SCK
SCK
8bit) / Product ID (1st Byte) / Product ID
SO
CS
CS
0
1
2
3
4
5
6
7
1
0
0
1
1
1
1
1
8
31 32 33 34 35 36 37 38 39
9 10 11
SCK
SI
Invalid
Data Out
SO
High-Z
Data Out
8
31 30 29 28
7
6
5
4
3
2
1
0
LSB
MSB
bit
Manufacturer ID
Continuation code
Product ID (1st Byte)
Product ID (2nd Byte)
10
7
0
0
6
0
1
5
0
1
Proprietary use
0
0
1
0
1
0
4
0
1
3
0
1
0
0
2
1
1
1
0
1
0
0
1
Hex
04H Fujitsu
7FH
Density
0
0
1
Hex
21H Density: 00001B = 16kbit
1
Hex
45H
Proprietary use
0
0
1
0
DS501-00031-1v1-J
MB85RDP16LX
• RDIO
RDIO FRAM
SI(IO0)
6
(A9, A7, A5, A3, A1)
SCK
4
SI(IO0)
4
CS
RDIO
(A10, A8, A6, A4, A2, A0)
SI(IO0)
SO(IO1) 5
5
SO(IO1)
4
(D6, D4, D2, D0)
SCK
(D7, D5, D3, D1)
CS
RDIO
SCK
4
0
CS
0
1
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
IO switches from Input to Output
16-bit address
OP-CODE
SI
1
0
1 1
0 0
1 1
X X 9
7
5
Data Out
3 1
X 6
4
2
(IO0)
SO
(IO1)
High-Z
X
X 10 8
6 4
2
0 6
4
2
0
5
3
1
LSB
LSB
0 7
5
3
1 7
MSB
MSB
Byte1
Invalid
Byte2
• WDIO
WDIO FRAM
SI(IO0)
6 (A10, A8, A6, A4, A2, A0)
(A9, A7, A5, A3, A1)
SI(IO0)
(D7, D5, D3, D1)
SO(IO1) 4
SI(IO0)
WDIO
SO(IO1)5
54
(D6, D4, D2, D0)
CS
FRAM
CS
WDIO
8
0
CS
0
1
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
16-bit address
OP-CODE
SI
(IO0)
SO
(IO1)
1
0
1 1
0 0
1 0
X X 9
7
5
Data In
3 1
X 6
4
2
High-Z
X
MSB
X 10 8
6 4
2
0 7
4
2
0
Invalid
5
3
1 7
5
3
1
Invalid
MSB
Byte1
DS501-00031-1v1-J
0 6
LSB
LSB
Byte2
11
MB85RDP16LX
• POS0/POS1/POS2/POS3
POS0, POS1, POS2, POS3 FRAM
2
43
8
f
6
”
(“2.
DCK
)
6
“000
” (“
for POS0/1/2/3”
48
H
43
)
FRAM
“000
48 FRAM
”
H
48 /
(RDTSs / RDTSd / WRTSs / WRTSd) 2
2
DIR
2
SO(IO1)
6
2
SO(IO1)
(Error Flags == 2’b00 and DIR == DIR’)
CS
Dummy Clocks
0
1
2
3 4
5
6
7
1
2
3
4
5
6
0
0
0
4
5
6
1
1
1
SCK
OP-CODE
SI
0 0
(IO0)
SO
(IO1)
1 1
0 0 DIR PP
Invalid
Signal Processing
0
0
High-Z
0
1
High-Z
(Error Flags != 2’b00 or DIR != DIR’)
CS
Dummy Clocks
0
1
2
3 4
5
6
7
1
2
3
SCK
OP-CODE
SI
(IO0)
SO
(IO1)
0 0
1 1
High-Z
old (DIR, PP)
0, 1
1, 1
1, 0
1, 1
1, 0
0, 0
0, 1
0, 0
others
12
0 0 DIR PP
new (DIR, PP)
0, 0
0, 0
0, 0
0, 1
1, 1
1, 1
1, 1
1, 0
others
Invalid
Signal Processing
0
0
1
1
High-Z
Binary counter operation
+1
+1
+1
+1
-1
-1
-1
-1
0
DS501-00031-1v1-J
MB85RDP16LX
• DIBC/DDBC
DIBC
46
1
8
fDCK (“2.
6
DDBC
6
”
1
)
“000
” (“
for DIBC/DDBC”
FRAM
H”
H
) 48
46
“000
48 FRAM
48 /
(RDTSs / RDTSd / WRTSs / WRTSd) 2
2
SO(IO1)
6
2
SO(IO1)
(Error Flags == 2’b00)
CS
Dummy Clocks
0
1
2
3 4
5
6
7
1
2
3
4
5
6
0
0
0
4
5
6
1
1
1
SCK
OP-CODE
SI
0 0
(IO0)
SO
(IO1)
1 1
1 1 0/1 0
Invalid
Signal Processing
0
0
High-Z
0
1
High-Z
1
High-Z
(Error Flags != 2’b00)
CS
Dummy Clocks
0
1
2
3 4
5
6
7
1
2
3
SCK
OP-CODE
SI
0 0
(IO0)
SO
(IO1)
1 1
1 1 0/1 0
High-Z
Name
DIBC
DDBC
Invalid
Signal Processing
0
0
OP-CODE (8-bit)
0011 1100B
0011 1110B
DS501-00031-1v1-J
1
Binary counter operation
+1
-1
13
MB85RDP16LX
• RDTSs (Single SO)
RDTSs FRAM
) SI
SCK
(
RDTSs
8
8
SO “000
SCK
RDTSs
CS
SI
SCK
H
”8
CS
8
0
RDTSs
READ
CS
0
1
0
0
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
OP-CODE
SI
1 1
1 0
0 0
Invalid
Data Out
High-Z
SO
7
6
5 4
3
2 1
0 15 14 13 12 11 10 9
LSB MSB
MSB
8
LSB
Invalid
Byte1
Byte0
• RDTSd (Dual IO)
RDTSd FRAM
) SI(IO0)
SCK
(D7, D5, D3, D1)
SCK
(
SI(IO0)
RDTSd 8
4 SO(IO1)
4
4
(D6, D4, D2, D0) “000
H
”
CS
CS
SCK
RDTSs
4
0
RDTSd
RDIO
CS
0
1
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
OP-CODE
SI
(IO0)
SO
(IO1)
0 1 1
1
1 0
Data Out
0 0 6
4
2 0 14 12 10 8 22 20 18 16 30 28 26 24
High-Z
7
5
LSB
3 1 15 13 11 9 23 21 19 17 31 29 27 25
MSB
Byte0
14
LSB
LSB
LSB
MSB
Byte1
MSB
Byte2
MSB
Byte3
Invalid
DS501-00031-1v1-J
MB85RDP16LX
• WRTSs (Single SO)
WRTSs FRAM
) SI
(
WRTSs
8
8
FRAM
“000
H
CS
”
CS
WRTSs
8
0
WRTSs
WRITE
CS
0
1
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
OP-CODE
SI
0 0
1 1
1 1
Data In
1 1 7
6
5
4 3
2
1
0 15 14 13 12 11 10 9
MSB
Byte0
High-Z
SO
Invalid
8
LSB
LSB MSB
Byte1
• WRTSd (Dual IO)
WRTSd
)
FRAM
SI(IO0)
WRTSd
4
(D7, D5, D3, D1)
SI(IO0)
(D6, D4, D2, D0)
FRAM “000
H
(
8
SO(IO1)
4
CS
”
CS
WRTSd
8
0
WRTSd
WDIO
CS
0
1
2
3 4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
OP-CODE
SI
(IO0)
SO
(IO1)
0 1 1
1
1 1
Data In
1 1 6
4
2 0 14 12 10 8 22 20 18 16 30 28 26 24
High-Z
7
5
MSB
MSB
Byte1
MSB
Byte2
Invalid
LSB
3 1 15 13 11 9 23 21 19 17 31 29 27 25
Byte0
DS501-00031-1v1-J
LSB
LSB
LSB
Invalid
MSB
Byte3
15
MB85RDP16LX

BP1, BP0 WRITE
WDIO
BP1
BP0
0
0
0
1
600H
7FFH (
1/4)
1
0
400H
7FFH (
1/2)
1
1
000H
7FFH ()

WEL, WPEN, WP WRITE
WEL
WRSR
WPEN
0
X
X
1
0
X
1
1
0
1
1
1
() POS0/1/2/3
16
WDIO
DIBC/DDBC
WRTSs/WRTSd
DS501-00031-1v1-J
MB85RDP16LX

for POS0/1/2/3
POS0/1/2/3 43
3
“000
H”“005
(Counter(0)
(PP, DIR, DIR’)
2
H”
FRAM
Counter(42))
(Eflag(0), Eflag(1))
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
000H
Counter(5)
Counter(4)
Counter(3)
Counter(2)
Counter(1)
Counter(0)
DIR
PP
001H
Counter(13) Counter(12) Counter(11) Counter(10) Counter(9)
Counter(8)
Counter(7)
Counter(6)
002H
Counter(21) Counter(20) Counter(19) Counter(18) Counter(17) Counter(16) Counter(15) Counter(14)
003H
Counter(29) Counter(28) Counter(27) Counter(26) Counter(25) Counter(24) Counter(23) Counter(22)
004H
Counter(37) Counter(36) Counter(35) Counter(34) Counter(33) Counter(32) Counter(31) Counter(30)
005H
()
Eflag(1)
Eflag(0)
DIR’
Counter(42) Counter(41) Counter(40) Counter(39) Counter(38)
FRAM
WRTSs/WRTSd

for POS0/1/2/3
2
(Eflag(1,0)) “00”
Eflag(1,0)
Status
“00”
“01”
“10”
counter(42:0)
counter(42:0)
400_0000_0000H
3FF_FFFF_FFFFH
3FF_FFFF_FFFFH
400_0000_0000H
ECC
“11”
()
Eflag(1,0)
FRAM
FRAM
DS501-00031-1v1-J
17
MB85RDP16LX

for POS0/1/2/3
1
3FF_FFFF_FFFFH
1
400_0000_0000H
3FF_FFFF_FFFFH Eflag(1,0)
Counter Value (decimal)
Counter Value (hex)
3FF FFFF FFFF
+
242-1
3FF FFFF FFFE
+
242-2
3FF FFFF FFFD
+
242-3
…
+
…
000 0000 0002
+
2
000 0000 0001
+
1
000 0000 0000
+
0
7FF FFFF FFFF
-
1
7FF FFFF FFFE
-
2
…
-
…
400 0000 0002
-
242-2
400 0000 0001
-
242-1
400 0000 0000
-
242

400_0000_0000H
"01"
for DIBC/DDBC
DIBC/DDBC 46
2
(Counter(0)
(Eflag(0), Eflag(1))
“000H”
“005H”
Counter(45))
FRAM
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
000H
Counter(7)
Counter(6)
Counter(5)
Counter(4)
Counter(3)
Counter(2)
Counter(1)
Counter(0)
001H
Counter(15) Counter(14) Counter(13) Counter(12) Counter(11) Counter(10) Counter(9)
Counter(8)
002H
Counter(23) Counter(22) Counter(21) Counter(20) Counter(19) Counter(18) Counter(17) Counter(16)
003H
Counter(31) Counter(30) Counter(29) Counter(28) Counter(27) Counter(26) Counter(25) Counter(24)
004H
Counter(39) Counter(38) Counter(37) Counter(36) Counter(35) Counter(34) Counter(33) Counter(32)
005H
()
18
Eflag(1)
Eflag(0)
Counter(45) Counter(44) Counter(43) Counter(42) Counter(41) Counter(40)
FRAM
WRTSs/WRTSd
DS501-00031-1v1-J
MB85RDP16LX

for DIBC/DDBC
2
(Eflag(1,0)) “00”
Eflag(1,0)
Status
“00”
“01”
“10”
counter(45:0)
counter(45:0)
2000_0000_0000H 1FFF_FFFF_FFFF
H
1FFF_FFFF_FFFFH
2000_0000_0000H
ECC
“11”
()
Eflag(1,0)
FRAM
FRAM

for DIBC/DDBC
1FFF_FFFF_FFFFH
2000_0000_0000H
1
Counter Value (hex)
1
2000_0000_0000H
1FFF_FFFF_FFFFH
Eflag(1,0)
Counter Value (decimal)
1FFF FFFF FFFF
+
245-1
1FFF FFFF FFFE
+
245-2
1FFF FFFF FFFD
+
245-3
…
+
…
0000 0000 0002
+
2
0000 0000 0001
+
1
0000 0000 0000
+
0
3FFF FFFF FFFF
-
1
3FFF FFFF FFFE
-
2
…
-
…
2000 0000 0002
-
45
2 -2
2000 0000 0001
-
245-1
2000 0000 0000
-
245
DS501-00031-1v1-J
"01"
19
MB85RDP16LX

*
VDD
− 0.5
+ 2.5
V
*
VIN
− 0.5
VDD + 0.5
V
*
VOUT
− 0.5
VDD + 0.5
V
TA
− 40
+ 105
℃
Tstg
− 55
+ 125
℃
, VSS
(0 V)
<
>
(
,
,
)

*1
VDD
*
2
1.65
− 40
TA
1.8
1.95
V
⎯
+ 105
℃
1 VSS (0 V)
2
<
>
,
20
,
DS501-00031-1v1-J
MB85RDP16LX

1.
|ILI|
CS = VDD
⎯
⎯
1
WP, SCK,
⎯
⎯
1
⎯
⎯
1
μA
μA
|ILO|
SI = 0 V to VDD
SO = 0 V to VDD
IDD
SCK = 15 MHz
⎯
⎯
0.7
mA
ISB
SCK = SI= CS = VDD
⎯
1 (25 )
11 (105℃)
6 (85℃)
μA
“H”
VIH
VDD = 1.65 to 1.95 V
VDD × 0.8
⎯
VDD + 0.3
V
“L”
VIL
VDD = 1.65 to 1.95 V
− 0.5
⎯
VDD × 0.2
V
“H”
VOH
IOH = −2 mA
VDD − 0.5
⎯
VDD
V
“L”
VOL
IOL = 2 mA
VSS
⎯
0.4
V
DS501-00031-1v1-J
21
MB85RDP16LX
2.
SCK
fCK
⎯
15
MHz
for SPI
tCH
33
⎯
ns
for SPI
tCL
33
⎯
ns
fCK
⎯
7.5
MHz
ns
for SPI
SCK for Dual SPI
POS0/1/2/3
for Dual SPI
tCH
66
⎯
for Dual SPI
tCL
66
⎯
ns
fDCK
⎯
2
MHz
fDCK
⎯
5
MHz
tCH
50
⎯
ns
tCL
50
⎯
ns
tCSU
10
⎯
ns
tCSH
10
⎯
ns
tOD
⎯
20
ns
tODV
⎯
18
ns
tOH
0
⎯
ns
tD
30
⎯
ns
tR
⎯
50
ns
tF
⎯
50
ns
tSU
5
⎯
ns
tH
5
⎯
ns
(
POS0/1/2/3
DIBC/DDBC
SCK
< 3 μs)
DIBC/DDBC
SCK
3 μs)
DIBC/DDBC
POS0/1/2/3
DIBC/DDBC
(
POS0/1/2/3
: 1.65 V
22
1.95 V
: − 40 °C + 105 °C
: 0.3 V 1.65 V
: 5 ns
: 5 ns
: VDD/2
: VDD/2
DS501-00031-1v1-J
MB85RDP16LX
AC
1.8 V
1.2 k
Output
30 pF
0.95 k
3.
CO
CI
DS501-00031-1v1-J
VDD = VIN = VOUT = 0 V
f = 1 MHz, TA = + 25 °C
⎯
4
pF
⎯
4
pF
23
MB85RDP16LX

•
24
DS501-00031-1v1-J
MB85RDP16LX

trs
tpd
trh
tr
tf
tpu
VDD
VDD
RST
RST
1.65 V
1.65 V
VIH (Min)
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
GND
GND
CS >VDD × 0.8 *
CS
CS >VDD × 0.8 *
CS : don't care
CS
* : CS (Max) < VDD + 0.3 V
OFF
CS
RST
RST
OFF
RST
ON
VDD(min)
DS501-00031-1v1-J
VDD(min)
RST
tpd
400
⎯
tpu
1
⎯
μs
tf
3
⎯
μs
tr
3
⎯
μs
trs
0
μs
trh
1
μs
ns
25
MB85RDP16LX
 FRAM
*1
/
*2
1
10
13
10
⎯
⎯
/
TA 105
℃
TA 105
℃
FRAM /
2

26
DS501-00031-1v1-J
MB85RDP16LX
 ESD
DUT
ESD HBM
JESD22-A114
ESD MM
JESD22-A115
ESD CDM
JESD22-C101
2000 V
2000 V
200 V
200 V
―
―
MB85RDP16LXPN-G-AMEWE1
JESD78
―
JESD78
―
Proprietary method
C-V
Proprietary method
200 V
200 V
A
VDD
IIN
VDD
-
VSS
V
VIN
VIN
IIN
I/O
+
DUT
IIN 300 mA
±300 mA
IIN
DS501-00031-1v1-J
300 mA
27
MB85RDP16LX
C-V
A
1
2
VDD
SW
DUT
+
V
VIN
C
200pF
-
SW2
1
1
VDD
VSS
2
5
5

JEDEC Moisture Sensitivity Level 3 (IPC / JEDEC J-STD-020D)

REACH
28
EU RoHS
RoHS
DS501-00031-1v1-J
MB85RDP16LX

MB85RDP16LXPN-G-AMEWE1
DS501-00031-1v1-J
SON, 8
(LCC-8P-M04)
1500
29
MB85RDP16LX

0.5 mm
SON, 8
2.0 mm
3.0 mm
0.75 mm Max.
0.015g
(LCC-8P-M04)
SON, 8
LCC-8P-M04
1.6±0.10
(.063±.004)
2.00±0.07
(.079±.003)
0.40±0.07
(.016±.003)
3.00±0.07
(.118±.003)
1.40±0.10
(.055±.004)
INDEX AREA
1PIN CORNER
(C0.30(C.012))
0.50(.020)
TYP
0.05(.002) MAX
0.25±0.05
(.010±.002)
0.70±0.05
(.028±.002)
0.15(.006)
mm
C
30
inches
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC8-04Sc-1-1
DS501-00031-1v1-J
MB85RDP16LX

[MB85RDP16LXPN-G-AMEWE1]
YYWW
P16X
0XX
[LCC-8P-M04]
DS501-00031-1v1-J
31
MB85RDP16LX

|
,
32
27
 ESD
28

30



DS501-00031-1v1-J
MB85RDP16LX
MEMO
DS501-00031-1v1-J
33
MB85RDP16LX
MEMO
34
DS501-00031-1v1-J
MB85RDP16LX
MEMO
DS501-00031-1v1-J
35
MB85RDP16LX
富士通セミコンダクター株式会社
222-0033
2-100-45
http://jp.fujitsu.com/fsl/
0120-198-610