GA08JT17-247 Normally – OFF Silicon Carbide Junction Transistor Features Package RoHS Compliant 175 °C Maximum Operating Temperature Gate Oxide Free SiC Switch Exceptional Safe Operating Area Excellent Gain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Coefficient of RDS,ON Suitable for Connecting an Anti-parallel Diode VDS = 1700 V RDS(ON) = 230 mΩ ID @ Tc=125°C = 8A hFE Tc=25°C = 60 D D G S D S G TO-247AB Advantages Applications Compatible with Si MOSFET/IGBT Gate Drive ICs > 20 µs Short-Circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal Distortion High Amplifier Bandwidth Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor Drives Absolute Maximum Ratings Parameter Drain – Source Voltage Continuous Drain Current Continuous Gate Current Symbol VDS ID IGM Turn-Off Safe Operating Area RBSOA Short Circuit Safe Operating Area SCSOA Reverse Gate – Source Voltage Reverse Drain – Source Voltage Power Dissipation Storage Temperature VSG VSD Ptot Tstg Conditions VGS = 0 V TC = 125 °C o TVJ = 175 C, IG = 1 A, Clamped Inductive Load TVJ = 175 oC, IG = 1 A, VDS = 1200 V, Non Repetitive TC = 125 °C Value 1700 8 1.5 ID,max = 8 @ VDS ≤ VDSmax Unit V A A Notes Fig. 6 Fig. 19 A Fig. 16 20 µs 30 50 48 -55 to 175 V V W °C Fig. 14 Electrical Characteristics Parameter Symbol Conditions Drain – Source On Resistance RDS(ON) ID = 8 A, Tj = 25 °C ID = 8 A, Tj = 125 °C ID = 8 A, Tj = 175 °C Gate Forward Voltage VGS(FWD) IG = 500 mA, Tj = 25 °C IG = 500 mA, Tj = 175 °C hFE VDS = 5 V, ID = 8 A, Tj = 25 °C VDS = 5 V, ID = 8 A, Tj = 175 °C Drain Leakage Current IDSS VR = 1700 V, VGS = 0 V, Tj = 25 °C VR = 1700 V, VGS = 0 V, Tj = 125 °C VR = 1700 V, VGS = 0 V, Tj = 175 °C Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C Min. Value Typical Max. Unit Notes mΩ Fig. 5 V Fig. 4 – Fig. 5 μA Fig. 6 On State Characteristics DC Current Gain 230 410 560 3.0 2.8 60 40 Off State Characteristics Aug 2014 0.2 0.5 2.0 20 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ 10 50 100 nA Pg 1 of 10 GA08JT17-247 Electrical Characteristics Parameter Symbol Conditions Ciss Crss/Coss EOSS VGS = 0 V, VD = 800 V, f = 1 MHz VD = 800 V, f = 1 MHz VGS = 0 V, VD = 1000 V, f = 1 MHz RG(INT-ZERO) RG(INT-ON) td(on) tf td(off) tr td(on) tf td(off) tr Eon Eoff Etot Eon Eoff Etot f = 1 MHz, VAC = 25 mV, Tj = 175 ºC VGS > 2.5 V Min. Value Typical Unit Notes 850 20 8.6 pF pF µJ Fig. 7 Fig. 7 Fig. 8 6.0 0.9 12 23 20 14 12 22 31 11 267 23 290 253 12 265 Ω Ω ns ns ns ns ns ns ns ns µJ µJ µJ µJ µJ µJ 1.03 °C/W Max. Capacitance Characteristics Input Capacitance Reverse Transfer/Output Capacitance Output Capacitance Stored Energy Switching Characteristics 1 Internal Gate Resistance, Zero Bias Internal Gate Resistance, On Turn On Delay Time Fall Time, VDS Turn Off Delay Time Rise Time, VDS Turn On Delay Time Fall Time, VDS Turn Off Delay Time Rise Time, VDS Turn-On Energy Per Pulse Turn-Off Energy Per Pulse Total Switching Energy Turn-On Energy Per Pulse Turn-Off Energy Per Pulse Total Switching Energy 1 Tj = 25 ºC, VDS = 1100 V, ID = 8 A, RG(EXT) = 20 Ω, CG = 9 nF, VG = 20/-5 V, Load = 138 Ω Refer to Fig. 20 for IG Waveform Tj = 175 ºC, VDS = 1100 V, ID = 8 A, RG(EXT) = 20 Ω, CG = 9 nF, VG = 20/-5 V, Load = 138 Ω Refer to Fig. 20 for IG Waveform Tj = 25 ºC, VDS = 1100 V, ID = 8 A, RG(EXT) = 20 Ω, CG = 9 nF, VG = 20/-5 V, Load = 1.05 mH Tj = 175 ºC, VDS = 1100 V, ID = 8 A, RG(EXT) = 20 Ω, CG = 9 nF, VG = 20/-5 V, Load = 1.05 mH Fig. 9, 11 Fig. 10, 12 Fig. 9 Fig. 10 Fig. 9, 11 Fig. 10, 12 Fig. 9 Fig. 10 – All times are relative to the Drain-Source Voltage VDS Thermal Characteristics Thermal resistance, junction - case RthJC Fig. 17 Figures Figure 1: Typical Output Characteristics at 25 °C Aug 2014 Figure 2: Typical Output Characteristics at 125 °C http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 2 of 10 GA08JT17-247 Figure 3: Typical Output Characteristics at 175 °C Figure 4: Typical Gate Source I-V Characteristics vs. Temperature Figure 5: Normalized On-Resistance and Current Gain vs. Temperature Figure 6: Typical Blocking Characteristics Figure 7: Input, Output, and Reverse Transfer Capacitance Figure 8: Output Capacitance Stored Energy Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 3 of 10 GA08JT17-247 2 Figure 9: Typical Turn On Energy Losses and Switching Times vs. Temperature Figure 10: Typical Turn Off Energy Losses and Switching Times vs. Temperature Figure 11: Typical Turn On Energy Losses and Switching Times vs. Drain Current Figure 12: Typical Turn Off Energy Losses and Switching Times vs. Drain Current Figure 13: Typical Hard Switched Device Power Loss vs. Switching Frequency 2 Figure 14: Power Derating Curve – Representative values based on device conduction and switching loss. Actual losses will depend on gate drive conditions, device load, and circuit topology. Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 4 of 10 GA08JT17-247 Figure 15: Forward Bias Safe Operating Area at Tc = 25 °C Figure 16: Turn-Off Safe Operating Area Figure 17: Transient Thermal Impedance Figure 18: Drain Current Derating vs. Pulse Width Figure 19: Drain Current Derating vs. Temperature Figure 20: Typical Gate Current Waveform Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 5 of 10 GA08JT17-247 Driving the GA08JT17-247 A. Gate Drive Theory of Operation The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 21. Figure 21: Idealized Gate Current Waveform Gate Currents, IG,pk/-IG,pk and Voltages during Turn-On and Turn-Off An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, QG, for turn-on is supplied by a burst of high gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. The IG,pon pulse should ideally terminate, when the drain voltage falls to its on-state value, in order to avoid unnecessary drive losses during the steady on-state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the TO-247 package and drive circuit. A voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The applied gate voltage should be maintained high enough, above the V GS,ON level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with V GS = 0 V, a negative gate voltage VGS may be used in order to speed up the turn-off transition. Steady On-State After the device is turned on, IG may be advantageously lowered to IG,steady for reducing unnecessary gate drive losses. The I G,steady is determined by noting the DC current gain, hFE, of the device. The desired IG,steady is determined by the peak device junction temperature TJ during operation, drain current ID, DC current gain hFE, and a 50 % safety margin to ensure operating the device in the saturation region with low on-state voltage drop by the equation: Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 6 of 10 GA08JT17-247 B. Gate Drive Implementation Examples Using the IXYS IX2204 Gate Driver The IXYS IX2204 is a dual output gate drive integrated circuit which can be used to drive an SJT by supplying the required gate drive current IG in a low-power gate drive solution. This configuration features an external gate capacitor, C G, which creates the brief current peak IG,on during device turn-on and IG,off during turn-off for fast switching and an external gate resistor R G(EXT) to set the continuous gate current IG,steady required for the device to remain on. This configuration is shown in Figure 22 with further details provided below. Gate Signal Isolation Barrier VGH U1 INA IXYS IX2204 INB Vin QHA OUTHA RCG Rb VGH FAULT BLANK VLA TRISTATE VHB SiC SJT QLA D Rch VEE VGL VEE VGL VGL DESAT CG OUTLA Rb X1 Vin VGH VHA IG G QHB OUTHB S Rb X2 MODE OUTLB Rb GND Vin VLB DRG RG(EXT) VEE VEE X3 QLB Optional VEE Figure 22: Gate drive configuration using an IXYS IX2204 gate drive IC. Table 1: Recommended Component List for implementing the IX2204 based Gate Drive for the GA08JT17-247 Reference Component RG(EXT) CG RCG DRG Rb QHA, QHB QLA, QLB U1 Gate Resistance, External Gate Capacitance Damping Resistor Silicon Schottky Diode BJT Base Resistor Current Boost NPN Current Boost PNP Signal Isolator X1 DC/DC Converter, VGH Supply X2 X3 DC/DC Converter, VGL Supply DC/DC Converter, VEE Supply Description 2.0 Ω, 2 W 10 nF 1.0 Ω, 0.5 W 40 V, 2 A 1.0 Ω, 0.5 W 40 V, 8 A, Silicon NPN BJT 40 V, 8 A, Silicon PNP BJT Opto-Isolator –or– Transformer Isolator VOUT = +20 V, VIN = +12 V, 2 W, VISO = 5.2 kV VOUT = +5 V, VIN = +12 V, 3 W, VISO = 3.0 kV VOUT = -5 V, VIN = +12 V, 2 W, VISO = 5.2 kV Suggested Part CRM2512-JW-2R2ELF C1812C103J1GACTU ERJ-1TYJ1R0U SS24T3G ERJ-1TYJ1R0U MJD44H11 MJD45H11 ACPL-4800 / ADUM3210 MGJ2D122005SC MEV3S1205SC MGJ2D122005SC Voltage Supply Selection The IX2204 gate drive design requires three supply voltages VGH, VGL, and VEE (listed in Table 2) optionally supplied through DC/DC converters. During device turn-on, VGH charges the external capacitor CG thereby delivering the narrow width, high current pulse I G,on to the SJT gate and charges the SJT’s internal terminal capacitances C GD and CGS. For a given level of parasitic inductance in the gate circuit and SJT package, the rise time of IG,on is controlled by the choice of VGH and CG. During the steady on-state, VGL in combination with the internal and external gate resistances provides a continuous gate current for the GA08JT17-247 to remain on. The VEE supply sets the gate negative during turn-off and steady off-state for faster switching and to avoid spurious turn-on which may be caused by external circuit noise. The power rating of the voltage supplies should be adequate to meet the gate drive power requirements as determined by Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 7 of 10 GA08JT17-247 Table 2: IX2204 Gate Drive Example Component List Values Symbol Parameter Range Typical VGH Supply Voltage, Driver Output A 15 – 20 + 20.0 VGL Supply Voltage, Driver Output B 5.0 – 7.0 + 5.0 VEE Negative Supply Voltage -10 – GND - 5.0 Gate Capacitor CG Selection VGH / VEE RCG CG Rch D IG G RG(INT) S VGL / VEE DRG RG(EXT) Figure 23: Primary gate drive circuit passive components with series gate resistance Schottky rectifier. An external gate capacitor CG connected directly to the device gate pin delivers the positive current peak I G,on during device turn-on and the negative current peak IG,off during turn-off. A low value resistor RCG is connected in series with CG to damp potential high-frequency oscillation. A high value resistor Rch in parallel with CG sets the SJT gate to a defined potential (-VEE) during steady off-state. At device turn-on, CG is pulled to VGH which produces a transient peak of gate voltage and current. This current peak rapidly charges the internal SJT CGS and CGD capacitances. A Schottky diode, DRG, in series with RG(EXT) blocks any CG induced current from draining out through RG(EXT) and ensures that all of the charge within CG flows only into the device gate, allowing for an ultra-fast device turn-on. During steady onstate, a potential of VGH - VGS = VGH – 3 V is across CG. When the device is turned off, CG is pulled to negative VEE and VGS is pulled to a transient peak of VGS,turn-off = VEE – (VGH – 3 V), this induces the negative current peak I G,off out of the gate which discharges the SJT internal capacitances. External Gate Resistor RG(EXT) Selection An external gate resistor RG(EXT) connected directly to the SJT gate pin acts to deliver a continuous current IG,steady during steady on-state. The gate current is determined by: The on-state gate-source voltage VGS(FWD) can be approximated to 3 V and the Schottky on-state voltage VSch can be approximated to 0.3 V which simplifies the equation to: The desired IG,steady is determined by the peak device junction temperature TJ during operation, drain current ID, DC current gain β, and a 50 % safety margin to avoid operating the device in saturation. IG,steady may also be approximated from the temperature dependent on-state curves of the device in Figures Error! Reference source not found. – Error! Reference source not found., provided that a 50 % increase is given. Symbol CG RCG Rch RG(EXT) RG(INT-ON) DRG Aug 2014 Table 3: Passive Output Component List Values Parameter Range Typical Gate Capacitor, External 5 – 20 10 Damping Resistor of Gate Capacitor 0.5 – 2.0 1.0 Charging Resistor 500 – 10k 1k Gate Resistor, External 0.4 – 5 2 Gate Resistance, Internal, On-State 0.5 – 1.5 0.9 Schottky Diode of Gate Resistor --- http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Units nF Ω Ω Ω Ω Pg 8 of 10 GA08JT17-247 Optional Gate Current Boost Network An optional output totem-pole network may be attached to the IX2204 output pins as shown in Figure 22 using either silicon BJTs (shown) or MOSFETs. This configuration allows the IX2204 to directly drive the BJT bases or MOSFET gates and not supply the full peak and steady state gate current entering the SJT gate. The primary gate current delivery device is transferred to the discrete components which have higher power dissipation ratings than the IX2204. Voltage Supply Isolation The DC/DC supply voltage converters are suggested to provide isolation at a minimum of twice the working VDS on the SJT transistor during off-state to provide adequate protection to circuitry external to the gate drive circuit. Suggested DC/DC converters have an isolation of 3.0 kV or greater. Alternatively, DC/DC converter galvanic isolation may be bypassed and direct connection of variable voltage supplies may be done, this may be convenient during testing and prototyping but carries risk and is not suggested for extended usage. Vin VGH COUT CIN Figure 24: Typical DC/DC converter configuration Signal Isolation The gate supply signal is suggested to be isolated to twice the working V DS on the SJT during off-state to provide adequate protection to circuitry external to the gate drive circuit. This may be done using opto or galvanic isolation techniques. Additional Features The IX2204 has additional functionality available which is unused in the given configuration. Desaturation detection and fault status monitoring may be implemented by un-grounding the DESAT, BLANK, and TRISTATE pins and configuring them as recommended in the IX2204 datasheet, available from IXYS. Active miller clamping is also available on other gate drive ICs which may also be desired in some SJT switching applications but is not required, refer to specific gate drive IC datasheets for more information. C. Alternative Gate Drive ICs dividual product manufacturers. Table 4 features a partial list of alternative gate drive ICs which may be used for driving the GA08JT17-247; specific product information should be obtained from the individual product manufacturers. Table 4: Additional Commercial Gate Drivers Compatible with GA08JT17-247 Manufacturer Part Number Optical Signal Isolation Desaturation Detection Features Active Miller Gate Clamping3 High Side Capability Number of Outputs Avago Tech. HCPL-316J – 1 Avago Tech. HCPL-322J 1 IXYS IXD_604 – – – 2 IXYS IXD_614 – – – 1 Micrel MIC4452YN – – – 1 Microsemi LX4510 – – – 1 Texas Instruments UCC27322 – – – 1 3 – Active Miller Gate Clamping recommended for VEE = GND switching applications as SJT and/or output BJT secondary gate discharge path. Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 9 of 10 GA08JT17-247 Package Dimensions: TO-247AB (4.318 REF.) 0.170 REF. (5.486) 0.216 PACKAGE OUTLINE (15.748) (16.256) 0.620 0.640 0.55 (13.97) 0.236 (5.99) 0.171 (4.699) 0.208 (5.283) 0.045 (1.14) 0.054 (1.36) 0.059 (1.498) 0.098 (2.489) 0.22 (5.59) 0.242 BSC. (6.147 BSC.) 0.819 0.844 (20.803) (21.438) 0.012 (0.3) 0.652 (16.56) Ø 0.140 (3.556) 0.143 (3.632) Ø 0.118 (3.00) Ø 0.283 (7.19) GA08JT17-247 XXXXXX Lot code 0.780 0.800 (19.812) (20.320) 0.177 MAX (4.496) 0.065 (1.651) 0.083 (2.108) 0.040 (1.016) 0.055 (1.397) 0.2146 (5.451) BSC. 0.016 (0.406) 0.031 (0.787) 0.075 (1.905) 0.115 (2.921) NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS Revision History Date Revision Comments 2014/08/26 2014/06/23 8 7 Updated Electrical Characteristics Updated Electrical Characteristics 2014/02/06 2013/12/18 6 5 Updated Electrical Characteristics Updated Gate Drive Section Supersedes Published by GeneSiC Semiconductor, Inc. 43670 Trade Center Place Suite 155 Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 10 of 10 GA08JT17-247 SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/sjt/GA08JT17-247_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA08JT17-247. * MODEL OF GeneSiC Semiconductor Inc. * * $Revision: 1.3 $ * $Date: 26-AUG-2014 $ * * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * * COPYRIGHT (C) 2014 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. * .model GA08JT17 NPN + IS 3.73E-47 + ISE 5.50E-27 + EG 3.2 + BF 63 + BR 0.55 + IKF 200 + NF 1 + NE 2.021 + RB 6.0 + RBM 0.9 + IRB 1e-4 + RE 0.103394007 + RC 0.151605993 + CJC 2.77E-10 + VJC 3.023103628 + MJC 0.460762158 + CJE 8.23E-10 + VJE 2.945448229 + MJE 0.498044294 + XTI 3 + XTB -0.7 + TRC1 7.50E-3 + VCEO 1700 + ICRATING 8 + MFG GeneSiC_Semiconductor *End of GA08JT17 SPICE Model Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 1