ONSEMI NTQS6463

NTQS6463
Power MOSFET
−20 V, −6.8 A, P−Channel TSSOP−8
Features
•
•
•
•
•
•
•
New Low Profile TSSOP−8 Package
Ultra Low RDS(on)
Higher Efficiency Extending Battery Life
Logic Level Gate Drive
Diode Exhibits High Speed, Soft Recovery
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperatures
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VDSS
RDS(on) TYP
ID MAX
−20 V
20 m @ −10 V
−6.8 A
Applications
• Power Management in Portable and Battery−Powered Products, i.e.:
•
•
P−Channel
Computers, Printers, PCMCIA Cards, Cellular and Cordless
Telephones
Lithium Ion Battery Applications
Note Book PC
D
G
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
−20
V
Gate−to−Source Voltage
VGS
12
V
Drain Current (Note 1)
− Continuous @ TA = 25°C
− Continuous @ TA = 70°C
− Pulsed (Note 3)
Total Power Dissipation (Note 1)
@ TA = 25°C
Drain Current (Note 2)
− Continuous @ TA = 25°C
− Continuous @ TA = 70°C
− Pulsed (Note 3)
ID
ID
IDM
−5.5
−4.4
30
PD
0.93
8
TSSOP−8
CASE 948S
PLASTIC
W
463
YWW
N
1
A
IDM
PD
1.39
W
TJ, Tstg
−55 to
+150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 40 V, IL = 18.4 A,
L = 5.0 mH, RG = 25 )
EAS
845
mJ
Thermal Resistance −
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
RJA
Operating and Storage
Temperature Range
MARKING
DIAGRAM
A
−6.8
−5.4
30
Total Power Dissipation (Note 2)
@ TA = 25°C
S
ID
ID
°C/W
463
Y
WW
N
= Device Code
= Year
= Work Week
= MOSFET
PIN ASSIGNMENT
1
D
S
S
2
3
G
4
134
90
8
7
6
5
D
S
S
D
Top View
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Minimum 3″ X 3″ FR−4 board, steady state.
2. Mounted on 1″ square (1 oz.) board, steady state.
3. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%.
ORDERING INFORMATION
Package
Shipping†
NTQS6463
TSSOP−8
100 Units/Rail
NTQS6463R2
TSSOP−8
3000/Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2004
September, 2004 − Rev. 2
1
Publication Order Number:
NTQS6463/D
NTQS6463
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
VGS(th)
−0.45
−0.9
−
V
Gate−Body Leakage (VGS = 0 V, VGS = ±8 V)
IGSS
−
−
±100
nA
Zero Gate Threshold Voltage Drain Current
(VDS = −16 V, VGS = 0 V)
(VDS = −16 V, VGS = 0 V, TJ = 70C)
IDSS
−
−
−
−
−1.0
−10
−
−
0.016
0.022
0.020
0.027
Characteristic
STATIC
Gate Threshold Voltage (VDS = VGS, ID = −250 µA)
Drain−Source On−State Resistance (Note 4)
(VGS = −4.5 V, ID = −6.8 A)
(VGS = −2.5 V, ID = −5.5 A)
µΑ
Ω
RDS(on)
Forward Transconductance (VDS = −15 V, ID = −6.8 A) (Note 4)
gFS
−
21
−
S
Diode Forward Voltage (IS = −1.3 A, VGS = 0 V) (Note 4)
VSD
−
−0.71
−1.1
V
Qg
−
28
50
nC
DYNAMIC
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
(VDS = −10 V,
VGS = −5.0 V,
ID = −6.8
6 8 A)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Source−Drain Reverse Recovery Time
(VDD = −10
10 V,
V
ID ≅ −1.0
1.0 A,
VGS = −4.5 V,
6 0 Ω)
RG = 6.0
(IF = −1.3 A, di/dt = 100 A/µs)
4. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
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2
Qgs
−
5.5
−
Qgd
−
9.0
−
td(on)
−
15
25
tr
−
22
40
td(off)
−
90
150
tf
−
53
90
trr
−
45
80
ns
ns
NTQS6463
16
−2.2 V
−2.8 V
−4 V
−6 V
−10 V
6
VDS ≥ −10 V
−2 V
−2.4 V
8
−ID, DRAIN CURRENT (A)
−ID, DRAIN CURRENT (A)
10
TJ = 25°C
−1.8 V
4
−1.6 V
2
12
TJ = 25°C
8
TJ = 100°C
4
TJ = −55°C
VGS = −1.4 V
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
0
2
1.5
2
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.04
ID = −7.4 A
TJ = 25°C
0.03
0.02
0.01
0
2
4
6
8
10
2.5
0.03
TJ = 25°C
0.025
VGS = −2.5
0.02
VGS = −4.5
0.015
0.01
2
4
6
8
10
12
14
−VGS, GATE−TO−SOURCE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.6
1000
VGS = 0 V
1.4
ID = −7.4 A
VGS = −4.5 V
−IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
1
−VGS, GATE−TO−SOURCE VOLTAGE (V)
0.05
0
0.5
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
0
1.2
1
TJ = 125°C
100
TJ = 100°C
0.8
0.6
−50
10
−25
0
25
50
75
100
125
150
4
8
12
16
TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation versus
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
20
NTQS6463
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6000
Ciss
C, CAPACITANCE (pF)
TJ = 25°C
VDS = 0 V
VGS = 0
5000
4000
Crss
3000
Ciss
2000
1000
0
−10
Coss
Crss
−5
0
VGS
5
10
15
20
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
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4
QT
4
VGS = −4.5
3
Q1
Q2
2
1
TJ = 25°C
ID = −6.8 A
0
0
4
8
12
16
20
28
24
1000
VDD = −16 V
ID = −6.8 A
VGS = −4.5 V
tf
t, TIME (ns)
5
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−VGS, GATE−TO−SOURCE VOLTAGE (V)
NTQS6463
td(off)
100
td(on)
10
1
10
100
Qg, TOTAL GATE CHARGE (nC)
RG, GATE RESISTANCE ()
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
100
VGS = 0 V
TJ = 25°C
1.2
−ID, DRAIN CURRENT (A)
−IS, SOURCE CURRENT (A)
tr
0.8
0.4
0
0.4
0.5
0.6
Mounted on 2″ sq. FR4 board (1″ sq. 1 oz. Cu 0.06″ thick single sided)
10 s
100 s
10
1 ms
10 ms
1
0.1
VGS = −4.5 V
SINGLE PULSE
TC = 25°C
0.01
0.1
0.7
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage versus
Current
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr, tf) do not exceed 10 s. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature.
Maximum energy at currents below rated continuous ID can
safely be assumed to equal the values indicated.
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5
NTQS6463
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S−01
ISSUE O
8x
0.20 (0.008) T U
K REF
0.10 (0.004)
S
2X
L/2
8
B
−U−
1
V
S
J J1
4
PIN 1
IDENT
S
T U
5
L
0.20 (0.008) T U
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
ÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇ
K1
K
A
−V−
SECTION N−N
−W−
C
0.076 (0.003)
D
−T− SEATING
DETAIL E
G
PLANE
P
0.25 (0.010)
N
M
N
P1
DIM
A
B
C
D
F
G
J
J1
K
K1
L
M
P
P1
MILLIMETERS
MIN
MAX
2.90
3.10
4.30
4.50
−−−
1.10
0.05
0.15
0.50
0.70
0.65 BSC
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
−−−
2.20
−−−
3.20
INCHES
MIN
MAX
0.114
0.122
0.169
0.177
−−−
0.043
0.002
0.006
0.020
0.028
0.026 BSC
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
−−−
0.087
−−−
0.126
F
DETAIL E
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your
local Sales Representative.
NTQS6463/D