[AK4386] AK4386 100dB 96kHz 24-Bit 2ch ΔΣ DAC AK4386 24 DAC ΔΣ 3V DR=100dB (SCF) AK4386 AK4386 MP3 16pin TSSOP STB, TV Sampling Rate: 8kHz ∼ 96kHz 24-Bit 8 times FIR Digital Filter SCF with high tolerance to clock jitter Single-ended output buffer Digital de-emphasis for 44.1kHz sampling I/F Format: 24-Bit MSB justified, 16/24-Bit LSB justified, I2S Compatible Master Clock: 512/768/1024/1536fs for Half Speed (8kHz ∼ 24kHz) 256/384/512/768fs for Normal Speed (8kHz ∼ 48kHz) 128/192/256/384fs for Double Speed (48kHz ∼ 96kHz) CMOS Input Level THD+N: −86dB DR, S/N: 100dB(@VDD=3.0V) Power Supply: 2.2 to 3.6V Ta = −20 ∼ 85°C (ET), −40 ∼ 85°C (VT) 16pin TSSOP TEST PDN DEM MCLK VDD De-emphasis Control DFS1 VSS Clock Divider VCOM DFS0 LRCK BICK SDTI Audio Data Interface DIF1 8X Interpolator ΔΣ Modulator SCF CTF LOUT 8X Interpolator ΔΣ Modulator SCF CTF ROUT DIF0 MS0280-J-01 2008/10 -1- [AK4386] ■ AK4386ET AK4386VT AKD4386 −20 ∼ +85°C −40 ∼ +85°C AK4386 16pin TSSOP (0.65mm pitch) 16pin TSSOP (0.65mm pitch) ■ MCLK 1 16 TEST BICK 2 15 DIF1 SDTI 3 14 VDD LRCK 4 13 VSS PDN 5 12 VCOM DFS0 6 11 LOUT DFS1 7 10 ROUT DEM 8 9 DIF0 Top View MS0280-J-01 2008/10 -2- [AK4386] No. Pin Name 1 MCLK 2 BICK 3 SDTI 4 LRCK I/O I I I I 5 PDN I 6 7 DFS0 DFS1 I I 8 DEM I 9 10 11 DIF0 ROUT LOUT I O O 12 VCOM O 13 14 15 VSS VDD DIF1 I 16 TEST I Function Master Clock Input Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin Input Channel Clock Pin Full Power Down Mode Pin “L” : Power down, “H” : Power up Sampling Speed Select 0 Pin Sampling Speed Select 1 Pin De-emphasis Filter Enable Pin “L” : OFF, “H” : ON (De-emphasis of fs=44.1kHz is enable.) Audio Interface Format 0 Pin Rch Analog Output Pin Lch Analog Output Pin Common Voltage Output Pin, 0.55 × VDD Normally connected to VSS with a 4.7μF (min. 1μF, max. 10μF) electrolytic capacitor. Ground Pin Power Supply Pin, 2.2 ∼ 3.6V Audio Interface Format 1 Pin Test Pin This pin should be connected to VDD. Note: All digital input pins should not be left floating. ■ Analog LOUT, ROUT MS0280-J-01 2008/10 -3- [AK4386] (VSS=0V; Note 1) Parameter Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Temperature (Powered applied) AK4386ET AK4386VT Storage Temperature Symbol VDD IIN VIND Ta Ta Tstg min −0.3 −0.3 −20 −40 −65 max 4.6 ±10 VDD+0.3 85 85 150 Units V mA V °C °C °C Note 1. : (VSS=0V; Note 1) Parameter Power Supply Symbol VDD min 2.2 typ 3.0 max 3.6 Units V Note 1. : MS0280-J-01 2008/10 -4- [AK4386] (Ta=25°C; VDD=3.0V; VSS=0V; fs=44.1kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 20Hz ∼ 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units Dynamic Characteristics: Resolution 24 Bits 0dBFS THD+N fs=44.1kHz −86 −76 dB −60dBFS BW=20kHz −37 dB 0dBFS fs=96kHz −84 dB −60dBFS BW=40kHz −34 dB DR (−60dBFS with A-weighted) 92 100 dB S/N (A-weighted) 92 100 dB Interchannel Isolation 80 100 dB DC Accuracy: Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 100 ppm/°C Output Voltage (Note 2) 1.85 2.0 2.15 Vpp Load Resistance (Note 3) 10 kΩ Load Capacitance 25 pF Power Supplies Power Supply Current Normal Operation (PDN pin = “H”, fs=44.1kHz) Normal Operation (PDN pin = “H”, fs=96kHz) Power Save mode (PDN pin = “H”, MCLK Stop) Full Power-down mode (PDN pin = “L”) Note 2. Note 3. AC Note 4. (Note 4) 9 10 2.5 50 mA mA mA μA Vout = 0.67 × VDD (typ) (0dB) VDD VDD 6 6.5 1.5 10 VSS MS0280-J-01 2008/10 -5- [AK4386] (Ta=25°C; VDD=2.2 ∼ 3.6V; fs=44.1kHz; DEM=OFF) Parameter Symbol DAC Digital Filter: Passband (Note 5) ±0.05dB PB −6.0dB Stopband (Note 5) SB Passband Ripple PR Stopband Attenuation SA Group Delay (Note 6) GD Digital Filter + SCF + CTF: FR Frequency Response 0 ∼ 20kHz 7) ∼ 40kHz (Note Note 5. Note 6. fs ( min typ max Units 0 24.1 22.05 20.0 - 64 - 24.0 - kHz kHz kHz dB dB 1/fs - ±0.5 ±1.0 - dB dB ±0.01 ) Note 7. fs=96kHz DC (Ta=25°C; VDD=2.2 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Symbol VIH VIL Iin MS0280-J-01 min 70%VDD - typ - max 30%VDD ±10 Units V V μA 2008/10 -6- [AK4386] (Ta=25°C; VDD=2.2 ∼ 3.6V) Parameter Master Clock Frequency Half Speed Mode (512/768/1024/1536fs) Normal Speed Mode (256/384/512/768fs) Double Speed Mode (128/192/256/384fs) Duty Cycle LRCK Frequency Half Speed Mode (DFS1-0 = “10”) Normal Speed Mode (DFS1-0 = “00”) Double Speed Mode (DFS1-0 = “01”) Duty Cycle Audio Interface Timing BICK Period Half Speed Mode Normal Speed Mode Double Speed Mode BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge LRCK Edge to BICK “↑” SDTI Hold Time SDTI Setup Time Power-Down & Reset Timing PDN Pulse Width Note 8. Note 9. AK4386 4.7μF VCOM pin DIF1-0 pin LRCK PDN pin = “L” VCOM pin tPD min. 19ms (Note 8) (Note 8) (Note 9) BICK Symbol min fCLK fCLK fCLK dCLK typ max Units 4.096 2.048 6.144 40 36.864 36.864 36.864 60 MHz MHz MHz % fsh fsn fsd dCLK 8 8 48 45 24 48 96 55 kHz kHz kHz % tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fs 1/128fs 1/64fs 70 70 40 40 40 40 ns ns ns ns ns ns ns ns ns tPD 4×C ms “↑” (C) tPD = 4 × C. 1μF ≤ C ≤ 10μF PDN pin MS0280-J-01 2008/10 -7- [AK4386] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL Audio Interface Timing tPD PDN VIL Power Down & Reset Timing MS0280-J-01 2008/10 -8- [AK4386] ■ AK4386 MCLK, BICK, LRCK MCLK MCLK LRCK Double speed MCLK Normal speed (PDN pin = “H”) MCLK MCLK LRCK ΔΣ (Table 1) Auto MCLK DFS1-0 pin Half speed (DFS1 pin = DFS0 pin = “H”) (Table 2) AK4386 VCOM MCLK (PDN pin = “L” → “H”) MCLK, LRCK DIF1-0 pin PDN pin Mode Normal Speed Double Speed Half Speed Auto DFS1 L L H H DFS0 fs L 8 ∼ 48kHz H 48 ∼ 96kHz L 8 ∼ 24kHz H 8 ∼ 96kHz Table 1. System Clock Example MCLK Frequency 512/768fs 128/192/256/384fs 1024/1536fs Sampling Speed Mode Normal Speed Double Speed Half Speed Table 2. Auto Mode MCLK Frequency 256/384/512/768fs 128/192/256/384fs 512/768/1024/1536fs Table 2 fs 8 ∼ 48kHz 48 ∼ 96kHz 8 ∼ 24kHz ■ 4 DIF1-0 pin 2’s BICK ≥ 48fs Mode 0 1 2 3 DIF1 L L H H (Table 3) BICK LSB “0” DIF0 SDTI Format L 16bit, LSB justified H 24bit, LSB justified L 24bit, MSB justified H 16/24bit, I2S Compatible Table 3. Audio Interface Format MS0280-J-01 MSB Mode 3 16 BICK = 32fs BICK ≥ 32fs ≥ 48fs ≥ 48fs ≥ 48fs or 32fs Figure Figure 1 Figure 2 Figure 3 Figure 4 2008/10 -9- [AK4386] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 0 1 2 3 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1 BICK(64fs) SDTI(i) Don't Care 15 14 13 12 1 0 Don't Care 15 14 13 12 2 1 0 SDTI-15:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 2 8 9 24 31 0 1 2 8 9 24 31 0 1 BICK(64fs) SDTI(i) Don't Care 23 1 0 8 Don't Care 8 23 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1 Timing LRCK 0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1 BICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing LRCK 0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1 BICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 3 Timing MS0280-J-01 2008/10 - 10 - [AK4386] ■ IIR fs=44.1kHz DEM pin = “H” Speed Mode (50/15μs ) Half Speed, Double OFF Mode DFS1 pin DFS0 pin DEM pin De-emphasis Filter L L L OFF Normal Speed L L H ON Double Speed L H * OFF Half Speed H L * OFF H H L OFF Auto H H H ON (Note) Table 4. De-emephasis Filter (*: Don’t care) Note. Normal speed fs=44.1kHz Half Speed, Double Speed Mode OFF ■ AK4386 PDN pin “L” AK4386 PDN pin = “L” DAC Hi-Z (PDN pin = “H”) VCOM “H” MCLK MCLK “L” Mode 0 1 2 PDN pin L H MCLK DAC Output Don’t care Hi-Z Supplied Normal Output Not Supplied VCOM Voltage Table 5. Power down mode MS0280-J-01 State Full Power Down Normal Power Save 2008/10 - 11 - [AK4386] (1) PDN pin PDN Internal State (1) Normal Operation Power-down D/A In (Digital) “0” data GD (2) GD (4) D/A Out (Analog) Clock In (2) (4) (3) (5) Don’t care MCLK, BICK, LRCK External MUTE Normal Operation (6) Mute ON Notes: (1) 19ms PDN pin “L” (VCOM pin VSS 4.7μF (2) (3) Hi-Z (4) PDN (“↑ ↓”) 3 ∼ 4LRCK “0” (5) (PDN pin = “L”) (6) (4) ) (GD) (MCLK, BICK, LRCK) Figure 5. Power-down/up sequence example 1 MS0280-J-01 2008/10 - 12 - [AK4386] (2) MCLK PDN pin (PDN pin = “H”) (1) Internal State Power-down D/A In (Digital) Power-down Normal Operation (2) GD (4) Hi-Z External MUTE (5) 19ms ) (6) PDN pin “L” (2) (3) (5) (6) (4) (5) MCLK Stop MCLK, BICK, LRCK MCLK (4) PDN pin VCOM (2) (4) Clock In Notes: (1) Normal Operation (3) GD D/A Out (Analog) Power-save (6) (VCOM pin VSS 4.7μF (GD) “0” (“↑”) MCLK “0” (MCLK ) (4) / 3 ∼ 4LRCK (BICK, LRCK) Figure 6. Power-down/up sequence example 2 MS0280-J-01 2008/10 - 13 - [AK4386] Figure 7 (AKD4386) Master Clock 1 MCLK TEST 64fs 2 BICK DIF1 15 24bit Audio Data 3 SDTI VDD 14 16 0.1u fs Reset & Power down Mode Setting Digital Ground + Analog Supply 2.2 to 3.6V 10u 4 LRCK VSS 13 5 PDN VCOM 12 6 DFS0 LOUT 11 Lch Out 7 DFS1 ROUT 10 Rch Out 8 DEM DIF0 9 AK4386 4.7u + (C) Analog Ground : - AK4386 VSS - LOUT/ROUT - VCOM 1μF - 10μF Figure 7. Typical Connection Diagram 1. VDD PC 2. VDD VSS VCOM 4.7μF VSS VCOM pin VCOM pin 3. AK4386 2.0Vpp(typ@VDD=3.0V) (SCF) ) 7FFFFFH(@24bit) 000000H(@24bit) VCOM ΔΣ (CTF) (0.55 × VDD) 2’s (2 800000H(@24bit) VCOM VCOM+ mV (0.55 × VDD) DC DC MS0280-J-01 2008/10 - 14 - [AK4386] 16pin TSSOP (Unit: mm) 5.0 16 1.10max 9 4.4 6.4±0.2 A 1 0.22±0.1 8 0.17±0.05 0.65 0.1±0.1 0.5±0.2 Detail A Seating Plane 0.10 0∼10° ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0280-J-01 2008/10 - 15 - [AK4386] (AK4386ET) AKM 4386ET XXYYY 1) 2) 3) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4386ET MS0280-J-01 2008/10 - 16 - [AK4386] (AK4386VT) AKM 4386VT XXYYY 4) 5) 6) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4386VT MS0280-J-01 2008/10 - 17 - [AK4386] Date (YY/MM/DD) 03/12/01 08/10/23 Revision 00 01 Reason Page Contents AK4386ET VT ET • • • • • • MS0280-J-01 2008/10 - 18 -