データシート

[AK4115]
AK4115
High Feature 192kHz 24bit Digital Audio Interface Transceiver
AK4115
216kHz, 24-bit
Dolby Digital
PLL
MPEG
Non-PCM
“Word Clock”
64pin LQFP
* Dolby Digital is a trademark of Dolby Laboratories.
† AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
† Very Low Jitter Analog PLL
† Synchronous / Asynchronous Mode
† Include Two X’tal Oscillators
† Clock Source: PLL or External Clock
- Reference Clock for PLL:
• Biphase signal: 22kHz to 216kHz
• External Clock (ELRCK pin): 22kHz to 216kHz
† 8-channel Receiver input
- One channel supports Differential Input
† 2-channel Transmission output (Through output or DIT)
- One channel supports Differential Output (RS422 Line Output Buffer)
† Auxiliary Digital Input
† De-emphasis for 32kHz, 44.1kHz and 48kHz
† Detection Functions
- Non-PCM Bit Stream Detection
- DTS-CD Bit Stream Detection
- Sampling Frequency Detection:
(22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz,
176.4kHz and 192kHz)
- Unlock & Parity Error Detection
- DAT Start ID Detection
† Up to 24bit Audio Data Format
† Audio Interface: Master or Slave Mode
† 192-bit Channel Status Buffer
† Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream
† Q-subcode Buffer for CD bit stream
† Serial μP Interface: 4-wire or I2C (max. 400kHz)
† Two Master Clock Outputs: 64fs/128fs/256fs/512fs
† Operating Voltage: 2.7 to 3.6V with 5V Logic Tolerance
† Package: 64pin LQFP
† Ta: -20 to 85°C
MS0573-J-01
2010/09
-1-
[AK4115]
XTI1
XTO1
AVSS AVDD R VCOM FILT
ACKS
XTI2
XTO2
X'tal
X'tal
Oscillator
Oscillator
PSEL
Clock
Recovery
Clock
Clock
MCKO1
Selector
Generator
MCKO2
RXP0
RXN0
DEM
RX1
8 to 3
DAIF
Input
Decoder
RX2
RX3
RX4
Audio I/F
for RX/TX
LRCK
BICK
SDTO
Selector
RX5
DAUX
RX6
RX7
ELRCK
TX0
EBICK
Audio I/F
for TX
TXP1
TXN1
ELRCK
EMCLK
ASYNC
DIT
Channel
Status
TVDD
TVSS
buffer
Q-subcode
buffer
DVDD
PDN
DVSS
CSN
OVDD
AC-3/MPEG
OVSS
Detect
XTL1
XTL0
VIN
B, C, U
Error &
STATUS
Detect
INT0
VOUT
INT1
µP I/F
CCLK
CDTO
CDTI
P/SN= “L” IIC
Figure 1. AK4115 Block Diagram in serial mode
MS0573-J-01
2010/09
-2-
[AK4115]
XTI1
XTO1
AVSS AVDD R VCOM FILT
XSEL
ACKS
XTI2
XTO2
X'tal
X'tal
Oscillator
Oscillator
PSEL
Clock
Recovery
Clock
Clock
MCKO1
Selector
Generator
MCKO2
RXP0
RXN0
4 to 2
RX1
Input
RX2
Selector
DEM
DAIF
Audio I/F
Decoder
RX3
for RX/TX
IPS0
LRCK
BICK
SDTO
DAUX
DIF0
DIF1
EBICK
ELRCK
TX0
EMCK
TXP1
TXN1
DIT
TVDD
TVSS
PDN
DVDD
DVSS
OCKS0
OVDD
AC-3/MPEG
OVSS
Detect
XTL1 XTL0
VIN
B,C,U,VOUT
OCKS1
Error &
CM0
STATUS
Detect
INT0
INT1
CM1
P/SN= “H”IPS1
Figure 2. AK4115 Block Diagram in parallel mode
MS0573-J-01
2010/09
-3-
[AK4115]
■
-20 ~ +85 °C
AK4115
AK4115VQ
AKD4115
64pin LQFP (0.5mm pitch)
RX3
AVSS
RX2
AVDD
RX1
AVSS
RXP0
RXN0
ACKS
P/SN
AVDD
VCOM
R
AVSS
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
63
62
IPS0/RX4
64
■
DIF0/RX5
1
48
FILT
TEST
2
47
XTL1
DIF1/RX6
3
46
XTL0
PDN
4
45
PSEL
XSEL/RX7
5
44
IPS1/IIC
DVDD
6
43
BVSS
VIN
7
42
DVSS
DAUX
8
41
DVDD
DVSS
9
40
OCKS0/CSN/CAD0
Top View
29
30
31
32
XTO2
OVDD
OVSS
EBICK
EMCK
28
33
XTI2
16
27
LRCK
XTO1
ELRCK
26
34
XTI1
15
25
SDTO
TVSS
INT0
24
35
TXN1
14
23
BICK
TXP1
INT1
22
CM0/CDTO/CAD1
36
TX0
37
13
21
12
OVSS
20
OVDD
TVDD
CM1/CDTI/SDA
19
38
U
11
VOUT
MCKO2
18
OCKS1/CCLK/SCL
C
39
17
10
B
MCKO1
MS0573-J-01
2010/09
-4-
[AK4115]
No.
Pin Name
DIF0
RX5
I/O
I
I
Function
Audio Data Interface Format #0 Pin in parallel mode
1
Receiver Channel #5 Pin in serial mode
(Internal biased pin)
TEST Pin
2
TEST
I
This pin must be connected to AVSS.
DIF1
I
Audio Data Interface Format #1 Pin in parallel mode
3
RX6
I
Receiver Channel #6 Pin in serial mode
(Internal biased pin)
Power-Down Mode Pin
4
PDN
I
When “L”, the AK4115 is powered-down and reset.
X’tal Oscillator Selection Pin in parallel mode
“L”: X’tal #1 is powered-up.
XSEL
I
5
“H”: X’tal #2 is powered-up.
XSEL pin and XSEL bit are ORed.
RX7
I
Receiver Channel #7 Pin in serial mode
(Internal biased pin)
6
DVDD
Digital Power Supply Pin, 3.3V
7
VIN
I
V-bit Input Pin for Transmitter Output
8
DAUX
I
Auxiliary Audio Data Input Pin
9
DVSS
Digital Ground Pin
10
MCKO1
O
Master Clock Output #1 Pin
11
MCKO2
O
Master Clock Output #2 Pin
12
OVDD
Digital Power Supply Pin, 3.3V
13
OVSS
Digital Ground Pin
14
BICK
I/O
Audio Serial Data Clock Pin
15
SDTO
O
Audio Serial Data Output Pin
16
LRCK
I/O
Channel Clock Pin
17
B
I/O
Block-Start Input/Output Pin
18
C
I/O
C-bit Input/Output Pin
19
U
I/O
U-bit Input/Output Pin
20
VOUT
O
V-bit Output Pin for Receiver
21
TVDD
Input tolerance & TX Output Buffer Power Supply Pin, 3.3V or 5V
22
TX0
O
Transmit Channel (Through Data) Output #0 Pin
23
TXP1
O
Transmit Channel Positive Output #1 Pin
24
TXN1
O
Transmit Channel Negative Output #1 Pin
25
TVSS
Input & TX Output Buffer Ground pin
26
XTI1
I
X’tal #1 Input Pin
27
XTO1
O
X’tal #1 Output Pin
28
XTI2
I
X’tal #2 Input Pin
29
XTO2
O
X’tal #2 Output Pin
30
OVDD
Digital Power Supply Pin, 3.3V
31
OVSS
Digital Ground Pin
32
EBICK
I/O
External Serial Data Clock Pin
33
EMCK
I
External Master Clock Input Pin
34
ELRCK
I/O
External Channel Clock Pin
35
INT0
O
Interrupt #0 Pin
36
INT1
O
Interrupt #1 Pin
Note 1. Do not allow digital input pins except internal biased pins to float.
MS0573-J-01
2010/09
-5-
[AK4115]
(
No.
Pin Name
CM0
CDTO
CAD1
CM1
CDTI
)
I/O
I
O
I
I
I
Function
Master Clock Operation Mode #0 Pin in parallel mode
37
Control Data Output Pin in serial mode, IIC pin = “L”.
Chip Address #1 Pin in serial mode, IIC pin = “H”.
Master Clock Operation Mode #1 Pin in parallel mode
Control Data Input Pin in serial mode, IIC pin = “L”.
38
Control Data Pin in serial mode, IIC pin = “H”.
SDA
I/O
An external pull-up resistor is required.
OCKS1
I
Output Clock Select #1 Pin in parallel mode
CCLK
I
Control Data Clock Pin in serial mode, IIC pin = “L”
39
Control Data Clock Pin in serial mode, IIC pin = “H”
SCL
I
An external pull-up resistor is required.
OCKS0
I
Output Clock Select #0 Pin in parallel mode
40
CSN
I
Chip Select Pin in serial mode, IIC pin = “L”.
CAD0
I
Chip Address #0 Pin in serial mode, IIC pin = “H”.
41
DVDD
Digital Power Supply Pin, 3.3V
42
DVSS
Digital Ground Pin
43
BVSS
Substrate Ground Pin
IPS1
I
Input Channel Select #1 Pin in parallel mode
44
IIC Select Pin in serial mode
IIC
I
“L”: 4-wire Serial, “H”: I2C
PLL Source Select Pin
45
PSEL
I
“L”: S/PDIF Input, “H”: ELRCK Input Clock
PSEL pin and PSEL bit are ORed in serial mode.
46
XTL0
I
X’tal Frequency Select #0 Pin
47
XTL1
I
X’tal Frequency Select #1 Pin
48
FILT
O
PLL Loop Filter Pin
49
AVSS
Analog Ground Pin
External Resistor Pin
50
R
O
10kΩ ±1% resistor should be connected to AVSS externally.
Common Voltage Output Pin
51
VCOM
O
4.7µF capacitor should be connected to AVSS externally.
52
AVDD
Analog Power Supply Pin, 3.3V
Parallel/Serial Select Pin
53
P/SN
I
“L”: Serial Mode, “H”: Parallel Mode
Master Clock Frequency Auto Setting Mode Pin.
54
ACKS
I
“L”: Disable, “H”: Enable
ACKS pin and ACKS bit are ORed in serial mode.
Receiver Channel #0 Negative Input Pin
(Internal biased pin)
55
RXN0
I
In serial mode, this channel is selected as default channel.
Receiver Channel #0 Positive Input Pin
(Internal biased pin)
56
RXP0
I
In serial mode, this channel is selected as default channel.
57
AVSS
Analog Ground Pin
58
RX1
I
Receiver Channel #1 Pin
(Internal biased pin)
59
AVDD
Analog Power Supply Pin, 3.3V
60
RX2
I
Receiver Channel #2 Pin
(Internal biased pin)
61
AVSS
Analog Ground Pin
62
RX3
I
Receiver Channel #3 Pin
(Internal biased pin)
63
AVDD
Analog Power Supply Pin, 3.3V
IPS0
I
Input Channel Select #0 Pin in parallel mode
64
RX4
I
Receiver Channel #4 Pin in serial mode
(Internal biased pin)
Note 1. Do not allow digital input pins except internal biased pins to float.
MS0573-J-01
2010/09
-6-
[AK4115]
■
1. Serial Mode (P/SN pin = “L”)
Classification
Analog Input
Analog Output
Digital Input
Digital Output
Digital
Input/Output
Pin Name
RXP0, RXN0, RX7-1
TEST
FILT
VIN, DAUX, XTI1, XTI2, EMCK
MCKO1, MCKO2, VOUT, TX0,
TXP1, TXN1, XTO1, XTO2,
INT0, INT1,
CDTO (IIC pin = “L”)
B, U, C
EBICK, ELRCK
Setting
AVSS
DVSS
BCU_IC bit = “1”:
BCU_IO bit = “0”: DVSS
:
: DVSS
2. Parallel Mode (P/SN pin = “H”)
Classification
Analog Input
Analog Output
Digital Input
Digital Output
Pin Name
Setting
RXP0, RXN0, RX3-1
TEST
AVSS
FILT
VIN, DAUX, XTI1, XTI2, EMCK,
DVSS
EBICK, ELRCK
MCKO1, MCKO2, VOUT, TX0,
TXP1, TXN1, XTO1, XTO2,
INT0, INT1, B, U, C
MS0573-J-01
2010/09
-7-
[AK4115]
(AVSS=OVSS=DVSS=TVSS=BVSS=0V; Note 2)
Parameter
Power Supplies: Analog
Digital
Logic Output Buffer
Input tolerance and TX Buffer
Symbol
AVDD
DVDD
OVDD
TVDD
| BVSS - AVSS | (Note 3)
ΔGND1
| BVSS - OVSS | (Note 3)
ΔGND2
| BVSS - DVSS | (Note 3)
ΔGND3
| BVSS - TVSS | (Note 3)
ΔGND4
Input Current (Any pins except supplies)
IIN
Input Voltage (Note 4)
VIN
Ambient Temperature (Power applied)
Ta
Storage Temperature
Tstg
Note 2.
Note 3. AVSS, OVSS, DVSS, BVSS, TVSS
Note 4.
“TVDD+0.3V”
6.0V
SCL, SDA pin
(TVDD+0.3V)
(AVSS=OVSS=DVSS=TVSS=BVSS=0V; Note 2)
Parameter
Symbol
Power
Analog
AVDD
Supplies:
Digital
DVDD
(Note 5)
Logic Output Buffer
OVDD
Input tolerance and TX Buffer
TVDD
Difference
AVDD – DVDD
AVDD – OVDD
OVDD – DVDD
Note 2.
Note 5. AVDD, DVDD, OVDD, TVDD
min
-0.3
-0.3
-0.3
-0.3
max
4.6
4.6
4.6
6.0
Units
V
V
V
V
-0.3
-20
-65
0.3
0.3
0.3
0.3
±10
“TVDD+0.3” or 6.0
85
150
V
V
V
V
mA
V
°C
°C
min
2.7
2.7
2.7
DVDD
-0.3
-0.3
-0.3
typ
3.3
3.3
3.3
5.0
0
0
0
max
3.6
3.6
3.6
5.5
0.3
0.3
0.3
Units
V
V
V
V
V
V
V
:
MS0573-J-01
2010/09
-8-
[AK4115]
S/PDIF
(Ta=25°C; AVDD=OVDD=DVDD=2.7~3.6V; TVDD=2.7~5.5V)
Parameter
Symbol
Input Resistance
Zin
Input Voltage
VTH
Input Sample Frequency
fs
Time deviation Jitter
RX input (PSEL = “0”)
ELRCK input (PSEL = “1”)
Cycle - to - Cycle Jitter
RX input (PSEL = “0”)
ELRCK input (PSEL = “1”)
min
200
22
typ
10
-
max
216
Units
kΩ
mVpp
kHz
-
100
300
-
ps RMS
ps RMS
-
70
70
-
ps RMS
ps RMS
DC
(Ta=25°C; AVDD=OVDD=DVDD=2.7~3.6V; TVDD=2.7~5.5V; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
Power Supply Current
Normal operation: PDN pin = “H” (Note 6)
AVDD+DVDD+OVDD:
28
42
mA
TVDD:
30
45
mA
Power down:
PDN pin = “L” (Note 7)
AVDD+DVDD+OVDD+TVDD:
10
100
μA
High-Level Input Voltage
VIH
70%DVDD
TVDD
V
Low-Level Input Voltage
VIL
DVSS-0.3
30%DVDD
V
Input Level at AC coupling (Only ELRCK pin)
VAC
0.5
TVDD
Vpp
Except for TX0, TXN1 and TXP1 pins
VOH
OVDD-0.4
V
High-Level Output Voltage
(Iout=-400μA)
Low-Level Output Voltage
VOL
0.4
V
(Except SDA pin: Iout=400μA)
VOL
0.4
V
(
SDA pin: Iout= 3mA)
TX0 Output Level
Output Level (Note 8)
VTXO0
0.4
0.5
0.6
V
TXN1 and TXP1 pins
Professional mode
(TVDD= 4.5 ~ 5.5V)
RTXPN
88
110
132
Output Impedance (Rp + Rn + R1) (Note 9)
Ω
Consumer Mode
(TVDD = 2.7 ~ 5.5V)
VTXO1
0.4
0.5
0.6
V
Output Level (Note 10)
Input Leakage Current
Iin
± 10
μA
Note 6. AVDD, OVDD, DVDD = 3.3V, TVDD=5.0V, CL=20pF, fs=216kHz, X'tal=24.576MHz, Clock Operation Mode 2,
OCKS1=1, OCKS0=1, TX0
: Figure 23, TX1
: Figure 25
AVDD=10mA (typ), OVDD+DVDD=18mA (typ)
Note 7. RX
TVDD
DVSS
Note 8. Figure 23
Figure 24
Note 9. Rp: TXP1
, Rn: TXN1
, R1 = 75Ω Figure 25
Note 10. Figure 26
MS0573-J-01
2010/09
-9-
[AK4115]
(Ta=25°C; AVDD=OVDD=DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Crystal Resonator
Frequency
fXTAL
11.2896
External Clock
Frequency
fECLK
11.2896
Duty
dECLK
40
MCKO1 Output
Frequency
fMCK1
2.816
Duty
dMCK1
40
MCKO2 Output
Frequency
fMCK2
1.408
Duty
dMCK2
40
PLL Clock Recover Frequency (RX7-0)
fpll
22
LRCK Frequency
fs
22
Duty Cycle (at Slave Mode)
dLCK
45
Duty Cycle (at Master Mode)
dLCK
Audio Interface Timing 1
Slave Mode
BICK Period
tBCK
72
BICK Pulse Width Low
tBCKL
27
Pulse Width High
tBCKH
27
tLRB
15
LRCK Edge to BICK “↑” (Note 11)
tBLR
15
BICK “↑” to LRCK Edge (Note 11)
tLRM
LRCK to SDTO (MSB) (3.0 ≤ DVDD,OVDD ≤ 3.6V)
tBSD
BICK “↓” to SDTO
(3.0 ≤ DVDD,OVDD ≤ 3.6V)
tLRM
LRCK to SDTO (MSB) (2.7 ≤ DVDD,OVDD < 3.0V)
tBSD
BICK “↓” to SDTO
(2.7 ≤ DVDD,OVDD < 3.0V)
tDXH
15
DAUX Hold Time
tDXS
15
DAUX Setup Time
Master Mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
DAUX Hold Time
DAUX Setup Time
Master Clock Timing 2
EMCK
ELRCK
Frequency
Duty
PLL Lock Range
Frequency
Duty
Audio Interface Timing 2
Slave Mode
EBICK Period
EBICK Pulse Width Low
Pulse Width High
ELRCK Edge to BICK “↑”
EBICK “↑” to ELRCK Edge
DAUX Hold Time
DAUX Setup Time
Master Mode
EBICK Frequency
EBICK Duty
EBICK “↓” to ELRCK
DAUX Hold Time
DAUX Setup Time
Note 11.
LRCK
Note 12.
ELRCK
(Note 12)
(Note 12)
typ
max
Units
50
50
50
50
24.576
27.648
60
27.648
60
27.648
60
216
216
55
-
MHz
MHz
%
MHz
%
MHz
%
kHz
kHz
%
%
-
20
20
25
25
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fBCK
dBCK
tMBLR
tBSD
tDXH
tDXS
-15
15
15
64fs
50
-
15
15
-
Hz
%
ns
ns
ns
ns
fECLK2
dECLK2
fEPLL
fs
dLCK
2.816
40
22
22
40
50
50
27.648
60
216
216
60
MHz
%
kHz
kHz
%
tEBCK
tEBCKL
tEBCKH
tELRB
tEBLR
tEDXH
tEDXS
72
27
27
15
15
15
15
-
-
ns
ns
ns
ns
ns
ns
ns
fEBCK
dEBCK
tEMBLR
tEDXH
tEDXS
-15
15
15
64fs
50
-
15
-
Hz
%
ns
ns
ns
BICK
EBICK
MS0573-J-01
2010/09
- 10 -
[AK4115]
(
)
(Ta=25°C; AVDD=OVDD=DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF)
Parameter
Symbol
Control Interface Timing (4-wire serial mode)
CCLK Period
tCCK
CCLK Pulse Width Low
tCCKL
Pulse Width High
tCCKH
CDTI Setup Time
tCDS
CDTI Hold Time
tCDH
CSN “H” Time
tCSW
tCSS
CSN “↓” to CCLK “↑”
tCSH
CCLK “↑” to CSN “↑”
tDCD
CDTO Delay
tCCZ
CSN “↑” to CDTO Hi-Z
2
Control Interface Timing (I C Bus mode):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
Clock Low Time
tLOW
Clock High Time
tHIGH
Setup Time for Repeated Start Condition
tSU:STA
SDA Hold Time from SCL Falling
(Note 13)
tHD:DAT
SDA Setup Time from SCL Rising
tSU:DAT
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
Capacitive load on bus
Cb
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
Reset Timing
PDN Pulse Width
tPW
Note 13.
300ns (SCL
)
Note 14. I2C-bus NXP B.V.
MS0573-J-01
min
typ
max
Units
200
80
80
50
50
150
50
50
-
-
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
150
-
-
ns
2010/09
- 11 -
[AK4115]
■
1/fECLK
VIH
XTI
VIL
tECLKH
tECLKL
dECLK = tECLKH x fECLK x 100
= tECLKL x fECLK x 100
1/fMCK1
MCKO1
50%OVDD
tMCKH1
tMCKL1
dMCK1 = tMCKH1 x fMCK1 x 100
= tMCKL1 x fMCK1 x 100
1/fMCK2
MCKO2
50%OVDD
tMCKH2
tMCKL2
dMCK2 = tMCKH2 x fMCK2 x 100
= tMCKL2 x fMCK2 x 100
1/fs
VIH
LRCK
VIL
tLRH
tLRL
dLCK = tLRH x fs x 100
= tLRL x fs x 100
1/fECLK2
VIH
EMCK
VIL
tECLKH2
tECLKL2
dECLK2 = tECLKH2 x fECLK2 x 100
= tECLKL2 x fECLK2 x 100
1/fs
VIH
ELRCK
VIL
tELRH
tELRL
dELCK = tELRH x fs x 100
= tELRL x fs x 100
Figure 3. Clock Timing
MS0573-J-01
2010/09
- 12 -
[AK4115]
VIH
LRCK
VIL
tBCK
tBLR
tLRB
tBCKL
tBCKH
VIH
BICK
VIL
tLRM
tBSD
50%OVDD
SDTO
tDXS
tDXH
VIH
DAUX
VIL
Figure 4. Serial Interface Timing 1 (Slave Mode)
50%OVDD
LRCK
tMBLR
50%OVDD
BICK
tBSD
50%OVDD
SDTO
tDXS
tDXH
VIH
DAUX
VIL
Figure 5. Serial Interface Timing 1 (Master Mode)
VIH
ELRCK
VIL
tEBCK
tEBLR
tELRB
tEBCKL
tEBCKH
VIH
EBICK
VIL
tEDXS
tEDXH
VIH
DAUX
VIL
Figure 6. Serial Interface Timing 2 (Slave Mode)
MS0573-J-01
2010/09
- 13 -
[AK4115]
ELRCK
50%OVDD
tEMBLR
50%OVDD
EBICK
tEDXS
tEDXH
VIH
DAUX
VIL
Figure 7. Serial Interface Timing 2 (Master Mode)
VIH
CSN
VIL
tCSS
tCCK
tCCKL tCCKH
VIH
CCLK
VIL
tCDH
tCDS
CDTI
C1
C0
0
0
VIH
VIL
Hi-Z
CDTO
Figure 8. WRITE/READ Command Input Timing in 4-wire serial mode
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
CDTO
VIL
D3
D2
D1
D0
VIH
VIL
Hi-Z
Figure 9. WRITE Data Input Timing in 4-wire serial mode
MS0573-J-01
2010/09
- 14 -
[AK4115]
VIH
CSN
VIL
VIH
CCLK
VIL
A1
CDTI
VIH
A0
VIL
tDCD
Hi-Z
CDTO
D7
D6
D5
50%OVDD
Figure 10. READ Data Output Timing 1 in 4-wire serial mode
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D3
D2
D1
D0
50%OVDD
Figure 11. READ Data Input Timing 2 in 4-wire serial mode
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 12. I2C Bus mode Timing
tPW
PDN
VIL
Figure 13. Power Down & Reset Timing
MS0573-J-01
2010/09
- 15 -
[AK4115]
■ Non-PCM (Dolby Digital, MPEG, etc) / DTS-CD
AK4115 Non-PCM
Dolby “Dolby Digital Data Stream in IEC60958
Interface”
32
Mode Non-PCM
NPCM bit
“1”
96
sync code 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F
NPCM bit
“1”
4096
4096
sync code
NPCM bit = “0”
sync code
NPCM bit
“0”
sync code
2
(Pc: burst information, Pd: length code: Figure 51,
Figure 52
)
DTS-CD
DTSCD bit
“1”
4096
sync code
DTSCD bit = “0”
sync
code
DTSCD bit
“0”
NPCM bit DTSCD bit OR AUTO bit
AK4115 DTS-CD
14bit Sync Word, 16bit Sync Word
DTS14 bit, DTS16 bit
ON/OFF
AUTO bit
AUDION bit OR INT1 pin
DTS-CD
14bit Sync Word, 16bit Sync Word
■ 216kHz
PLL 22kHz
216kHz
XTL1-0
(22.05kHz,
24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
■ PLL
PLL
ELRCK pin
RX7-0 pin
PSEL pin
“Word Clock”
PSEL bit PSEL pin
ELRCK pin
(1fs)
OR
PSEL bit
PSEL
Reference Clock for PLL
0
RX Input
1
ELRCK Input
Table 1. Setting of PLL Reference Clock
Default
■ PLL
PLL
FAST bit
PSEL = “1”
PSEL = “0”
(fs)
FAST bit
max. 15ms(VCOM pin
4.7μF
FAST bit
max.35ms
Table 2
PDN pin: “L” Æ “H”
)
PSEL
FAST bit
PLL Lock Time
0
0
≤ (20ms + 384/fs)
0
1
≤ (20ms + 1/fs)
1
≤ 35ms
Table 2. PLL Lock Time (fs: Sampling Frequency)
MS0573-J-01
Table 2
FAST bit = “1”
VCOM
VCOM
Default
2010/09
- 16 -
[AK4115]
■ Word Clock (Studio Sync Clock)
Word Clock
PLL
ELRCK pin
216kHz
(1fs)
MCLK BICK
LRCK
AC
Word Clock (ELRCK pin)
ELRCK pin
LRCK pin
Word Clock (ELRCK)
LRCK ELRCK
(WSYNC bit = “1”)
Word Clock (ELRCK)
PLL
0.5Vpp(min)
±5%
22kHz
±1/(128fs)
WSYNC bit “0”
■ DIT/DIR Mode
AK4115
DIT DIR
DIT DIR
ASYNC bit
1.
: ASYNC bit = “0”
PSEL
CM1-0
SDTO
PLL
X'tal
RX
Mode -6
BICK
LRCK PLL
Mode2
Mode3
Mode2-3
X'tal
PLL
SDTO
Mode
PSEL
CM1
CM0
UNLOCK
PLL Status
0
0
0
0
-
ON
1
0
0
1
-
OFF
X'tal Status
ON
(Note 16)
ON
2
0
1
0
0
ON
ON
3
0
1
1
1
-
ON
ON
4
1
0
0
-
ON
5
1
0
1
-
OFF
ON
ON
ON
(Note 16)
ON
6
1
1
0
0
ON
ON
PLL UNLOCK
X’tal
PLL
ELRCK
DAUX
Clock source
PLL
(RX)
X'tal
PLL
(RX)
X'tal
X’tal
PLL
(ELRCK)
X’tal
PLL
(ELRCK)
X'tal
1
ON
ON
Note 15. ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note 16. X’tal fs
(XTL1,0= “1,1”) X’tal
Note 17. MCKO1/2, BICK, LRCK
Table 3. Clock operation for DIT/DIR in synchronous mode
MS0573-J-01
MCKO1/2
Clock I/O
SDTO
Note 17
RX
Note 17
DAUX
Note 17
RX
Note 17
Note 17
DAUX
DAUX
Note 17
DAUX
Note 17
DAUX
Note 17
DAUX
Note 17
DAUX
OFF
2010/09
- 17 -
[AK4115]
XTI1
XTO1
X'tal
ACKS
XTI2
XTO2
X'tal
XSEL
Oscillator
Oscillator
Clock
Recovery
Clock Selector
Clock
MCKO1
(CM1-0)
Generator
MCKO2
RXP0
RXN0
RX1
DEM
8 to 3
DAIF
Input
Decoder
RX2
RX3
RX4
LRCK
Audio I/F
BICK
for RX/TX
SDTO
Selector
RX5
DAUX
RX6
RX7
TX0
TXP1
TXN1
DIT
Figure 14. Clocks for DIT/DIR in synchronous mode (PSEL bit = “0”)
XTI1
XTO1
X'tal
ACKS
XSEL
XTO2
X'tal
Oscillator
Oscillator
Clock
Recovery
XTI2
Clock Selector
Clock
MCKO1
(CM1-0)
Generator
MCKO2
RXP0
RXN0
RX1
8 to 2
Audio I/F
Input
for RX/TX
RX2
RX3
RX4
LRCK
BICK
SDTO
Selector
RX5
DAUX
RX6
RX7
ELRCK
TX0
TXP1
TXN1
DIT
Figure 15. Clocks for DIT/DIR in synchronous mode (PSEL bit = “1”)
MS0573-J-01
2010/09
- 18 -
[AK4115]
2.
: ASYNC bit = “1”, PSEL = “0”
ASYNC bit 1
SDTO
“L”
MSEL bit
DIT DIR
DAUX
X'tal EMCK
Mode 1 Mode 2(PLL Unlock
ELRCK EBCIK
(See Table 4)
)
TX
Mode3
MSEL bit
Master Clock
0
X’tal
Defalut
1
EMCK
Table 4. Master clock setting for TX in asynchronous mode.
RX
Clock
I/O
TX
Mode
CM1
CM0
UNLOCK
PLL
Status
X'tal
Status
0
0
0
-
ON
ON
(Note 19)
PLL
(RX)
Note 20
RX
1
0
1
-
OFF
ON
X'tal
Note 20
“L”
0
ON
ON
PLL
(RX)
Note 20
RX
1
ON
ON
X'tal
Note 20
“L”
-
ON
ON
X'tal
Note 20
“L”
2
1
3
1
Clock
Source
SDTO
0
1
Clock
Source
X’tal
or
EMCK
(Note 22)
X’tal
or
EMCK
X’tal
or
EMCK
X’tal
or
EMCK
X’tal
or
EMCK
Note 18. ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note 19 X’tal fs
(XTL1,0= “1,1”) X’tal
Note 20: MCKO1/2, BICK, LRCK
Note 21. EMCK or X’tal, EBICK, ELRCK, DAUX
Note 22. X’tal OFF
EMCK
Table 5. Clock operation for DIT/DIR in asynchronous mode
XTI1
XTO1
X'tal
ACKS
Note 21
Note 21
Note 21
Note 21
Note 21
OFF
XTI2
XTO2
X'tal
XSEL
Oscillator
Oscillator
Clock
Recovery
Clock
I/O
Clock Selector
Clock
MCKO1
(CM1-0)
Generator
MCKO2
RXP0
RXN0
RX1
DEM
8 to 3
DAIF
Input
Decoder
RX2
RX3
RX4
Audio I/F
for RX
“L”
Selector
RX5
LRCK
BICK
SDTO
MSEL
RX6
EMCK
RX7
Audio I/F
TX0
for TX
TXP1
TXN1
ELRCK
EBICK
DAUX
DIT
Figure 16. Clocks for DIT/DIR in asynchronous mode
MS0573-J-01
2010/09
- 19 -
[AK4115]
■ Block start, Channel status bit, User bit and Validity bit
RX
TX
B, C, U pin I/O
BCU_IO bit
a.
& AES
Block
ASYNC BCU_IO
Start
bit
bit
(B pin)
0
Input
1
Output
0
Input
1
Output
0
1
Note 23. RX
Note 24. RX
Note 25. C pin
CR191-0 bit
Note 26. VIN pin VTX bit
Note 27. UDIT bit “1”
,
B, C, U, VOUT pin
“L” (BCU_IO bit = “1”)
Mode2 UNLOCK
(P/SN pin = “L”, AES3 bit = “0”)
RX
Channel
Validity
User bit
Status bit
bit
VOUT pin
CR191-0 bits
N/A
VRX bit
(Note 24)
VRX bit
C pin
U pin
VOUT pin
CR191-0 bits
(Note 24)
(Note 23)
Channel
Status bit
C pin
CT191-0 bits
(Note 25)
CT191-0 bits
All
“0” data
(Note 27)
CR191-0 bits
C pin
CT191-0 bits
(Note 25)
U pin
N/A
VRX bit
TX
VOUT pin
C pin
U pin
VRX bit
CT191-0 bits
CR191-0 bits
(Note 24)
(Note 23)
C pin CR191-0 bit
VOUT pin VRX bit
OR
OR
U bit DIT(U bit DIR-DIT loop mode)
User bit
U pin
All
“0” data
Validity
bit
VIN pin
VTX bit
(Note 26)
VIN pin
VTX bit
(Note 26)
VIN pin
VTX bit
(Note 26)
VTX bit
Table 6. Block start, Channel Status bit, User bit and Validity bit in serial mode except AES3 mode (N/A: Not available)
MS0573-J-01
2010/09
- 20 -
[AK4115]
b.
DIF1
bit
BCU_IO
bit
AES3
Block
Start
(B pin)
0
Input
1
Output
0
Input
1
Output
0
1
Note 28. RX
Note 29. RX
Note 30. RX
Note 31. RX
Note 32. C pin
Note 33. TX
Note 34. VIN pin
Note 35. UDIT bit
CT191-0 bit
(P/SN pin = “L”, AES3 bit = “1”, ASYNC bit = “0”)
RX
TX
Channel
Validity
Channel
User bit
User bit
Status bit
bit
Status bit
VOUT pin
CR191-0 bits
C pin
VRX bit
SDTO pin
U pin
SDTO pin
CT191-0 bits
SDTO pin
(Note 28)
(Note 32)
(Note 31)
C pin
VOUT pin
All “0”
U pin
CR191-0 bits
VRX bit
CT191-0 bits
data
SDTO pin
SDTO pin
SDTO pin
(Note 35)
(Note 30)
(Note 29)
(Note 31)
VOUT pin
CR191-0 bits
CT191-0 bits
VRX bit
DAUX
SDTO pin
SDTO pin
DAUX pin
pin
SDTO pin
(Note 28)
(Note 33)
(Note 31)
C pin
VOUT pin
U pin
CT191-0 bits
DAUX
CR191-0 bits
VRX bit
SDTO pin
DAUX pin
pin
SDTO pin
SDTO pin
(Note 30)
(Note 33)
(Note 29)
(Note 31)
CR191-0 bit
SDTO pin
C pin
SDTO pin
CR191-0 bit
U pin SDTO pin
VOUT pin VRX bit
SDTO pin
OR
CTX bit
CT191-0 bit
DAUX pin
VTX bit
“1”
,
Validity
bit
VIN pin
VTX bit
(Note 34)
VIN pin
VTX bit
(Note 34)
DAUX
pin
DAUX
pin
OR
U bit
DIT(U bit
DIR-DIT loop mode)
Table 7. Block start, Channel Status bit, User bit and Validity bit in serial mode & AES3 mode
c.
(P/SN pin = “H”)
Block
Start
(B pin)
Output
RX
Channel
Status bit
User bit
TX
Validity bit
Channel Status bit
User bit
Validity
bit
Default value of
All
VIN pin
CT191-0 bits
“0” data
Table 8. Block start, Channel Status bit, User bit and Validity bit in parallel mode
C pin
U pin
VOUT pin
MS0573-J-01
2010/09
- 21 -
[AK4115]
1.
1-1. RX
CR191-0 bit
C pin
BCU_IO bit = “1”
AES3
SDTO
1-2. TX
CT191-0 bit
C pin
AES3
Pro
C pin
C pin
(bit0 = “1”)
CCRE bit “0”
(bit0 = “0”)
CTX bit = “0”
CTX bit = “1”
CCRE bit
CRC
CRC
“1”
BCU_IO = “0”
OR
CT191-0 bit
CRC
pin
CT191-0 bit
AES3
CT191-0 bit
TX
(bit0 = “0”)
bit20-23(audio channel)
CT20 bit
CT20 bit = “1”
AK4115 “Stereo mode”
bit20-23 Sub-frame1
“1000” (Lch.)
Sub-frame2
“0100”(Rch.)
CT20 bit
“0”
bit20-23
Sub-frame1
Sub-frame2
“0000”
CTRAN bit
“0”
“1”
CR191-0 bit
CT191-0 bit
CT191-0 bit
CTRAN bit
“0”
CTRAN bit = “1”
CT191-0 bit
2.
2-1. RX
BCU_IO bit
AES3
“1”
U pin
SDTO
2-2. TX
BCU_IO bit
“0”
ASYNC bit = “0” (
)
“0”
loop-back mode)
DAUX pin
U pin
UDIT bit
“1”
UDIT bit
PLL
MS0573-J-01
U bit
BCU_IO bit = “1”
UDIT bit
“0”
DIT(U bit DIR-DIT
AES3
U pin
2010/09
- 22 -
[AK4115]
3.
3-1. RX
VRX bit
VOUT pin
AES3
VOUT pin
“L”
SDTO
VRX bit
3-2. TX
VIN pin
VTX bit
Sub-frame
VIN pin
VTX bit
OR
LRCK
VIN pin
BCU_IO bit = “0”
BCU_IO bit
AES3
“1”
VIN pin
VIN pin
VXT bit
DAUX pin
4.
LRCK
ELRCK
(BCU_IO bit = “0”)
(BCU_IO bit = “1”)
39
“H”
0 “H”
“H”
AES3
B pin
DAUX pin
B (Input)
B bit
Don’t care
Don’t care
B (Output)
C (or U,V)
C(R191) C(L0)
C(R0)
C(L1)
C(L38)
C(R39) C(L40)
R0
L1
L38
R39
LRCK(ELRCK)
(Except I2S)
LRCK(ELRCK)
(I2S)
SDTO (DAUX)
R191
L0
L40
Figure 17. B, C, U, V Input/output timings
MS0573-J-01
2010/09
- 23 -
[AK4115]
■
AK4115
bit
2
(MCKO1 pin and MCKO2 pin)
MCKO2 pin
XMCK
2
1) XMCK bit = “0”
PLL
(Table 9)
OCKS1-0
X'tal
(MCKO1 pin, MCKO2 pin)
X’tal
256fs
192kHz
96kHz
512fs
OCKS0
0
1
0
1
MCKO1 pin MCKO2 pin
X’tal
256fs
256fs
256fs
256fs
128fs
256fs
512fs
256fs
512fs
128fs
64fs
128fs
Table 9. Master Clock Output Frequency
fs
256fs,512fs
128fs
No.
0
1
2
3
OCKS1
0
0
1
1
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
Default
2) XMCK bit = “1”
MCKO2 pin
CM1-0 bit, OCKS1-0 bit
DIV bit
XTI pin
MCKO1 pin
CM1-0 bit, OCKS1-0 bit
XMCK bit DIV bit MCKO2 Clock Source
MCKO2 Frequency
1
0
X’tal (Note 36)
x1
1
1
X’tal (Note 36)
x 1/2
Note 36. MCKO2
XSEL bit
Table 10. Select output frequency of MCKO2
■ Master Clock Auto Setting Mode
Master Clock Auto Setting Mode
ACKS “1”
OCKS1-0
MCLK/LRCK
ACKS pin
OR
PLL
X'tal
ACKS bit
MCKO1 MCKO2
(RX
ELRCK)
MCKO1/MCKO2
Table 11
OCKS1-0
Mode
MCKO1
MCKO2
Sampling Frequency Range
Normal Speed
512fs
256fs
22kHz to 48kHz
Double Speed
256fs
128fs
64kHz to 96kHz
Quad Speed
128fs
64fs
176.4kHz to 216kHz
Table 11. Master Clock Frequency Select (Master Clock Auto Setting Mode)
MS0573-J-01
2010/09
- 24 -
[AK4115]
■ X’tal
AK4115
2
XSEL bit
X’tal
2
X’tal
XSEL pin
XSEL
0
1
Status
X’tal #1
X’tal #2
Power-Up
Power-Down
Power-Down
Power-Up
Table 12. Setting of X’tal oscillator
AK4115 XTI1/2 pin
1) X’tal
XTI1/2
AK4115
XTO1/2
Note:
(typ. 5-10pF)
Figure 18. X’tal mode
2)
XTI1/2
External Clock
AK4115
XTO1/2
Figure 19. External clock mode
3) XTI/XTO
(Clock Operation Mode 0)
XTI1/2
AK4115
XTO1/2
Figure 20. OFF mode
MS0573-J-01
2010/09
- 25 -
[AK4115]
■
AK4115
1. X’tal
2.
XTL1,0 pin
2
RX
XTL1, 0 = “1,1”
FS3-0 bit
XTL1
X’tal Frequency
X’tal #1
X’tal #2
0
11.2896MHz
12.288MHz
1
12.288MHz
11.2896MHz
0
24.576MHz
22.5792MHz
1
(Use channel status)
(Use channel status)
Table 13. Reference X’tal frequency
XTL0
0
0
1
1
Except XTL1, 0 = “1,1”
Register output
fs
FS3
0
0
0
0
0
0
1
1
1
1
1
FS2
0
0
0
0
1
1
0
0
0
1
1
Note 37:
FS1
FS0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
0
0
0
±3%
FS3-0 bit
Note 38:
Note 39.
Clock comparison
(Note 37)
44.1kHz ± 3%
48kHz ± 3%
32kHz ± 3%
22.05kHz ± 3%
24kHz ± 3%
64kHz ± 3%
88.2kHz ± 3%
96kHz ± 3%
176.4kHz ± 3%
192kHz ± 3%
Table 14
192kHz +3%
“0001”, “0101”, “0111”, “1001”
Byte3 Bit3-0 FS3-0 bits
Table 14
44.1kHz
Reserved
48kHz
32kHz
22.05kHz
24kHz
64kHz
88.2kHz
96kHz
176.4kHz
192kHz
Default
XTL1, 0 = “1, 1”
Consumer
mode
(Note 38)
Byte3
Bit3,2,1,0
0000
0001
0010
0011
0100
0110
1000
1010
1100
1110
Professional mode
(Note 39)
Byte0
Bit7,6
01
10
11
00
00
00
00
00
00
Byte4
Bit6,5,4,3
0000
(Others)
0000
0000
1001
0001
1010
0010
1011
0011
22.05kHz -3%
FS3-0 bits = “0001”
Table 14.
MS0573-J-01
2010/09
- 26 -
[AK4115]
PEM bit
(CS12 bit = “0”
2
“1”
)
1
PEM
CS12 bit =
Pre-emphasis
0
1
Table 15.
OFF
ON
PEM
Pre-emphasis
0
1
Table 16.
OFF
ON
Byte 0
Bits 3-5
≠ 0X100
0X100
Byte 0
Bits 2-4
≠110
110
■
IIR
3
DEAU bit = “1”
(32kHz, 44.1kHz, 48kHz)
FS3-0 bits
(50/15μs
DEAU bit = “0”
OFF
PEM bit = “0”
PEM
1
1
1
1
0
FS3
0
0
0
FS2
0
0
0
DEM1-0 bits
FS1
0
1
1
(Others)
x
Table 17.
PEM
1
1
1
1
0
Table 18.
)
x
x
DEM1
0
0
1
1
x
DEM0
0
1
0
1
x
MS0573-J-01
FS0
0
0
1
Mode
44.1kHz
48kHz
32kHz
OFF
x
OFF
(DEAU bit = “1”: Default)
Mode
44.1kHz
OFF
Default
48kHz
32kHz
OFF
(DEAU bit = “0”)
2010/09
- 27 -
[AK4115]
■
AK4115
PDN pin
PWN bit
PDN pin
RSTN bit
PDN pin
“L”
PDN pin:
“L”
RSTN bit (
“0”
00H D0):
PWN RSTN
“0”
PWN bit (
SDTO pin
“L”
PWN RSTN
00H D1):
“0”
PLL
X’tal
■
8
(RX7-0)
200mVpp
IPS2 bit
0
0
0
0
1
1
1
1
Table 19.
4
(RX3-0)
IPS2-0
IPS1 bit
0
0
1
1
0
0
1
1
IPS1 pin
0
0
1
1
Table 20.
IPS0 bit
0
1
0
1
0
1
0
1
IPS0 pin
0
1
0
1
MS0573-J-01
INPUT Data
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
Default
INPUT Data
RX0
RX1
RX2
RX3
2010/09
- 28 -
[AK4115]
■
AK4115
TX1
TX0
TX1
2
OPS00, OPS01, OPS02 bit
RX7-0
DIT
RS422
TX1
OPS10, OPS11, OPS12 bit
DIT
RX
TX0
RX0
(DIT: DAUX
IEC60958
DIT bit
OPS02
0
0
0
0
1
1
1
1
DIT
0
0
0
0
0
0
0
0
1
TX0
RX7-0
OPS01
OPS00
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Table 21. TX0
OPS12
OPS11
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
x
x
Table 22. TX1
MS0573-J-01
OPS10
0
1
0
1
0
1
0
1
x
“1”
TX1
Output Data
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
Output Data
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
DAUX
)
RX7-0
DAUX
Default
Default
2010/09
- 29 -
[AK4115]
■
0.1uF
75Ω
Coax
RX
75Ω
AK4115
Figure 21.
Note: Coaxial
(Coaxial
)
RX
50mV
Optical Receiver
Optical
Fiber
470
RX
O/E
AK4115
Figure 22.
(
)
0.1uF
RXP
110Ω
Twisted
Pair
110Ω
0.1uF
RXN
AK4115
Table 23.
Note. RXN pin
AC
Coaxial
2
(RX3-0)
“H”
RX7-4
“L”
MS0573-J-01
2010/09
- 30 -
[AK4115]
■
AK4115 2
TX
Figure 25, Figure 26
TVDD
T1
1:1
Figure 23, Figure 24,
1%
1. TX0
TX0
R1, R2
0.5V±20%
R1
TX0
75Ω cable
R2
TVSS
TVDD R1
3.3V 240Ω
3.0V 220Ω
5.0V 430Ω
T1
Figure 23. TX0
Note:
(PDN pin = “L”)
0.1uF
R2
150Ω
150Ω
150Ω
1
TX0 pin
Figure 24
AC
R1
TX0
75Ω cable
R2
TVDD R1
3.3V 240Ω
3.0V 220Ω
5.0V 430Ω
TVSS
T1
Figure 24. TX0
(AC
R2
150Ω
150Ω
150Ω
)
2. TX1
(TVDD = 4.5V ∼ 5.5V)
2-1.
TVDD=5V±10%
TX1 RS422
110Ω
75Ω
75Ω
110Ω ± 20%
RS422
AES3
2∼7Vpp
0.1uF
TXP1
110Ω cable
TXN1
T1
Figure 25.
MS0573-J-01
2010/09
- 31 -
[AK4115]
2-2.
(TVDD = 2.7V ∼ 5.5V)
75Ω±20%
R2
0.5V±20%
R1
0.5V±20%
0.1uF
R1
TXP1
75Ω cable
R2
TVDD R1
3.3V 270Ω
3.0V 240Ω
5.0V 430Ω
open
TXN1
T1
Figure 26.
(AC
R2
150Ω
150Ω
150Ω
)
■ PLL Loop Filter
FILT pin
(C1)
(R)
(C2)
FILT pin
(PSEL = “1”)
AVSS
Studio Sync
FILT pin
AK4115
FILT
R
C2
C1
AVSS
Figure 27. PLL Loop Filter
C1 [nF]
C2 [pF]
R [Ω]
24k ± 5%
10 ± 30%
100 ± 30%
Table 24. PLL Loop Filter
MS0573-J-01
2010/09
- 32 -
[AK4115]
■ Q-subcode buffers
CD
1.
2.
3.
4.
Q-subcode
Subcode sync word (S0,S1)
Start bit
“1”
Q-W
7 bit
start bit
Start bit
8-16 bits
Q-subcode
S0
S1
S2
S3
:
S97
S0
S1
S2
S3
:
1
0
0
1
1
:
1
0
0
1
1
:
16
Q3 Q4
CTRL
Q5
Q6
CD
Q-subcode
“0” bit
QINT
QINT bit
“0”
2
3
4
5
6
7
8
*
0
0
0
0
0
0
0
0…
0
0
0
0
0
0
0
0…
Q2 R2 S2
T2
U2 V2 W2 0…
Q3 R3 S3
T3
U3 V3 W3 0…
:
:
:
:
:
:
:
:
Q97 R97 S97 T97 U97 V97 W97 0…
0
0
0
0
0
0
0
0…
0
0
0
0
0
0
0
0…
Q2 R2 S2
T2
U2 V2 W2 0…
Q3 R3 S3
T3
U3 V3 W3 0…
:
:
:
:
:
:
:
:
↑
Q
Q2
U
Q7 Q8
ADRS
(*) number of "0" : min=0; max=8.
Figure 28. U-bit
(CD)
Q9
Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
TRACK NUMBER
INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49
MINUTE
SECOND
FRAME
Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73
ZERO
ABSOLUTE MINUTE
ABSOLUTE SECOND
Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97
ABSOLUTE FRAME
CRC
G(x)=x^16+x^12+x^5+1
Figure 29.Q-subcode
Addr
Register Name
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
D7
D6
D4
D3
D2
D1
D0
Q9
Q8
···
···
Q17
Q16
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
Q81
Q80
···
···
Figure 30. Q-subcode register
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
···
Q3
Q11
···
···
···
···
···
···
···
Q75
Q2
Q10
···
···
···
···
···
···
···
Q74
MS0573-J-01
D5
2010/09
- 33 -
[AK4115]
■ RX
(PSEL = “0”)
INT0, INT1 pin
“H”
Operation Mode 1), INT0, INT1 pin
1. UNLCK
9
PLL
OFF
(Clock
“L”
: PLL
“1”
2. PAR
:
“1”
3. AUTO
: Non-Linear PCM
DTS-CD
NPCM bit
DTSCD bit OR
4. V
:
“1”
5. AUDION
:
6. STC
:
AUDIO
FS3-0 or PEM bit
7. QINT
8. CINT
1
: U-bit Sync
U-bit
:
“1”
1
“1”
Sync
1
9. DAT
Sync
“1”
: DAT Start ID
DAT
“DAT Start ID”
DCNT bit = “1”
“3840x LRCK”
“DAT Start ID”
“3841x LRCK”
“DAT Start ID”
bit = “0”
DAT Start ID
“1”
MS0573-J-01
“1”
“1”
“1”
DCNT
2010/09
- 34 -
[AK4115]
1.
INT0 pin
UNLOCK, PAR
“H”
OR INT0 pin
AUTO, AUDION OR INT1
(UNLOCK
Parity)
1024/fs
Table 25
Event
UNLCK
PAR
AUTO
1
x
x
0
1
x
0
0
x
x
x
1
x
x
x
x
x
0
Note 40. AUTO or AUDION
Note 41. UNLCK or PAR
Note 42. UNLCK or PAR
Note 43. UNLCK, PAR
Table 25.
“H”
Pin
AUDION
INT0
INT1
SDTO
VOUT
x
“L”
“L”
“H”
Note 40 Previous Data
x
Output
Output
Output
x
“L”
x
“H”
Note 41
Note 42
Note 43
1
“L”
0
INT1 pin
“L” or “H”
INT0 pin
“L” or “H”
SDTO pin
“L”, “Previous Data” or “Normal Data”
VOUT pin
“L” or “Normal Output”
(x: Don’t care)
2.
1
9
OR
INT1-0 pin
INT
07H, 08H(DAT bit)
1024/fs (EFH1-0 bits
“L”
INT0
)
“H”
INT1
07H UNLCK, PAR, AUTO, AUDION, VRX bit
QINT, CINT, DAT bit
“1”
“H”
INT0 pin
Pc Pd
INT1 pin AUTO, AUDION
UNLCK, PAR
Event
UNLCK
PAR
1
x
0
1
x
x
Table 26.
STC,
Others
x
x
x
SDTO
“L”
Previous Data
Output
MS0573-J-01
Pin
VOUT
TX
“L”
Output
Output
Output
Output
Output
(x: Don’t care)
2010/09
- 35 -
[AK4115]
Error
(UNLOCK, PAR,..)
(Error)
INT0 pin
Hold Time (max: 4096/fs)
INT1 pin
Hold Time = 0
Register
(PAR,CINT,QINT)
Reset
Hold “1”
Register
(others)
Command
MCKO,BICK,LRCK
(UNLOCK)
READ 07,08H
Free Run
(fs: around 6kHz)
MCKO,BICK,LRCK
(except UNLOCK)
SDTO
(UNLOCK)
SDTO
(PAR error)
Previous Data
SDTO
(others)
VOUT pin
(UNLOCK)
VOUT pin
(except UNLOCK)
Normal Operation
Figure 31. INT0/1 pin
MS0573-J-01
2010/09
- 36 -
[AK4115]
PDN pin ="L" to "H"
Initialize
Read (07H, 08H)
INT0/1 pin ="H"
No
Yes
Release
Muting
Mute DA C output
Read (07H, 08H)
(Each Error Handling)
Read 07H, 08H
(Res ets registers)
No
INT0/1 pin ="H"
Yes
Figure 32.
1
MS0573-J-01
2010/09
- 37 -
[AK4115]
PDN pin ="L" to "H"
Initialize
Read (07H, 08H)
No
INT1 pin ="H"
Yes
Read (07H, 08H)
and
Detect QSUB= “1”
(Read Q-buffer)
QCRC = “0”
No
New data
is invalid
Yes
INT1 pin ="L"
No
Yes
New data
is valid
Figure 33.
(Q/CINT)
MS0573-J-01
2010/09
- 38 -
[AK4115]
■ ELRCK
(PSEL = “1”)
INT0, INT1 pin
“H”
Operation Mode 1), INT0, INT1 pin
1.
UNLCK : PLL
PLL
ELRCK
2
PLL
OFF
(Clock
“L”
“1”
4
5%
ELRCK
2%
PLL
2.
FS3-0
typ. 11kHz
:
FS3-0 bit 128fs
INT0 pin, INT1 pin
“L”
128
INT0
INT0 INT1
FS3-0 bit
“1fs”
STC bit
“H”
INT0 INT1
2
1.
UNLCK
“L”
INT0
FS3-0 bit
INT1
INT0, INT1
2.
2
UNLCK
1
0
OR
INT0
INT1
Event
Change of FS3-0 bits
x
1
Table 27.
MS0573-J-01
INT0
Pin
SDTO
“L”
Output
(x: Don’t care)
INT1
TX
Output
Output
2010/09
- 39 -
[AK4115]
■
1. LRCK, BICK, SDTO and DAUX
8
(Table 28) DIF2-0 bit
4
(Table 29) DIF1 pin, DIF0 pin
2’s complement
SDTO BICK
DAUX
Mode 0-5
BICK 64fs
Mode 6-7 Mode 4-5
fs=48kHz
128fs
20
(Mode 0-2)
(Figure 34)
Parity Error, Bi-phase Error or Frame Length Error
MSB
BICK
LSB
SDTO
“L”
PLL
“0”
SDTO
DAUX
Clock Mode 1
DAUX
3 PLL unlock
Mode 5, 7
Mode 5, 7
24
Clock Mode 2
Left justified
SDTO
I2S
LRCK BICK
Mode 4-5
AES3 bit “1”
U, B bit
(Figure 39)
DAUX
MSB
SDTO
DAUX pin
AES3
LSB
2’s complement
B bit “1”
B-sync
SDTO pin
DIF0 bit
24 bit, MSB justified
SDTO pin
V, U, C, B bit
“0”
SDTO pin
Mode 8-9
Mode 6-7
MCKO1/2 pin
V, C,
DIF0 bit = “0”
LSB
24bit, MSB justified
DIF0 bit = “1”
AES3
(ASYNC bit = “0”)
sub-frame of IEC958
0
3 4
preamble
7 8
11 12
27 28 29 30 31
Aux.
V U C P
LSB
MSB
MSB
LSB
23
0
AK4115 Audio Data (MSB First)
Figure 34. Bit configuration
MS0573-J-01
2010/09
- 40 -
[AK4115]
Mode
0
1
2
3
4
5
6
7
8
9
AES3
bit
0
0
0
0
0
0
0
0
1
1
Mode
4
5
6
7
DIF2
bit
0
0
0
0
1
1
1
1
0
0
DIF1 DIF0
bit
bit
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
Table 28.
DIF1
pin
0
0
1
1
DIF0
pin
0
1
0
1
DAUX
SDTO
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
24bit, Left justified
AES3 Mode
DAUX
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
AES3 Mode
AES3 Mode
LRCK
I/O
H/L
O
L/H
O
H/L
I
L/H
I
SDTO
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
Table 29.
LRCK
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
H/L
I
L/H
I
H/L
O
H/L
O
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
BICK
64fs
64fs
64fs
64fs
64fs
64fs
64-128fs
64-128fs
64fs
64fs
I/O
O
O
O
O
O
O
I
I
O
O
BICK
64fs
64fs
64-128fs
64-128fs
I/O
O
O
I
I
2. EMCK, ELRCK, EBICK and DAUX
DAUX
MSEL bit
EDIF1-0 bit
X’tal or EMCK
Mode
EDIF1 bit
4
5
6
7
0
0
1
1
EDIF0 bit
0
1
0
1
Table 30.
X’tal/EMCK
ECKS1
0
0
1
1
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
ELRCK
I/O
H/L
O
L/H
O
H/L
I
L/H
I
ECKS1-0 bit
128fs, 256fs or 512fs
DAUX
ECKS0
EMCK Frequency
0
512fs
1
256fs
0
128fs
1
N/A
Table 31. EMCK
MS0573-J-01
fs(max)
54kHz
108kHz
216kHz
-
EBICK
64fs
64fs
64-128fs
64-128fs
I/O
O
O
I
I
Default
Default
2010/09
- 41 -
Default
[AK4115]
LRCK(O)
0
1
2
15
16
17
31
0
1
2
15
16
17
31
0
1
BICK
(O:64fs)
15
14
1
0
15
14
1
0
SDTO(O)
15:MSB, 0:LSB
Rch Data
Lch Data
Figure 35. Mode 0 Timing
LRCK(O)
0
1
2
9
10
12
11
31
0
1
2
9
10
11
12
31
0
1
0
1
BICK
(O:64fs)
23
22
21
20
1
0
23
22
21
20
1
0
SDTO(O)
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 36. Mode 3 Timing
LRCK
ELRCK
BICK
EBICK
(64fs)
0
1
23
SDTO(O)
DAUX(I)
2
21
22 21
22
2
24
23
1
31
0
0
1
2
23 22
21
3
22
2
23
1
24
31
0
23 22
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 37. Mode 4, 6 Timing
Mode4 : LRCK, BICK, ELRCK, EBICK : Output
Mode6 : LRCK, BICK, ELRCK, EBICK: Input
LRCK
ELRCK
BICK
EBICK
(64fs)
SDTO(O)
DAUX(I)
0
1
2
23
22
22 21
24
23
2
1
25
31
0
1
2
23 22
0
21
22
3
23
2
1
24
25
0
31
0
1
23
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 38. Mode 5, 7 Timing
MS0573-J-01
Mode5 : LRCK, BICK, ELRCK, EBICK : Output
Mode7 : LRCK, BICK, ELRCK, EBICK : Input
2010/09
- 42 -
[AK4115]
LRCK(O)
0
1
2
24
25
27
26
28
31
0
1
2
24
25
26
27
31
28
0
1
BICK(O)
(64fs)
SDTO(O)
DAUX(I)
0
1
2
23
V
U
C
0
B
1
2
23
V
U
C
B
0
1
23:MSB, 0:LSB
V: Validity, C: C-bit, U:U-bit, B:B sync
Rch Data
Lch Data
Figure 39. AES3 Mode
■
1. 4
(IIC pin = “L”)
4
I/F (CSN, CCLK, CDTI, CDTO)
I/F
Chip address (2bits, C1-0 “00”
Read/Write (1bit), Register address (MSB first, 8bits) Control Data (MSB first, 8bits)
CCLK
“↓”
“↑”
CSN
“↑”
CSN “↑”
Hi-Z
CCLK
5MHz (max)
PDN pin = “L”
P/SN pin
PDN pin = “L”
),
CSN
0
1
7
8
2
3
4
5
6
0
0
0
0
0 R/W A7
9
10
11
12
13
14
15 16
A6
A5
A4
A3
A2
A1
A0 D7 D6 D5 D4 D3 D2 D1 D0
A6
A5
A4
A3
A2
A1
A0 D7 D6 D5 D4 D3 D2 D1 D0
17
18
19
20
21
22
23
CCLK
CDTI
WRITE
C1 C0
Hi-Z
CDTO
CDTI
READ
CDTO
C1 C0
0
0
0
0
0 R/W A7
Hi-Z
C1-C0:
R/W:
A7-A0:
D7-D0:
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Chip Address (Fixed to “00”)
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
Figure 40. 4
I/F
MS0573-J-01
2010/09
- 43 -
[AK4115]
2. I2C
(IIC pin = “H”)
AK4115 I2C
(max : 400kHz)
2-1.
IC
·
1
·
IC
IC
READ
IC
WRITE
·
2-1-1.
SDA
SCL
“L”
·
“L”
“H”
“H”
“H”
SCL
“L”
SDA
SDA
SCL
·
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 41.
2-1-2.
SCL
“H”
SDA
“H”
·
“L”
SCL
·
·
“H”
·
SDA
“L”
“H”
SCL
SDA
START CONDITION
Figure 42.
STOP CONDITION
·
·
MS0573-J-01
2010/09
- 44 -
[AK4115]
2-1-3.
IC
1
SDA
IC
SDA
(HIGH
)
“L”
AK4115
WRITE
AK4115
·
READ
SDA
·
SDA
AK4115
·
AK4115
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 43.
2-1-4.
1
1
IC
“00100”
·
IC
·
2
7
IC
·
1
R/W bit = “0”
READ
0
0
1
8
WRITE
0
(
0
CAD1
(CAD1, CAD0
Figure 44.
)
CAD0
5
CAD1 pin, CAD0 pin
IC
R/W bit
R/W bit = “1”
R/W
)
1
MS0573-J-01
2010/09
- 45 -
[AK4115]
2-2. WRITE
R/W bit
“0”
AK4115
2
A7
WRITE
A6
WRITE
A5
A4
A3
Figure 45.
2
MSB first, 8-bit
A2
A1
A0
2
3
8 bit MSB first
D7
D6
D5
D4
Figure 46.
D3
D2
D1
D0
3
AK4115
1
49H
S
T
A
R
T
SDA
·
Register
Address(n)
Slave
Address
·
00H
S
T
Data(n+x) O
P
Data(n+1)
Data(n)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 47. WRITE
MS0573-J-01
2010/09
- 46 -
[AK4115]
2-3. READ
R/W bit
“1”
·
AK4115
READ
49H
AK4115
00H
·
·
·
READ
2-3-1.
AK4115
·
·
·
(READ
WRITE
n+1
(R/W bit = “1”)
·
AK4115
READ
·
·
)
n
·
·
·
·
1
1
·
S
T
A
R
T
SDA
Slave
Address
Data(n)
Data(n+1)
READ
S
Data(n+x) T
O
P
Data(n+2)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 48. CURRENT ADDRESS READ
2-3-2.
·
·
·
(R/W bit = “1”)
·
WRITE
WRITE
READ
·
·
(R/W bit = “0”)
AK4115
·
READ
·
(R/W bit = “1”)
AK4115
·
1
·
READ
S
T
A
R
T
SDA
Slave
Address
S
T
A
R
T
Word
Address(n)
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 49. RANDOM READ
MS0573-J-01
2010/09
- 47 -
[AK4115]
■
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
CLK & Power Down Control
CS12
BCU
CM1
CM0
OCKS1
OCKS0
PWN
RSTN
01H
Format & De-em Control
AES3
DIF2
DIF1
DIF0
DEAU
DEM1
DEM0
ACKS
02H
Input/ Output Control 0
TX1E
OPS12
OPS11
OPS10
TX0E
OPS02
OPS01
OPS00
03H
Input/ Output Control 1
EFH1
EFH0
UDIT
BCU_IO
DIT
IPS2
IPS1
IPS0
04H
INT0 MASK
MQIT0
MAUT0
MCIT0
MULK0
MV0
MSTC0 MAUD0 MPAR0
05H
INT1 MASK
MQIT1
MAUT1
MCIT1
MULK1
MV1
MSTC1 MAUD1 MPAR1
06H
DAT Mask & DTS Detect
DIV
XMCK
FAST
DCNT
DTS16
DTS14
07H
Receiver Status 0
QINT
AUTO
CINT
UNLCK
VRX
STC
AUDION
PAR
08H
Receiver Status 1
FS3
FS2
FS1
FS0
PEM
DAT
DTSCD
NPCM
0
0
0
0
09H
Receiver Status 2
0
0
0AH
Clock Control
TX1NE
0
0BH
TX Control
MSEL
0CH
RX Channel Status Byte 0
•
23H
MDAT1 MDAT0
QCRC
CCRC
MCK2E MCK1E ASYNC WSYNC
XSEL
PSEL
ECKS1
ECKS0
EDIF1
EDIF0
CTRAN
CCRE
VTX
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
•
RX Channel Status Byte 23
•
CR191
•
CR190
•
CR189
•
CR188
•
CR187
•
CR186
•
CR185
•
CR184
24H
TX Channel Status Byte 0
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
•
3BH
•
TX Channel Status Byte 23
•
CT191
•
CT190
•
CT189
•
CT188
•
CT187
•
CT186
•
CT185
•
CT184
3CH
Burst Preamble Pc Byte 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
3DH
Burst Preamble Pc Byte 1
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
3EH
Burst Preamble Pd Byte 0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
3FH
Burst Preamble Pd Byte 1
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
40H
Q-subcode Address / Control
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
41H
Q-subcode Track
Q17
Q16
Q15
Q14
Q13
Q12
Q11
Q10
42H
Q-subcode Index
Q25
Q24
Q23
Q22
Q21
Q20
Q19
Q18
43H
Q-subcode Minute
Q33
Q32
Q31
Q30
Q29
Q28
Q27
Q26
44H
Q-subcode Second
Q41
Q40
Q39
Q38
Q37
Q36
Q35
Q34
45H
Q-subcode Frame
Q49
Q48
Q47
Q46
Q45
Q44
Q43
Q42
46H
Q-subcode Zero
Q57
Q56
Q55
Q54
Q53
Q52
Q51
Q50
47H
Q-subcode ABS Minute
Q65
Q64
Q63
Q62
Q61
Q60
Q59
Q58
48H
Q-subcode ABS Second
Q73
Q72
Q71
Q70
Q69
Q68
Q67
Q66
49H
Q-subcode ABS Frame
Q81
Q80
Q79
Q78
Q77
Q76
Q75
Q74
4AH
Optional Control
0
0
0
0
0
0
CTX
0
: PDN pin
“L”
RSTN bit
“0”
PWN bit
“0”
4BH
FFH
MS0573-J-01
2010/09
- 48 -
[AK4115]
■
Reset & Initialize
Addr
Register Name
00H CLK & Power Down Control
R/W
Default
D7
CS12
R/W
0
D6
BCU
R/W
1
D5
CM1
R/W
0
D4
CM0
R/W
0
D3
D2
OCKS1 OCKS0
R/W
R/W
0
0
D1
PWN
R/W
1
D0
RSTN
R/W
1
RSTN:
0:
1:
&
(Default)
PWN:
0:
1:
(Default)
OCKS1-0:
(See Table 9)
CM1-0:
(See Table 1, Table 4)
BCU: BCU_IO bit = “1”
(B) , C, U
0: B pin, C pin, U pin
“L”
1: B pin, C pin, U pin
BCU_IO bit
“0”
BCU bit
CS12:
0: Channel 1 (Default)
1: Channel 2
C-bit, AUDION, PEM, FS3-0, Pc, Pd
channel 1
(Default)
Format & De-emphasis Control
Addr
Register Name
01H Format & De-em Control
R/W
Default
D7
AES3
R/W
0
D6
DIF2
R/W
1
ACKS: Master clock Auto Setting Mode
0: Disable (Default)
1: Enable
DEM1-0: 32, 44.1, 48kHz
DEAU:
0: Disable
1: Enable (Default)
DIF2-0, AES3:
D5
DIF1
R/W
1
D4
DIF0
R/W
0
D3
DEAU
R/W
1
D2
DEM1
R/W
0
D1
DEM0
R/W
1
D0
ACKS
R/W
0
(See Table 18)
(See Table 28)
MS0573-J-01
2010/09
- 49 -
[AK4115]
Input/Output Control
Addr
Register Name
02H Input/ Output Control 0
R/W
Default
OPS02-00: TX0 pin
TX0E: TX0 pin
0: Disable. TX0 pin
1: Enable (Default)
OPS12-10: TX1 pin
TX1E: TXP1/N1 pin
0: Disable. TXP1 pin
1: Enable (Default)
Addr
Register Name
03H Input/ Output Control 1
R/W
Default
D7
TX1E
R/W
1
D6
D5
D4
OPS12 OPS11 OPS10
R/W
R/W
R/W
0
0
0
D3
TX0E
R/W
1
D2
D1
D0
OPS02 OPS01 OPS00
R/W
R/W
R/W
0
0
0
(See Table 21)
“L”
(See Table 22)
“L”
D7
EFH1
R/W
0
TXN1 pin
D6
EFH0
R/W
1
“H”
D5
D4
UDIT BCU_IO
R/W
R/W
0
1
D3
DIT
R/W
1
D2
IPS2
R/W
0
D1
IPS1
R/W
0
D0
IPS0
R/W
0
IPS2-0:
(See Table 19)
DIT: TXP1/N1 pin
0:
(RX
).
1:
(DAUX
) (Default)
BCU_IO: B pin, C pin, U pin
0:
1:
(Default)
UDIT: DIT U bit
0: U bit “0”
(Default)
1:
U bit
(U bit
)
EFH1-0: INT0 pin
00: 512 LRCK
01: 1024 LRCK (Default)
10: 2048 LRCK
11: 4096 LRCK
MS0573-J-01
2010/09
- 50 -
[AK4115]
Mask Control for INT0
Addr
Register Name
04H INT0 MASK
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
MQIT0 MAUT0 MCIT0 MULK0 MVRX0 MSTC0 MAUD0 MPAR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
0
1
1
1
0
MPAR0: Mask enable for PAR bit
0: Mask disable (Default)
1: Mask enable
MAUD0:Mask enable for AUDION bit
0: Mask disable
1: Mask enable (Default)
MSTC0: Mask enable for STC bit
0: Mask disable
1: Mask enable (Default)
MVRX0:Mask enable for VRX bit
0: Mask disable
1: Mask enable (Default)
MULK0:Mask enable for UNLCK bit
0: Mask disable (Default)
1: Mask enable
MCIT0: Mask enable for CINT bit
0: Mask disable
1: Mask enable (Default)
MAUT0:Mask enable for AUTO bit
0: Mask disable
1: Mask enable (Default)
MQIT0: Mask enable for QINT bit
0: Mask disable
1: Mask enable (Default)
“1”
INT0 pin
MS0573-J-01
2010/09
- 51 -
[AK4115]
Mask Control for INT1
Addr
Register Name
05H INT1 MASK
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
MQIT1 MAUT1 MCIT1 MULK1 MVRX1 MSTC1 MAUD MPAR1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
1
1
1
0
1
MPAR1: Mask enable for PAR bit
0: Mask disable
1: Mask enable (Default)
MAUD1:Mask enable for AUDION bit
0: Mask disable (Default)
1: Mask enable
MSTC1: Mask enable for STC bit
0: Mask disable
1: Mask enable (Default)
MVRX1:Mask enable for VRX bit
0: Mask disable
1: Mask enable (Default)
MULK1:Mask enable for UNLCK bit
0: Mask disable
1: Mask enable (Default)
MCIT1: Mask enable for CINT bit
0: Mask disable
1: Mask enable (Default)
MAUT1:Mask enable for AUTO bit
0: Mask disable (Default)
1: Mask enable
MQIT1: Mask enable for QINT bit
0: Mask disable
1: Mask enable (Default)
“1”
INT1 pin
MS0573-J-01
2010/09
- 52 -
[AK4115]
DAT Mask & DTS Detect
Addr
Register Name
06H DAT Mask & DTS Detect
R/W
Default
D7
DIV
R/W
0
D6
XMCK
R/W
0
D5
FAST
R/W
0
D4
DCNT
R/W
1
MDAT0: Mask enable for DAT bit
0: Mask disable
1: Mask enable (Default)
“1”
MDAT1: Mask enable for DAT bit
0: Mask disable
1: Mask enable (Default)
“1”
DTS14: DTS-CD 14bit Sync Word Detect
0: Disable
1: Enable (Default)
DTS16: DTS-CD 16bit Sync Word Detect
0: Disable
1: Enable (Default)
DCNT: DAT Start ID Counter
0: Disable
1: Enable (Default)
FAST:
PLL Lock Time
0: ≤ (20ms + 384/fs) (Default)
1: ≤ (20ms + 1/fs)
XMCK: MCKO2
(See Table 10)
0: CM1-0 bits, OCKS1-0 bits
(Default)
1: X’tal
DIV: X’tal
MCKO2
(See Table 10)
0: x1 (Default)
1: x 1/2
MS0573-J-01
D3
DTS16
R/W
1
D2
D1
D0
DTS14 MDAT1 MDAT0
R/W
R/W
R/W
1
1
1
INT0 pin
INT1 pin
2010/09
- 53 -
[AK4115]
Receiver Status 0
Addr
Register Name
07H Receiver status 0
R/W
Default
D7
QINT
RD
0
D6
AUTO
RD
0
D5
CINT
RD
0
D4
UNLCK
RD
0
D3
VRX
RD
0
D2
STC
RD
0
D1
AUDION
RD
0
D0
PAR
RD
0
PAR:
0: No Error
1: Error
PAR bit
“1”
AUDION: Audio
0: Audio
1: Non Audio
STC:
0: No detect
1: Detect
FS3-0 bits or PEM bit
STC bit
“1”
VRX: RX
0: Valid
1: Invalid
UNLCK: PLL Lock Status
0: Lock
1: Unlock
CINT:
0: No change
1: Changed
Addr = 0CH(Channel Status
C-bit
AUTO: Non-PCM
0: No detect
1: Detect
QINT: Q-subcode Buffer Interrupt
0: No change
1: Changed
Addr = 40H(
)
49H(
)
STC, QINT, CINT, PAR bit
READ
07H
)
24H Channel Status
“1”
MS0573-J-01
Q-subcode
“1”
2010/09
- 54 -
[AK4115]
Receiver Status 1
Addr
Register Name
08H Receiver status 1
R/W
Default
NPCM: Non-PCM
0: No detect
1: Detect
DTSCD: DTS-CD
0: No detect
1: Detect
DAT: DAT Start ID
0: No detect
1: Detect
DAT bit
PEM: Pre-emphasis
0: OFF
1: ON
D7
FS3
RD
0
D6
FS2
RD
0
08H
D5
FS1
RD
0
D4
FS0
RD
1
D3
PEM
RD
0
D2
DAT
RD
0
D1
DTSCD
RD
0
D0
NPCM
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
0
RD
0
D1
QCRC
RD
0
D0
CCRC
RD
0
READ
(See Table 14)
FS3-0:
Receiver Status 1
Addr
Register Name
09H Receiver status 1
R/W
Default
CCRC:
D7
0
RD
0
D6
0
RD
0
CRCC
0: No error
1: Error
CS12 bit
QCRC: Q-subcode CRCC
0: No error
1: Error
MS0573-J-01
2010/09
- 55 -
[AK4115]
Mode Control
Addr
Register Name
0AH Mode Control
R/W
Default
D7
TX1NE
R/W
1
D6
0
RD
0
D5
D4
D3
D2
MCK2E MCK1E ASYNC WSYNC
R/W
R/W
R/W
R/W
1
1
0
0
PSEL: PLL
(See Table 1)
XSEL: X’tal
(See Table 12)
WSYNC:
ELRCK
0: Disable (Default)
1: Enable
ASYNC: DIT/DIR
0:
(Default)
1:
MCK1E: MCKO1
0: Disable. “L”
1: Enable (Default)
MCK2E: MCKO2
0: Disable. “L”
1: Enable (Default)
TX1NE: TXN1 pin
0: Disable. “L”
Consumer mode
1: Enable (Default)
D1
XSEL
R/W
0
D0
PSEL
R/W
0
D1
CCRE
R/W
1
D0
VTX
R/W
0
“0”
TX Control
Addr
Register Name
0BH TX Control
R/W
Default
D7
MSEL
RD
0
D6
ECKS1
RD
0
D5
ECKS0
R/W
1
D4
EDIF1
R/W
1
D3
EDIF0
R/W
0
D2
CTRAN
R/W
0
VTX: TX
0: Valid (Default)
1: Invalid
CCRE:
0: CRC
1: CRC
CTRAN: CR191-0 bit
0:
(Default)
1:
or
CTRAN bit “0”
CT191-0 bit
EDIF1-0:
ECK1-0: EMCK
MSEL:
TX
CRC
CRC
“1”
(Default)
CR191-0 bit CT191-0 bit
(See Table 30)
(See Table 31)
(See Table 4)
MS0573-J-01
2010/09
- 56 -
[AK4115]
Receiver Channel Status
Addr
Register Name
0CH RX Channel Status Byte 0
•
•
23H RX Channel Status Byte 23
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
•
•
•
•
•
•
•
•
CR191 CR190 CR189 CR188 CR187 CR186 CR185 CR184
RD
Not initialized
CR191-0: Receiver Channel Status Byte 23-0
Transmitter Channel Status
Addr
Register Name
24H TX Channel Status Byte 0
R/W
Default
25H TX Channel Status Byte 1
•
•
3BH TX Channel Status Byte 23
R/W
Default
D7
CT7
D6
CT6
D5
CT5
0
CT15
•
CT191
0
CT14
•
CT190
0
CT13
•
CT189
D4
CT4
D3
CT3
R/W
0
0
CT12
CT11
•
•
CT188 CT187
R/W
0
D2
CT2
D1
CT1
D0
CT0
1
CT10
•
CT186
0
CT9
•
CT185
0
CT8
•
CT184
D2
PC2
PC10
PD2
PD10
D1
PC1
PC9
PD1
PD9
D0
PC0
PC8
PD0
PD8
CT7-0: Transmitter Channel Status Byte 0
Default: “00000100”
CT191-8: Transmitter Channel Status Byte 23-1
Default: “00000000”
Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams
Addr
3CH
3DH
3EH
3FH
Register Name
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
R/W
Default
D7
PC7
PC15
PD7
PD15
D6
PC6
PC14
PD6
PD14
D5
PC5
PC13
PD5
PD13
D4
PC4
PC12
PD4
PD12
D3
PC3
PC11
PD3
PD11
RD
Not initialized
PC15-0: Burst Preamble Pc Byte 0 and 1
PD15-0: Burst Preamble Pd Byte 0 and 1
MS0573-J-01
2010/09
- 57 -
[AK4115]
Q-subcode Buffer
Addr
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
R/W
Default
D7
Q9
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
Q81
D6
Q8
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
Q80
D5
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
D4
Q6
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
D3
Q5
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
D2
Q4
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
D1
Q3
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
D0
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
RD
Not initialized
Optional Control
Addr
Register Name
4AH Optional Control
R/W
Default
CTX: AES3
0: DAUX
1:
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
CT191-0 bit
MS0573-J-01
D4
0
RD
0
TX1
TX1
D3
0
RD
0
D2
0
RD
0
D1
CTX
R/W
0
D0
0
RD
0
(Default)
2010/09
- 58 -
[AK4115]
■ Non-PCM
sub-frame of IEC958
0
3 4
preamble
7 8
11 12
Aux.
27 28 29 30 31
LSB
MSB V U C P
16 bits of bitstream
0
Pa Pb Pc Pd
15
Burst_payload
stuffing
repetition time of the burst
Figure 50. IEC60958
Preamble word
Pa
Pb
Pc
Pd
Length of field
16 bits
16 bits
16 bits
16 bits
Table 32.
Contents
sync word 1
sync word 2
Burst info
Length code
Bits of Pc Value
Contents
0-4
data type
NULL data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 without extension
MPEG-2 data with extension
MPEG-2 AAC ADTS
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
reserved, shall be set to “0”
error-flag indicating a valid burst_payload
error-flag indicating that the burst_payload may contain
errors
data type dependent info
bit stream number, shall be set to “0”
Table 33.
Pc
5, 6
7
8-12
13-15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
0
0
1
0
Value
0xF872
0x4E1F
see Table 33
numbers of bits
Repetition time of burst
in IEC60958 frames
MS0573-J-01
≤4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
2010/09
- 59 -
[AK4115]
■ Non-PCM
1) Non-PCM
4096
PDN pin
Bit stream
Pa Pb Pc1 Pd1
Pa Pb Pc2 Pd2
Pa Pb Pc3 Pd3
Repetition time
>4096 frames
AUTO bit
Pc Register
“0”
Pd Register
“0”
Pc1
Pc2
Pd1
Pd2
Figure 51.
2) Non-PCM
Pc3
Pd3
1
(MULK0 bit = “0”
)
INT0 hold time
INT0 pin
< PLL Lock time
Bit stream
Pa Pb Pc1 Pd1
Stop
Pa Pb Pcn Pdn
2~3 Syncs (B,M or W)
<Repetition time
AUTO bit
Pc Register
Pd Register
Pc0
Pc1
Pd0
Pcn
Pd1
Figure 52.
Pdn
2
MS0573-J-01
2010/09
- 60 -
[AK4115]
Figure 53
4-wire serial mode
3.3V
S/PDIF Sources
C1: 0.1μ
C2: 10μ
C2
+
C1
4.7μ
C1
C1
S/PDIF
Sources
59
58
57
56
55
54
RX4
RX3
AVSS
RX2
AVDD
RX1
AVSS
RXP0
RXN0
ACKS
53
52
51
50
49
R
60
AVSS
61
VCOM
62
P/SN
63
10kΩ
AVDD
64
AVDD
+
100p
10n
24kΩ
1 RX5
FILT 48
2 TEST(AVSS)
XTL1 47
3 RX6
XTL0 46
4 PDN
PSEL 45
5 RX7
IIC 44
C2 C1
3.3V
+
6 DVDD
BVSS 43
7 VIN
DVSS 42
8 DAUX
DVDD 41
C1 +
Top View
9 DVSS
C2
3.3V
CSN 40
10 MCKO1
CCLK 39
11 MCKO2
CDTI 38
uP
DSP1
12 OVDD
CDTO 37
13 OVSS
INT1 36
C1
INT0 35
14 BICK
VOUT
TVDD
TX0
TXP1
TXN1
TVSS
XTI1
XTO1
XTI2
XTO2
OVDD
OVSS
EBICK
EMCK 33
U
16 LRCK
C
ELRCK 34
B
15 SDTO
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DSP2
C1
C1
+
+
uP
C
C2
C
C
C2
C
S/PDIF out
5V
3.3V
Figure 53. Typical Connection Diagram (4-wire serial mode)
Notes:
- XTL0 XTL1
Table 13
- “C”
- AVSS, BVSS, TVSS, OVSS, DVSS
-
R pin
MS0573-J-01
FILT pin
2010/09
- 61 -
[AK4115]
64pin LQFP(Unit: mm)
12.0
Max 1.85
10.0
1.40
0.00~0.25
33
32
48
12.0
49
64
17
16
1
0.5
0.2±0.1
0.09~0.25
0.10 M
0°~10°
0.50±0.25
0.10
■
MS0573-J-01
2010/09
- 62 -
[AK4115]
AKM
AK4115VQ
XXXXXXX
1
XXXXXXX: Date code identifier
Date (YY/MM/DD)
06/12/13
10/09/28
Revision
00
01
Reason
Page
Contents
7
■
1. Serial Mode (P/SN pin = “L”)
CDTO pin
2. Parallel Mode (P/SN pin = “H”)
CDTO pin
0AH, D5: MCK1E → MCK2E
56
62
MS0573-J-01
2010/09
- 63 -
[AK4115]
z
z
z
z
z
z
MS0573-J-01
2010/09
- 64 -