ASAHI KASEI [AK4113] AK4113 6:1 AK4113 192kHz, 24bit AK4113 192kHz 24bit DIR (DIR) Dolby Digital / MPEG CODEC(AK4626, AK4628) Non-PCM Dolby Digital µP I/F 30Pin VSOP * Dolby Digital is a trademark of Dolby Laboratories. AES/EBU, IEC60958, S/PDIF, EIAJ CP1201 PLL PLL : 8k ∼ 216kHz PLL/X'tal 6 1 32kHz, 44.1kHz, 48kHz - Non-PCM - DTS-CD 8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz - Unlock & Parity Error - Validity - DAT Start ID 24bit : / 40bit Non-PCM Pc, Pd CD Q-subcode µP : I2C(max. 400kHz) or 4-wire 64fs/128fs/256fs/512fs : 2.7 to 3.6V 5V 30 VSOP Ta: - 40 ∼ 85°C MS0349-J-02 2005/08 -1- ASAHI KASEI [AK4113] AVSS AVDD R XTI XTO X'tal RX1 Oscillator RX2 RX3 RX4 Input Clock Recovery Clock MCKO1 Generator MCKO2 (BOUT) Selector RX5 DEM RX6 DAIF Audio Decoder I/F V/TX LRCK BICK SDTO DAUX PDN CSN DVDD Error & STATUS Detect AC-3/MPEG DVSS TVDD Detect INT0 Q-subcode buffer µP I/F CCLK CDTO CDTI INT1(C, UOUT) P/SN= “L” I2C Figure 1. AVSS AVDD R XTI XTO X'tal Oscillator RX1 Input RX5 Selector Clock Recovery Clock MCKO1 Generator MCKO2 DEM DAIF V Audio Decoder I/F DIF0 DIF1 LRCK BICK SDTO DIF2 DAUX IPS PDN OCKS0 DVDD DVSS TVDD AC-3/MPEG Detect Error & STATUS Detect INT0 INT1 OCKS1 CM0 CM1 FS96 P/SN=“H” Figure 2. MS0349-J-02 2005/08 -2- ASAHI KASEI [AK4113] AK4113VF AKD4113 -40 ~ +85 °C AK4113 30pin VSOP (0.65mm pitch) DVDD 1 30 CM0/CDTO/CAD1 DVSS 2 29 CM1/CDTI/SDA TVDD 3 28 OCKS1/CCLK/SCL V/TX 4 27 OCKS0/CSN/CAD0 XTI 5 26 MCKO1 XTO 6 25 MCKO2 PDN 7 24 DAUX R 8 23 BICK AVDD 9 22 SDTO AVSS 10 21 LRCK RX1 11 20 INT0 RX2/DIF0 12 19 FS96/I2C RX3/DIF1 13 18 P/SN RX4/DIF2 14 17 INT1 RX5 15 16 IPS/RX6 Top View MS0349-J-02 2005/08 -3- ASAHI KASEI No. 1 2 3 Pin Name DVDD DVSS TVDD V TX XTI XTO [AK4113] I/O O O I O Function Digital Power Supply Pin, 3.3V Digital Ground Pin Input Buffer Power Supply Pin, 3.3V or 5V Validity Flag Output Pin in parallel control mode 4 Transmit channel (Through data) Output Pin in serial control mode 5 X'tal Input Pin 6 X'tal Output Pin Power-Down Mode Pin 7 PDN I When “L”, the AK4113 is powered-down and reset. External Resistor Pin 8 R This pin must be connected to AVSS via 15kΩ ± 5% resistor. 9 AVDD Analog Power Supply Pin 10 AVSS Analog Ground Pin 11 RX1 I Receiver Channel #1 Pin (Internal Biased Pin) DIF0 I Audio Data Interface Format #0 Pin in parallel control mode 12 RX2 I Receiver Channel #2 Pin in serial control mode (Internal Biased Pin) DIF1 I Audio Data Interface Format #1 Pin in parallel control mode 13 RX3 I Receiver Channel #3 Pin in serial control mode (Internal Biased Pin) DIF2 I Audio Data Interface Format #2 Pin in parallel control mode 14 RX4 I Receiver Channel #4 Pin in serial control mode (Internal Biased Pin) 15 RX5 I Receiver Channel #5 Pin (Internal Biased Pin) IPS I Input Channel Select Pin in parallel control mode 16 RX6 I Receiver Channel #6 Pin (Internal Biased Pin) Interrupt #1 Pin (when BCU bit = “0”) 17 INT1 O U-bit Output Pin (when BCU bit = “1”, UCE bit = “0”) C-bit Output Pin (when BCU bit = “1”, UCE bit = “1”) Parallel/Serial Select Pin 18 I P/SN “L”: Serial control mode, “H”: Parallel control mode 96kHz Sampling Detect Pin in parallel control mode FS96 O This function is enabled when the input frequency of XTI is 24.576MHz. 19 “L”: fs=54kHz or less, “H”: fs=64kHz or more I2C Select Pin in serial control mode. I2C I “L”: 4-wire Serial, “H”: I2C 20 INT0 O Interrupt #0 Pin 21 LRCK I/O Output Channel Clock Pin 22 SDTO O Audio Serial Data Output Pin 23 BICK I/O Audio Serial Data Clock Pin 24 DAUX I Auxiliary Audio Data Input Pin Master Clock #2 Output Pin (when BCU bit = “0”) 25 MCKO2 O Block Start Signal Output Pin (when BCU bit = “1”) 26 MCKO1 O Master Clock #1 Output Pin OCKS0 I Output Clock Select #0 Pin in parallel control mode 27 CSN I Chip Select Pin in serial control mode, I2C pin = “L” CAD0 I Chip Address #0 Pin in serial control mode, I2C pin = “H” Note 1. Do not allow digital input pins except internal biased pins (RX1-6 pins) to float. MS0349-J-02 2005/08 -4- ASAHI KASEI No. [AK4113] Pin Name I/O Function OCKS1 I Output Clock Select #1 Pin in parallel control mode CCLK I Control Data Clock Pin in serial control mode, I2C pin = “L” SCL I Control Data Clock Pin in serial control mode, I2C pin = “H” CM1 I Master Clock Operation Mode #1 Pin in parallel control mode 29 CDTI I Control Data Input Pin in serial control mode, I2C pin = “L” Control Data Pin in serial control mode, I2C pin = “H” SDA I/O CM0 I Master Clock Operation Mode #0 Pin in parallel control mode 30 CDTO O Control Data Output Pin in serial control mode CAD1 I Chip Address #1 Pin in serial control mode, I2C pin = “H” Note 1. Do not allow digital input pins except internal biased pins (RX1-6 pins) to float. 28 Classification Analog Input Pin Name RX1, RX2/DIF0, RX3/DIF1, RX4/DIF2, RX5, RX6/IPS RX1, RX5 Digital Input Digital Output DAUX, XTI DVSS V/TX, XTO, INT0, INT1, MCKO1, MCKO2 I2C/FS96 4-wire mode (I2C pin CAD1/CDTO/CM0 = “L”) MS0349-J-02 2005/08 -5- ASAHI KASEI AK4112B [AK4113] AK4113 Function RX Input Channel Serial control mode Parallel control mode PLL Lock Range Resistor value for R pin PLL Lock Time DTS-CD Bit Stream Detection DAT Start ID Detection Q-subcode Buffer for CD bit Stream fs Detection in serial control mode Serial µP Interface Error Handling Pins Master Clock Output Frequency Channel Status Bit MCKO2 Clock Source in serial control mode Audio I/F at reset in serial control mode Package AK4112B 4ch 1ch 22kHz to 108kHz 18k ± 1% AK4113 6ch 2ch 8kHz to 216kHz 15k ± 5% FAST bit =“0”: ≤ (15ms+384/fs) ≤ 20ms FAST bit =“1”: ≤ (15ms+1/fs) Not available Available Not available Available Not available Available ≤ 54kHz 8k / 11.025k / 16k / 22.05k / 24k/ or 32k / 44.1k / 48k / 64k / 88.2k / ≥88.2kHz 96k / 176.4k / 192kHz 4-wire 4-wire/I2C (max.400kHz) AUTO, ERF, FS96 INT0, INT1 128fs/256fs/512fs 64fs/128fs/256fs/512fs 32bit 40bit Depend on CM1-0, XMCK and Depend on CM1-0 bits BCU bits Master Mode Slave Mode 28pin VSOP 30pin VSOP MS0349-J-02 2005/08 -6- ASAHI KASEI [AK4113] 2. AK4112B DVDD 1 30 CM0/CDTO/CAD1 DVSS 2 29 CM1/CDTI/SDA TVDD 3 28 OCKS1/CCLK/SCL V/TX 4 27 OCKS0/CSN/CAD0 XTI 5 26 MCKO1 XTO 6 25 MCKO2 PDN 7 24 DAUX R 8 23 BICK AVDD 9 22 SDTO AVSS 10 21 LRCK RX1 11 20 INT0 (ERF) RX2/DIF0 12 19 FS96/I2C (FS96) RX3/DIF1 13 18 P/SN RX4/DIF2 14 17 INT1 (AUTO) 15 16 IPS/RX6 (None) (None) RX5 : 1) 2) ( ) AK4112B AK4112B Top View AK4113 AK4113 . 3. AK4112B AK4113 MS0349-J-02 2005/08 -7- ASAHI KASEI [AK4113] (AVSS, DVSS=0V; Note 2) Parameter Power Supplies: Analog Digital Input Buffer |AVSS-DVSS| (Note 3) Input Current (Any pins except supplies) Input Voltage Ambient Temperature (Power applied) Storage Temperature Note 2. Note 3. AVSS, DVSS Symbol AVDD DVDD TVDD ∆GND IIN VIN Ta Tstg Min -0.3 -0.3 -0.3 -0.3 -40 -65 max 4.6 4.6 6.0 0.3 ±10 TVDD+0.3 85 150 Units V V V V mA V °C °C : (AVSS, DVSS=0V; Note 2) Parameter Power Supplies: Analog Digital Input Buffer Difference Note 2. Symbol AVDD DVDD TVDD AVDD - DVDD S/PDIF (Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V) Parameter Symbol Input Resistance Zin Input Voltage VTH Input Hysteresis VHY Input Sample Frequency fs MS0349-J-02 min 2.7 2.7 DVDD -0.3 typ 3.3 3.3 3.3 0 max 3.6 3.6 5.5 0.3 Units V V V V min typ 10 max Units kΩ mVpp mV kHz 350 8 185 - 216 2005/08 -8- ASAHI KASEI [AK4113] DC (Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified) Parameter Symbol min typ max Units Power Supply Current Normal operation: PDN pin = “H” (Note 4) 26 42 mA Power down: PDN pin = “L” (Note 5) 10 100 µA High-Level Input Voltage VIH 70%DVDD TVDD V Low-Level Input Voltage VIL DVSS - 0.3 30%DVDD V High-Level Output Voltage VOH DVDD-0.4 V (Except TX pin: Iout=-400µA) Low-Level Output Voltage VOL 0.4 V (Except TX and SDA pin: Iout=400µA) VOL 0.4 V ( SDA pin: Iout= 3mA) TX Output Level (Note 6) VTXO 0.4 0.5 0.6 V Input Leakage Current (Except RX1-6, XTI pins) Iin ± 10 µA Note 4. AVDD, DVDD=3.3V, TVDD=5.0V, CL=20pF, fs=216kHz, X'tal=24.576MHz, Clock Operation Mode 2, OCKS1 bit = “1”, OCKS0 bit = “1”, Master mode, TX pin Figure 19 AVDD=5mA (typ), DVDD=21mA (typ), TVDD=0.1µA (typ) Note 5. RX DVDD DVSS Note 6. Figure 19 (Ta=25°C; AVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol Master Clock Timing Crystal Resonator Frequency fXTAL External Clock Frequency fECLK Duty dECLK MCKO1 Output Frequency fMCK1 Duty dMCK1 MCKO2 Output Frequency fMCK2 Duty dMCK2 PLL Clock Recover Frequency (RX1-6) fpll LRCK Frequency fs Duty Cycle dLCK Audio Interface Timing Slave Mode BICK Period tBCK BICK Pulse Width Low tBCKL Pulse Width High tBCKH tLRB LRCK Edge to BICK “↑” (Note 7) tBLR BICK “↑” to LRCK Edge (Note 7) tLRM LRCK to SDTO (MSB) tBSD BICK “↓” to SDTO tDXH DAUX Hold Time tDXS DAUX Setup Time Master Mode BICK Frequency fBCK BICK Duty dBCK tMBLR BICK “↓” to LRCK tBSD BICK “↓” to SDTO tDXH DAUX Hold Time tDXS DAUX Setup Time Note 7. LRCK min 11.2896 11.2896 40 1.024 40 0.512 40 8 8 45 typ 50 50 50 - max Units 24.576 24.576 60 27.648 60 27.648 60 216 216 55 MHz MHz % MHz % MHz % kHz kHz % 72 27 27 15 15 20 20 15 15 64fs 50 -15 15 15 15 15 ns ns ns ns ns ns ns ns ns Hz % ns ns ns ns BICK MS0349-J-02 2005/08 -9- ASAHI KASEI [AK4113] (Ta=25°C; AVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol Control Interface Timing (4-wire serial mode) tCCK CCLK Period tCCKL CCLK Pulse Width Low tCCKH Pulse Width High tCDS CDTI Setup Time tCDH CDTI Hold Time tCSW CSN “H” Time tCSS CSN “↓” to CCLK “↑” tCSH CCLK “↑” to CSN “↑” tDCD CDTO Delay tCCZ CSN “↑” to CDTO Hi-Z 2 Control Interface Timing (I C Bus mode): fSCL SCL Clock Frequency tBUF Bus Free Time Between Transmissions tHD:STA Start Condition Hold Time (prior to first clock pulse) tLOW Clock Low Time tHIGH Clock High Time tSU:STA Setup Time for Repeated Start Condition tHD:DAT SDA Hold Time from SCL Falling (Note 8) tSU:DAT SDA Setup Time from SCL Rising tR Rise Time of Both SDA and SCL Lines tF Fall Time of Both SDA and SCL Lines tSU:STO Setup Time for Stop Condition Cb Capacitive load on bus tSP Pulse Width of Spike Noise Suppressed by Input Filter Reset Timing PDN Pulse Width tPW Note 8. 300ns (SCL ) Note 9. I2C Philips Semiconductors MS0349-J-02 min typ max Units 45 70 ns ns ns ns ns ns ns ns ns ns 400 0.3 0.3 400 50 kHz µs µs µs µs µs µs µs µs µs µs pF ns 200 80 80 50 50 150 50 50 1.3 0.6 1.3 0.6 0.6 0 0.1 0.6 0 150 ns 2005/08 - 10 - ASAHI KASEI [AK4113] 1/fECLK VIH XTI VIL tECLKH tECLKL dECLK = tECLKH x fECLK x 100 = tECLKL x fECLK x 100 1/fMCK1 MCKO1 50%DVDD tMCKH1 tMCKL1 dMCK1 = tMCKH1 x fMCK1 x 100 = tMCKL1 x fMCK1 x 100 1/fMCK2 50%DVDD MCKO2 tMCKH2 tMCKL2 dMCK2 = tMCKH2 x fMCK2 x 100 = tMCKL2 x fMCK2 x 100 1/fs VIH LRCK VIL tLRH tLRL dLCK = tLRH x fs x 100 = tLRL x fs x 100 Figure 3. VIH LRCK VIL tBCK tBLR tLRB tBCKL tBCKH VIH BICK VIL tLRM tBSD 50%DVDD SDTO tDXS tDXH VIH DAUX VIL Figure 4. (Slave mode) MS0349-J-02 2005/08 - 11 - ASAHI KASEI [AK4113] 50%DVDD LRCK tMBLR 50%DVDD BICK tBSD 50%DVDD SDTO tDXS tDXH VIH DAUX VIL Figure 5. (Master mode) VIH CSN VIL tCSS tCCK tCCKL tCCKH VIH CCLK VIL tCDH tCDS CDTI CDTO C1 C0 R/W A4 VIH VIL Hi-Z Figure 6. WRITE/READ (4-wire serial control mode) MS0349-J-02 2005/08 - 12 - ASAHI KASEI [AK4113] tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 VIH D0 VIL Hi-Z CDTO Figure 7. WRITE (4-wire serial mode) VIH CSN VIL VIH CCLK VIL CDTI A1 VIH A0 VIL tDCD Hi-Z CDTO D7 Figure 8. READ D6 D5 50%DVDD 1 (4-wire serial mode) tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI VIL tCCZ CDTO D3 D2 D1 Figure 9. READ D0 50%DVDD 2 (4-wire serial mode) MS0349-J-02 2005/08 - 13 - ASAHI KASEI [AK4113] VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA tSU:STO Start Stop Figure 10. I2C tPW PDN VIL Figure 11. MS0349-J-02 2005/08 - 14 - ASAHI KASEI [AK4113] Non-PCM/DTS-CD AK4113 Non-PCM Dolby “Dolby Digital Data Stream in IEC60958 Interface” 32 Mode Non-PCM NPCM bit “1” 96 sync code 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F NPCM bit “1” 4096 4096 sync code NPCM bit = “0” sync code NPCM bit “0” sync code 2 (Pc: burst information, Pd: length code; Table 17, Table 18 ) DTS-CD DTSCD bit “1” 4096 sync code DTSCD bit = “0” sync code DTSCD bit “0” NPCM bit DTSCD bit OR AUTO bit AK4113 DTS-CD 14bit Sync Word, 16bit Sync Word DTS14 bit, DTS16 bit ON/OFF AUTO bit AUDION bit 14bit Sync Word, 16bit Sync Word DTS-CD OR INT1 pin 216kHz PLL 8kHz (fs) FAST bit 216kHz Figure 12 FAST bit = “1” PLL FAST bit XTL1-0 bits (8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz) 24.576MHz 64kHz FS96 pin “H” 54kHz “L” FAST bit PLL Lock Time 0 Default ≤ (15 ms + 384/fs) 1 ≤ (15 ms + 1/fs) Figure 12. PLL Lock Time (fs: Sampling Frequency) MS0349-J-02 2005/08 - 15 - ASAHI KASEI [AK4113] RX CM0 DAUX CM1 X'tal Mode 3 Mode 2, 3 RX Mode 0 1 CM1 0 0 2 1 3 1 Note: X’tal Mode 2 X’tal CM0 CM1 PLL Unlock PLL X'tal CM0 0 1 UNLOCK PLL X'tal Clock source SDTO ON ON (Note) PLL RX OFF ON X'tal DAUX 0 ON ON PLL RX 0 1 ON ON X'tal DAUX 1 ON ON X'tal DAUX ON: (Power-up), OFF: (Power-Down) (XTL1-0 bit = “11”) OFF Default Table 1. AK4113 bit 2 (MCKO1 pin and MCKO2 pin) MCKO2 pin XMCK 2 1) XMCK bit = “0”, BCU bit = “0” AK4112B, AK4114 X'tal X’tal fs No. 0 1 2 3 OCKS1 0 0 1 1 PLL OCKS1-0 OCKS0 0 1 0 1 MCKO1 pin 256fs 256fs 512fs 128fs Table 2. (Table 2) 96kHz 512fs MCKO2 pin 256fs 128fs 256fs 64fs (MCKO1 pin, MCKO2 pin) 192kHz 256fs,512fs X’tal 256fs 256fs 512fs 128fs fs (max) 108 kHz 108 kHz 54 kHz 216 kHz Default 2) XMCK bit = “1”, BCU bit = “0” MCKO2 pin CM1-0 bit, OCKS1-0 bit DIV bit XMCK bit 1 1 XTI pin MCKO1 pin DIV bit MCKO2 Clock Source 0 X’tal 1 X’tal Table 3. MCKO2 pin MS0349-J-02 CM1-0 bit, OCKS1-0 bit MCKO2 Frequency x1 x 1/2 2005/08 - 16 - ASAHI KASEI [AK4113] AK4113 XTI pin 1) X’tal XTI AK4113 XTO Figure 13. X’tal Note: (typ.10-40pF) 2) XTI External Clock AK4113 XTO Figure 14. 3) XTI/XTO XTI AK4113 XTO Figure 15. OFF MS0349-J-02 2005/08 - 17 - ASAHI KASEI [AK4113] AK4113 XTL1-0 bit X’tal 2 X’tal FS3-0 bits XTL1-0 bits = “11” FS3-0 bits XTL1-0 bit = “10” XTL1 bit XTL0 bit 0 0 0 1 1 0 1 1 X’tal Frequency 11.2896MHz 12.288MHz 24.576MHz Default Table 4. XTL1-0 bit = “11” XTL1-0 bit = “11” Register output fs FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 Note 10. 44.1kHz Reserved 48kHz 32kHz 22.05kHz 11.025kHz 24kHz 16kHz 88.2kHz 8kHz 96kHz 64kHz 176.4kHz 192kHz Clock comparison (Note 10) 44.1kHz ± 3% 48kHz ± 3% 32kHz ± 3% 22.05kHz ± 3% 11.025kHz ± 3% 24kHz ± 3% 16kHz ± 3% 88.2kHz ± 3% 8kHz ± 3% 96kHz ± 3% 64kHz ± 3% 176.4kHz ± 3% 192kHz ± 3% Consumer mode (Note 11) Byte3 Bit3,2,1,0 0000 0001 0010 0011 0100 Professional mode (Note 12) Byte0 Bit7,6 01 Byte4 Bit6,5,4,3 0000 (Others) 10 0000 11 0000 00 1001 0110 00 0001 1000 00 1010 1010 00 0010 1100 1110 00 00 1011 0011 ±3% 8kHz ∼ 216kHz bits = “0001”, “1101” Note 11. Byte3 Bit3-0 FS3-0 bits Note 12. Table 5 FS3-0 FS3-0 bit=“0001” Table 5. MS0349-J-02 2005/08 - 18 - ASAHI KASEI [AK4113] PEM bit (CS12 bit = “0” 2 “1” ) 1 PEM bit CS12 bit = Pre-emphasis 0 1 Table 6. PEM bit OFF ON Pre-emphasis 0 1 Table 7. OFF ON Byte 0 Bits 3-5 ≠ 0X100 0X100 Byte 0 Bits 2-4 ≠110 110 IIR 3 DEAU bit = “1” (32kHz, 44.1kHz, 48kHz) FS3-0 bits (50/15µs DEAU bit = “0” OFF PEM bit = “0” PEM bit 1 1 1 1 0 FS3 bit 0 0 0 x Table 8. PEM bit 1 1 1 1 0 Table 9. DEM1-0 bits FS2 bit FS1 bit 0 0 0 1 0 1 (Others) x x DEM1 bit 0 0 1 1 x ) DEM0 bit 0 1 0 1 x MS0349-J-02 FS0 bit 0 0 1 Mode 44.1kHz 48kHz 32kHz OFF x OFF (DEAU bit = “1”: Default) Mode 44.1kHz OFF Default 48kHz 32kHz OFF (DEAU bit = “0”) 2005/08 - 19 - ASAHI KASEI [AK4113] AK4113 PDN pin PWN bit PDN pin RSTN bit PDN pin “L” PDN pin: “L” RSTN bit ( “0” 00H D0): PWN RSTN “0” PWN bit ( SDTO pin “L” PWN RSTN 00H D1): “0” PLL X’tal MS0349-J-02 2005/08 - 20 - ASAHI KASEI [AK4113] 6 (RX1-6) 2 (RX1 RX5) IPS2-0 bit IPS pin 350mVpp bit, UCE bit Figure 16 ) BCU (Table 12 Block start, C-bit, U-bit IPS2 bit 0 0 0 0 1 1 1 1 Table 10. IPS1 bit 0 0 1 1 0 0 1 1 IPS0 bit 0 1 0 1 0 1 0 1 IPS pin L H INPUT Data RX1 RX2 RX3 RX4 RX5 RX6 No use No use Default INPUT Data RX1 RX5 Table 11. BCU bit 0 1 1 UCE bit MCKO2 pin x (Don’t care) MCKO2 clock output 0 Block start signal output 1 Block start signal output Table 12. B, C, U INT1 pin INT1 output U-bit output C-bit output (B, C, U, V Output timing at RX mode, Master mode) B C (or U,V) C(R191) C(L0) C(R0) C(L1) C(L39) C(R39) C(L40) 1/4fs LRCK SDTO 2 (I S) SDTO 2 (except I S) Block start L191 R191 L0 R0 R38 L39 R39 R190 L191 R191 L0 L38 R39 L39 frame 0 frame 39 “H” Figure 16. B, C, U, V MS0349-J-02 2005/08 - 21 - ASAHI KASEI [AK4113] RX 6 OPS2-0 bits OPS2 bit 0 0 0 0 1 1 1 1 1 TX pin (TX pin) TXE bit OPS1 bit OPS0 bit INPUT Data 0 0 RX1 0 1 RX2 1 0 RX3 1 1 RX4 0 0 RX5 0 1 RX6 1 0 No use 1 1 No use Table 13. Output Data Select MS0349-J-02 Default 2005/08 - 22 - ASAHI KASEI [AK4113] 0.1uF RX 75Ω Coax 75Ω 0.47nF AK4113 Note Figure 17. (Coaxial Note: Coaxial ) RX 50mV Optical Receiver Optical Fiber 470 RX O/E AK4113 Figure 18. Coaxial ( ) RX 2 RX (RX1,5) RX2, 3, 4, 6 “L” “H” AK4113 TX 0.5V+/-20% Figure 19 T1 1:1 R1 TX 75Ω cable R2 DVSS T1 Vdd R1 R2 3.3V 240Ω 150Ω 3.0V 220Ω 150Ω Figure 19. TX MS0349-J-02 2005/08 - 23 - ASAHI KASEI [AK4113] UU 1. 2. 3. 4. CD Q-subcode Subcode sync word (S0,S1) 16 Start bit “1” Q-W 7 bit start bit Start bit 8-16 bits Q-subcode S0 S1 S2 S3 : S97 S0 S1 S2 S3 : 1 0 0 1 1 : 1 0 0 1 1 : “0” bit QINT 2 3 0 0 0 0 Q2 R2 Q3 R3 : : Q97 R97 0 0 0 0 Q2 R2 Q3 R3 : : QINT bit 4 0 0 S2 S3 : S97 0 0 S2 S3 : 5 0 0 T2 T3 : T97 0 0 T2 T3 : 6 0 0 U2 U3 : U97 0 0 U2 U3 : “0” 7 8 0 0 0 0 V2 W2 V3 W3 : : V97 W97 0 0 0 0 V2 W2 V3 W3 : : * 0… 0… 0… 0… : 0… 0… 0… 0… 0… : (*) number of "0" : min=0; max=8. Figure 20. U-bit (CD) Q2 Q3 Q4 CTRL Q5 Q6 Q7 Q8 ADRS Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 TRACK NUMBER INDEX Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49 MINUTE SECOND FRAME Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73 ZERO ABSOLUTE MINUTE ABSOLUTE SECOND Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97 ABSOLUTE FRAME CRC G(x)=x16+x12+x5+1 Figure 21. Addr 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH Register Name Q-subcode Address / Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode ABS Minute Q-subcode ABS Second Q-subcode ABS Frame D7 Q9 Q17 Q D6 Q8 Q16 D5 D4 Q81 Q80 Figure 22. Q-subcode register MS0349-J-02 D3 D2 D1 Q3 Q11 D0 Q2 Q10 Q75 Q74 2005/08 - 24 - ASAHI KASEI [AK4113] INT0, INT1 pin Operation Mode 1) 1. UNLCK “H” INT0/1 pin 9 PLL OFF (Clock “L” : PLL “1” 2. PAR : “1” 3. AUTO : Non-Linear PCM DTS-CD NPCM bit DTSCD bit OR 4. V : 5. AUDION : 6. STC : AUDIO FS3-0 or PEM bit 7. QINT 8. CINT 1 : U-bit Sync U-bit : “1” 1 “1” Sync 1 9. DAT Sync “1” : DAT Start ID DAT “DAT Start ID” DCNT bit = “1” “3840x LRCK” “DAT Start ID” “3841x LRCK” “DAT Start ID” bit = “0” DAT Start ID “1” MS0349-J-02 “1” “1” “1” DCNT 2005/08 - 25 - ASAHI KASEI [AK4113] 1. pin UNLCK, PAR “H” INT0 pin UNLCK 1 0 0 x x x PAR x 1 0 x x x Event AUTO x x x 1 x 0 AUDION x x x x 1 0 OR INT0 pin INT0 INT1 “H” Note 13 “L” “H” Note 14 AUTO, AUDION OR INT1 1024/fs “H” Pin SDTO “L” Previous Data Output V “L” Output Output Note 15 Note 16 “L” Note 13. AUTO, AUDION Note 14. UNLCK, PAR Note 15. UNLCK, PAR INT1 pin “L” or “H” INT0 pin “L” or “H” SDTO pin “L”, “Previous Data”, “Normal Output” Note 16. UNLCK, PAR V pin “L” or “Normal Output” Table 14. ( ) x: Don’t care 2. 1 9 OR INT INT 07H, 08H(DAT bit) 1024/fs (EFH1-0 INT0 bits ) “H” INT1 “L” 07H UNLCK, PAR, AUTO, AUDION, V bit 07H STC, QINT, CINT bit 08H DAT bit 07H, 08H(DAT bit) INT0 pin Pc Pd INT1 pin AUTO, AUDION UNLCK, PAR UNLCK 1 0 x Table 15. Event PAR x 1 x “1” “0” Others x x x SDTO “L” Previous Data Output ( MS0349-J-02 Pin V “L” Output Output TX Output Output Output ) x: Don’t care 2005/08 - 26 - ASAHI KASEI Error (Unlock, Parity,..) [AK4113] (Error) INT0 pin Hold Time (max: 4096/fs) INT1 pin Hold Time = 0 Register (PAR,STC, CINT,QINT) Reset Hold “1” Register (others) Command MCKO,BICK,LRCK (Unlock) READ 07,08H Free Run (fs: around 5kHz) MCKO,BICK,LRCK (except Unlock) SDTO (Unlock) SDTO (Parity error) Previous Data SDTO (others) Vpin (Unlock) Vpin (except Unlock) Normal Operation Figure 23. INT0/1 pin MS0349-J-02 2005/08 - 27 - ASAHI KASEI [AK4113] PDN pin = “L” to “H” Initialize Read (07H,08H) INT0/1 pin=“H” No Yes Release Muting Mute DAC output Read (07H,08H) (Each Error Handling) Read (07H,08H) (Resets registers) No INT0/1 pin =“H” Yes Figure 24. 1 MS0349-J-02 2005/08 - 28 - ASAHI KASEI [AK4113] PDN pin = “L” to “H” Initialize Read (07H,08H) No INT1 pin = “H” Yes Read (07H,08H) and Detect QSUB= “1” (Read Q-buffer) QCRC = “0” No New data is invalid Yes INT1 pin = “L” No Yes New data is valid Figure 25. (Q/CINT) MS0349-J-02 2005/08 - 29 - ASAHI KASEI [AK4113] 8 (Table 16) DIF2-0 MSB 2’s SDTO BICK DAUX Mode0-5 BICK 64fs Mode 6-7 Mode 4-5 BICK fs=48kHz 128fs 20 (Mode0-2) LSB Mode 3-7 4 Aux Figure 26 Parity Error SDTO “L” PLL “0” DAUX SDTO Clock Mode 1 PLL unlock Clock Mode 2 Clock Mode 3 DAUX pin DAUX Mode 5, 7 24 , Left justified SDTO Mode 5, 7 I2S Mode 6-7 Mode4-5 LRCK BICK MCKO1/2 pin sub-frame of IEC60958 0 3 4 preamble 7 8 11 12 27 28 29 30 31 Aux. V U C P LSB MSB MSB LSB 23 0 AK4113 Audio Data (MSB First) Figure 26. Mode DIF2 DIF1 DIF0 0 1 2 3 4 5 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S LRCK I/O H/L O H/L O H/L O H/L O H/L O L/H O 6 1 1 0 24bit, Left justified 24bit, Left justified H/L I 7 1 1 1 24bit, I2S 24bit, I2S L/H I DAUX SDTO BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs (Note 17) 64-128fs (Note 17) I/O O O O O O O I Default I Table 16. Note 17. BICK MS0349-J-02 2005/08 - 30 - ASAHI KASEI [AK4113] LRCK(O) 0 1 2 15 16 17 31 0 1 2 15 16 17 31 0 1 0 1 0 1 BICK (O:64fs) 15 14 1 0 15 14 1 0 SDTO(O) 15:MSB, 0:LSB Rch Data Lch Data Figure 27. Mode 0 LRCK(O) 0 1 2 9 10 12 11 31 0 1 2 9 10 11 12 31 BICK (O:64fs) 23 22 21 20 1 0 23 22 21 20 1 0 SDTO(O) 23:MSB, 0:LSB Rch Data Lch Data Figure 28. Mode 3 LRCK 0 1 2 21 22 24 23 31 0 1 2 21 22 23 24 31 BICK (64fs) 23 22 21 2 1 0 23 22 3 2 1 0 23 22 SDTO(O) 23:MSB, 0:LSB Rch Data Lch Data Figure 29. Mode 4, 6 Mode4 : LRCK, BICK : Output Mode6 : LRCK, BICK : Input LRCK 0 1 2 22 24 23 25 31 0 1 2 21 22 23 24 25 31 0 1 BICK (64fs) SDTO(O) 23 22 21 2 1 23 22 0 3 2 1 0 23 23:MSB, 0:LSB Rch Data Lch Data Figure 30. Mode 5, 7 Mode5 : LRCK, BICK : Output Mode7 : LRCK, BICK : Input MS0349-J-02 2005/08 - 31 - ASAHI KASEI [AK4113] 1. 4 (I2C pin = “L”) 4 I/F (CSN, CCLK, CDTI, CDTO) I/F Chip address (2bits, AK4113 “00” Read/Write (1bit), Register address (MSB first, 5bits) Control Data (MSB first, 8bits) CCLK “↓” “↑” CSN “↑” CSN “↑” Hi-Z CCLK 5MHz (max) PDN pin = “L” ), CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 WRITE Hi-Z CDTO CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 READ Hi-Z CDTO C1,C0: R/W: A4-A0: D7-D0: “L” CCLK “↑” 15 Hi-Z Chip Address (Fixed to “00”) READ/WRITE (0:READ, 1:WRITE) Register Address Control Data Figure 31. 4 CSN D7 D6 D5 D4 D3 D2 D1 D0 I/F 17 MS0349-J-02 2005/08 - 32 - ASAHI KASEI [AK4113] 2. I2C (I2C pin = “H”) AK4113 I2C (max:400kHz) 2-1 IC · 1 · IC IC READ IC WRITE · 2-1-1. SDA SCL “L” · “L” “H” “H” “H” SCL “L” SDA SDA SCL · SCL SDA DATA LINE STABLE : DATA VALID CHANGE OF DATA ALLOWED Figure 32. 2-1-2. SCL “H” SDA “H” · “L” SCL · · “H” · SDA “L” “H” SCL SDA START CONDITION Figure 33. STOP CONDITION · · MS0349-J-02 2005/08 - 33 - ASAHI KASEI [AK4113] 2-1-3. IC 1 SDA IC SDA (HIGH ) “L” AK4113 WRITE AK4113 · READ SDA · SDA AK4113 · AK4113 Clock pulse for acknowledge SCL FROM MASTER 1 8 9 DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER START CONDITION acknowledge Figure 34. 2-1-4. 1 1 · · “00100” 2 0 pin = “1” 7 IC · 1 R/W bit = “0” READ 0 0 1 8 WRITE 0 0 ( CAD1 (CAD1,CAD0 Figure 35. CAD0 5 CAD1 pin, CAD IC ) R/W bit R/W bit R/W ) 1 MS0349-J-02 2005/08 - 34 - ASAHI KASEI [AK4113] 2-2. WRITE R/W bit “0” 3 bit AK4113 2 Don’t care * WRITE WRITE 2 MSB first * * A4 A3 A2 A1 A0 (*: Don’t care) Figure 36. 2 3 8 bit MSB first D7 D6 D5 D4 Figure 37. D3 D2 D1 D0 3 AK4113 1 1CH S T A R T SDA Slave Address · · Register Address(n) 00H Data(n) S T Data(n+x) O P Data(n+1) S P A C K A C K A C K A C K Figure 38. WRITE MS0349-J-02 2005/08 - 35 - ASAHI KASEI [AK4113] 2-3. READ R/W bit “1” · AK4113 READ 1CH AK4113 00H · · · READ 2-3-1. AK4113 · · · (READ WRITE n+1 (R/W bit = “1”) · AK4113 READ · · ) n · · · · 1 1 · S T A R T SDA Slave Address Data(n) Data(n+1) READ S Data(n+x) T O P Data(n+2) S P A C K A C K A C K A C K Figure 39. CURRENT ADDRESS READ 2-3-2. · · · (R/W bit = “1”) · WRITE WRITE READ · · (R/W bit = “0”) AK4113 · READ · (R/W bit = “1”) AK4113 · 1 · READ S T A R T SDA Slave Address S T A R T Word Address(n) S Slave Address Data(n) S Data(n+x) T O P Data(n+1) S A C K P A C K A C K A C K A C K Figure 40. RANDOM READ MS0349-J-02 2005/08 - 36 - ASAHI KASEI [AK4113] Addr 01H Register Name CLK & Power Down Control Format & De-em Control 02H Input/ Output Control 0 03H Input/ Output Control 1 FAST XMCK DIV 04H INT0 MASK MQIT0 MAUT0 MCIT0 MULK0 MV0 MSTC0 MAUD0 MPAR0 05H INT1 MASK MQIT1 MAUT1 MCIT1 MULK1 MV1 MSTC1 MAUD1 MPAR1 06H DAT Mask & DTS Detect 07H 00H D7 D6 D5 D4 D3 D2 D1 D0 CS12 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN V/TX DIF2 DIF1 DIF0 DEAU DEM1 DEM0 0 0 XTL1 XTL0 UCE TXE OPS2 OPS1 OPS0 EFH1 EFH0 IPS2 IPS1 IPS0 0 0 0 DCNT DTS16 DTS14 MDAT1 MDAT0 Receiver status 0 QINT AUTO CINT UNLCK V STC AUDION PAR 08H Receiver status 1 FS3 FS2 FS1 FS0 PEM DAT DTSCD NPCM 09H Receiver status 2 0 0 0 0 0 0 QCRC CCRC 0AH RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 0BH RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0CH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0DH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0EH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 0FH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 10H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 11H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 12H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 13H Q-subcode Address/Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 14H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 15H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 16H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 17H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 18H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 19H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 1AH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 1BH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1CH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 : PDN pin “L” RSTN bit “0” PWN bit “0” 1DH 1FH MS0349-J-02 2005/08 - 37 - ASAHI KASEI [AK4113] Reset & Initialize Addr Register Name 00H CLK & Power Down Control R/W Default D7 CS12 R/W 0 D6 BCU R/W 0 D5 CM1 R/W 0 D4 CM0 R/W 0 D3 D2 OCKS1 OCKS0 R/W R/W 0 0 D1 PWN R/W 1 D0 RSTN R/W 1 RSTN: 0: 1: & (Default) 0: 1: (Default) PWN: OCKS1-0: CM1-0: BCU: (See Table 2) (See Table 1) (B) , C, U 0: Disable (Default) 1: Enable (See Table 12) CS12: 0: Channel 1 (Default) 1: Channel 2 C-bit, AUDION, PEM, FS3-0, Pc, Pd channel 1 Format & De-emphasis Control Addr Register Name 01H Format & De-em Control R/W Default D7 V/TX R/W 0 D6 DIF2 R/W 1 DEM1-0: 32, 44.1, 48kHz DEAU: 0: Disable 1: Enable (Default) DIF2-0: V/TX: V/TX Output Select 0: Validity Flag Output. (Default) This output is updated every fs cycle. 1: TX MS0349-J-02 D5 DIF1 R/W 1 D4 DIF0 R/W 0 D3 DEAU R/W 1 D2 DEM1 R/W 0 D1 DEM0 R/W 1 D0 0 RD 0 (Table 9) (Table 16; Default: “110”) 2005/08 - 38 - ASAHI KASEI [AK4113] Input/Output Control Addr Register Name 02H Input/ Output Control 0 R/W Default OPS2-0: TXE: TX D7 0 RD 0 (TX) D6 XTL1 R/W 0 D5 XTL0 R/W 0 D4 UCE R/W 0 D3 TXE R/W 1 D2 OPS2 R/W 0 D1 OPS1 R/W 0 D0 OPS0 R/W 0 D3 D2 IPS2 R/W 0 D1 IPS1 R/W 0 D0 IPS0 R/W 0 (See Table 13; Default: “000”) 0: TX pin “L” 1: (Default) UCE: C-bit, U-bit ( See Table 12, Default: “0”) XTL1-0: (See Table 4, Default: 00) Addr Register Name 03H Input/ Output Control 1 R/W Default D7 EFH1 R/W 0 D6 EFH0 R/W 1 D5 FAST R/W 0 D4 XMCK DIV R/W 0 R/W 0 IPS2-0: (See Table 10; Default: “000”) DIV: X’tal MCKO2 (See Table 3) 0: x1 (Default) 1: x 1/2 XMCK: MCKO2 (See Table 3) 0: CM1-0 bits, OCKS1-0 bits (Default) 1: X’tal FAST: PLL Lock Time 0: ≤ (15ms + 384/fs) (Default) 1: ≤ (15ms + 1/fs) EFH1-0: INT0 pin 00: 512/fs 01: 1024/fs (Default) 10: 2048/fs 11: 4096/fs MS0349-J-02 2005/08 - 39 - ASAHI KASEI [AK4113] Mask Control for INT0 Addr Register Name 04H INT0 MASK R/W Default D7 D6 D5 D4 MQIT0 MAUT0 MCIT0 MULK0 R/W R/W R/W R/W 1 1 1 0 D3 MV0 R/W 1 D2 D1 D0 MSTC0 MAUD0 MPAR0 R/W R/W R/W 1 1 0 MPAR0: Mask enable for PAR bit 0: Mask disable (Default) 1: Mask enable MAUD0: Mask enable for AUDION bit 0: Mask disable 1: Mask enable (Default) MSTC0: Mask enable for STC bit 0: Mask disable 1: Mask enable (Default) MV0: Mask enable for V bit 0: Mask disable 1: Mask enable (Default) MULK0: Mask enable for UNLCK bit 0: Mask disable (Default) 1: Mask enable MCIT0: Mask enable for CINT bit 0: Mask disable 1: Mask enable (Default) MAUT0: Mask enable for AUTO bit 0: Mask disable 1: Mask enable (Default) MQIT0: Mask enable for QINT bit 0: Mask disable 1: Mask enable (Default) “1” INT0 pin MS0349-J-02 2005/08 - 40 - ASAHI KASEI [AK4113] Mask Control for INT1 Addr Register Name 05H INT1 MASK R/W Default D7 D6 D5 D4 MQIT1 MAUT1 MCIT1 MULK1 R/W R/W R/W R/W 1 0 1 1 D3 MV1 R/W 1 D2 D1 D0 MSTC1 MAUD1 MPAR1 R/W R/W R/W 1 0 1 MPAR1: Mask enable for PAR bit 0: Mask disable 1: Mask enable (Default) MAUD1: Mask enable for AUDION bit 0: Mask disable (Default) 1: Mask enable MSTC1: Mask enable for STC bit 0: Mask disable 1: Mask enable (Default) MV1: Mask enable for V bit 0: Mask disable 1: Mask enable (Default) MULK1: Mask enable for UNLCK bit 0: Mask disable 1: Mask enable (Default) MCIT1: Mask enable for CINT bit 0: Mask disable 1: Mask enable (Default) MAUT1: Mask enable for AUTO bit 0: Mask disable (Default) 1: Mask enable MQIT1: Mask enable for QINT bit 0: Mask disable 1: Mask enable (Default) “1” INT1 pin DAT Mask & DTS Detect Addr Register Name 06H DAT Mask & DTS Detect R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 MDAT0: Mask enable for DAT bit 0: Mask disable 1: Mask enable (Default) “1” DAT MDAT1: Mask enable for DAT bit 0: Mask disable 1: Mask enable (Default) “1” DAT DTS14: DTS-CD 14bit Sync Word Detect 0: Disable 1: Enable (Default) DTS16: DTS-CD 16bit Sync Word Detect 0: Disable 1: Enable (Default) DCNT: DAT Start ID Counter 0: Disable 1: Enable (Default) MS0349-J-02 D4 DCNT R/W 1 D3 DTS16 R/W 1 D2 D1 D0 DTS14 MDAT1 MDAT0 R/W R/W R/W 1 1 1 INT0 pin INT1 pin 2005/08 - 41 - ASAHI KASEI [AK4113] Receiver Status 0 Addr Register Name 07H Receiver status 0 R/W Default D7 QINT RD 0 D6 AUTO RD 0 D5 CINT RD 0 D4 UNLCK RD 0 D3 V RD 0 D2 STC RD 0 D1 AUDION RD 0 D0 PAR RD 0 PAR: 0: No Error 1: Error PAR bit “1” AUDION: Audio 0: Audio 1: Non Audio STC: 0: No detect 1: Detect FS3-0 bits or PEM bit STC bit “1” V: 0: Valid 1: Invalid UNLCK: PLL 0: Lock 1: Unlock CINT: 0: No change 1: Changed Addr = 0AH(Channel Status Addr) C-bit “1” AUTO: Non-PCM 0: No detect 1: Detect QINT: Q 0: No change 1: Changed Addr = 13H( ) 1CH( ) STC, QINT, CINT, PAR bit Addr=07H 0EH Channel Status Q-subcode Addr “1” READ MS0349-J-02 2005/08 - 42 - ASAHI KASEI [AK4113] Receiver Status 1 Addr Register Name 08H Receiver status 1 R/W Default D7 FS3 RD 0 D6 FS2 RD 0 NPCM: Non-PCM 0: No detect 1: Detect DTSCD: DTC-CD 0: No detect 1: Detect DAT: DAT Start ID Detect 0: No detect 1: Detect DAT bit Addr = 08H PEM: Pre-emphasis Detect 0: OFF 1: ON FS3-0: D5 FS1 RD 0 D4 FS0 RD 1 D3 PEM RD 0 D2 DAT RD 0 D1 DTSCD RD 0 D0 NPCM RD 0 D5 0 RD 0 D4 0 RD 0 D3 0 RD 0 D2 0 RD 0 D1 QCRC RD 0 D0 CCRC RD 0 READ (Table 5) Receiver Status 2 Addr Register Name 09H Receiver status 2 R/W Default D7 0 RD 0 CCRC: D6 0 RD 0 CRCC 0: No error 1: Error CS12 bit QCRC: Q CRCC 0: No error 1: Error MS0349-J-02 2005/08 - 43 - ASAHI KASEI [AK4113] Receiver Channel Status Addr 0AH 0BH 0CH 0DH 0EH Register Name RX Channel Status Byte 0 RX Channel Status Byte 1 RX Channel Status Byte 2 RX Channel Status Byte 3 RX Channel Status Byte 4 R/W Default D7 CR7 CR15 CR23 CR31 CR39 (192 D5 CR5 CR13 CR21 CR29 CR37 D4 CR4 CR12 CR20 CR28 CR36 D3 CR3 CR11 CR19 CR27 CR35 D2 CR2 CR10 CR18 CR26 CR34 D1 CR1 CR9 CR17 CR25 CR33 D0 CR0 CR8 CR16 CR24 CR32 D2 PC2 PC10 PD2 PD10 D1 PC1 PC9 PD1 PD9 D0 PC0 PC8 PD0 PD8 D2 Q4 Q12 Q20 Q28 Q36 Q44 Q52 Q60 Q68 Q76 D1 Q3 Q11 Q19 Q27 Q35 Q43 Q51 Q59 Q67 Q75 D0 Q2 Q10 Q18 Q26 Q34 Q42 Q50 Q58 Q66 Q74 RD Not initialized CR39-0: 1 D6 CR6 CR14 CR22 CR30 CR38 ) Byte 4-0 40 bit Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams Addr 0FH 10H 11H 12H Register Name Burst Preamble Pc Byte 0 Burst Preamble Pc Byte 1 Burst Preamble Pd Byte 0 Burst Preamble Pd Byte 1 R/W Default D7 PC7 PC15 PD7 PD15 D6 PC6 PC14 PD6 PD14 PC15-0: PD15-0: Pc Byte 0, 1 Pd Byte 0, 1 D5 PC5 PC13 PD5 PD13 D4 PC4 PC12 PD4 PD12 D3 PC3 PC11 PD3 PD11 RD Not initialized Q-subcode Buffer Addr 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH Register Name Q-subcode Address / Control Q-subcode Track Q-subcode Index Q-subcode Minute Q-subcode Second Q-subcode Frame Q-subcode Zero Q-subcode ABS Minute Q-subcode ABS Second Q-subcode ABS Frame R/W Default D7 Q9 Q17 Q25 Q33 Q41 Q49 Q57 Q65 Q73 Q81 D6 Q8 Q16 Q24 Q32 Q40 Q48 Q56 Q64 Q72 Q80 D5 Q7 Q15 Q23 Q31 Q39 Q47 Q55 Q63 Q71 Q79 D4 Q6 Q14 Q22 Q30 Q38 Q46 Q54 Q62 Q70 Q78 D3 Q5 Q13 Q21 Q29 Q37 Q45 Q53 Q61 Q69 Q77 RD Not initialized Q2-81: Q-subcode ( Figure 20 and Figure 21 ) U bit 1 80bit MS0349-J-02 2005/08 - 44 - ASAHI KASEI [AK4113] Non-PCM sub-frame of IEC60958 0 3 4 preamble 7 8 11 12 Aux. 27 28 29 30 31 LSB MSB V U C P 16 bits of bitstream 0 Pa Pb Pc Pd 15 Burst_payload stuffing repetition time of the burst Figure 41. IEC60958 Preamble word Pa Pb Pc Pd Length of field 16 bits 16 bits 16 bits 16 bits Table 17. Contents sync word 1 sync word 2 Burst info Length code Bits of Pc Value Contents 0-4 data type NULL data Dolby AC-3 data reserved PAUSE MPEG-1 Layer1 data MPEG-1 Layer2 or 3 data or MPEG-2 without extension MPEG-2 data with extension MPEG-2 AAC ADTS MPEG-2, Layer1 Low sample rate MPEG-2, Layer2 or 3 Low sample rate reserved DTS type I DTS type II DTS type III ATRAC ATRAC2/3 reserved reserved, shall be set to “0” error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors data type dependent info bit stream number, shall be set to “0” Table 18. Pc 5, 6 7 8-12 13-15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 0 0 1 0 Value 0xF872 0x4E1F see Table 18 numbers of bits Repetition time of burst in IEC60958 frames MS0349-J-02 ≤4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 2005/08 - 45 - ASAHI KASEI [AK4113] Non-PCM 1) Non-PCM 4096 PDN pin Bit stream Pa Pb Pc1 Pd1 Pa Pb Pc2 Pd2 Pa Pb Pc3 Pd3 Repetition time >4096 frames AUTO bit Pc Register “0” Pd Register “0” Pc1 Pc2 Pd1 Pd2 Figure 42. 2) Non-PCM Pc3 Pd3 1 (MULK0 bit = “0” ) INT0 hold time INT0 pin PLL Lock Time Bit stream Pa Pb Pc1 Pd1 Stop Pa Pb Pcn Pdn 2~3 Syncs (B,M or W) AUTO bit Pc Register Pd Register <Repetition time Pc0 Pc1 Pd0 Pcn Pd1 Figure 43. Pdn 2 MS0349-J-02 2005/08 - 46 - ASAHI KASEI [AK4113] Figure 44 3.3V Supply 10u 0.1u + 1 DVDD CDTO 30 2 DVSS CDTI 29 3 TVDD CCLK 28 4 V/TX CSN 27 5 XTI MCKO1 26 6 XTO MCKO2 25 7 PDN DAUX 24 8 R BICK 23 9 AVDD SDTO 22 10 AVSS LRCK 21 11 RX1 INT0 20 12 RX2 I2C 19 13 RX3 P/SN 18 14 RX4 INT1 17 15 RX5 RX6 16 3.3~5V Supply + 0.1u 10u C C 15k±5% 3.3V Supply 10u + 0.1u (see Figure 15,16) AK4113 Microcontroller DSP and AD/DA Figure 44. Typical Connection Diagram (4-wire serial control mode) Note : - XTL1-0 bits -C - AVSS, DVSS - Table 4 R pin MS0349-J-02 2005/08 - 47 - ASAHI KASEI [AK4113] PACKAGE 30pin VSOP (Unit: mm ) *9.7±0.1 0.3 30 1.5MAX 16 15 1 0.22±0.1 7.6±0.2 5.6±0.1 A 0.15 +0.10 -0.05 0.65 0.12 M 0.45±0.2 +0.10 0.08 0.10 -0.05 1.2±0.10 Detail A NOTE: Dimension "*" does not include mold flash. MS0349-J-02 2005/08 - 48 - ASAHI KASEI [AK4113] MARKING AKM AK4113VF XXXBYYYYC XXXBYYYYC: XXXB: YYYYC: Date (YY/MM/DD) 04/10/20 05/03/08 05/08/11 Revision 00 01 02 Date code identifier Lot number (X : Digit number, B : Alpha character ) Assembly date (Y : Digit number C : Alpha character) Reason Page Contents 3, 4, 7 4 Pin Name: #14; RX4/IPS2 Æ RX4/DIF2 INT0 pin I/O: “I” Æ “O” • • • • • • MS0349-J-02 2005/08 - 49 -