SONY CXB1595AN

CXB1595AN
Fibre Channel Repeater
Description
The CXB1595AN is a clock and data recovery IC
for fibre channel 1.0625Gbaud with a built-in PLL.
This IC incorporates a port bypass circuit and is
suitable for disk array and FC-AL HUB, etc.
Features
• Conforms to ANSI X3T11 Fibre Channel standard
• Single 3.3V power supply
• Low power consumption: 380mW (Typ.)
• Low jitter
• PLL lock detection circuit
• Port bypass circuit
• Small plastic package (30-pin SSOP)
30 pin SSOP (Plastic)
Structure
Bipolar silicon monolithic IC
Applications
• Fibre channel arbitrated loop 1.0625Gbaud HUB
• Disk array
Pin Configuration
REFCLK
1
30 CDR_SELN
LKDT
2
29 DIAG_SELN
VEET
3
28 LOOP_SELN
DIAG_OUT
4
27 DIAG_IN
DIAG_OUTN
5
26 DIAG_INN
VCCE
6
25 VCCG
LOOP_IN
7
24 LOOP_OUT
LOOP_INN
8
23 LOOP_OUTN
VEEG
9
22 VCCE
PORT_IN 10
PORT_INN 11
LKREFN 12
21 PORT_OUT
20 PORT_OUTN
19 VEEE
VEEP 13
18 PORT_SEL0N
LPF1 14
17 PORT_SEL1N
LPF2 15
16 VCCP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99632-PS
CXB1595AN
Block Diagram
CDR_SELN
53.125MHz
REFCLK
(TTL/I)
(TTL/I)
DIAG_SELN
S
LKDT
(TTL/O)
0
Y
1
DIAG_OUT
(TTL/I)
LOOP_SELN
(TTL/I)
1.0625Gboud
DIAG_OUTN
(ECL/O)
DIAG_IN
DIAG_INN
(ECL/I)
S
0
LOOP_OUT
LOOP_IN
Y
1.0625Gboud
1
Frequency
Detector
Unlock
Detector
Recovered clock
LOOP_INN
(ECL/I)
Low
LOOP_OUTN
(ECL/O)
11
00 Y
PORT_OUT
PORT_OUTN
1
Y
PORT_IN
PORT_INN
(ECL/I) 1.0625Gboud
Clock and Data
Recovery
Retimed data
01
(ECL/O)
10
S1 S0
0
S
PORT_SEL0N
LKREFN
(TTL/I)
(TTL/I)
PORT_SEL1N
(TTL/I)
LPF1
LPF2
–2–
CXB1595AN
Pin Description
Pin
No.
Symbol
Type
Equivalent circuit
Description
VCCG
1
REFCLK
Input
TTL
Reference clock.
This pin is used for the PLL
to take the frequency. Input
53.125MHz to this pin.
TTL_IN
VEET
VEEG
VCCE
2
LKDT
TTL_OUT
Output
TTL
PLL lock detection signal
output.
Outputs high level when PLL
is locked to the serial data.
Outputs low level when
LKREFN is in the low level or
the serial data isn't locked to
the serial input data.
VEET
3
VEET
Ground for TTL I/O: 0V.
Ground
VCCE
4
5
DIAG_OUT
DIAG_OUTN
ECL_OUT
Output
ECL
Differential serial data output.
ECL_OUTN
VEEE
6
VCCE
Power supply for ECL l/O:
3.3V ± 5%.
Power
supply
VCCE
VCCG
ECL_IN
7
8
LOOP_IN
LOOP_INN
Input
ECL
VCCE – 1.3V
Differential serial data input.
ECL_INN
VEEE
VEEG
–3–
CXB1595AN
Pin
No.
9
Symbol
VEEG
Type
Equivalent circuit
Ground for internal logic Gate:
0V.
Ground
VCCE
VCCG
ECL_IN
10
11
PORT_IN
PORT_INN
Description
Input
ECL
VCCE – 1.3V
Differential serial data input.
ECL_INN
VEEE
VEEG
VCCG
12
LKREFN
Input
TTL
Lock to reference.
An active low input.
LKREFN causes the PLL lock
to the REFCLK.
TTL_IN
VEET
13
VEEP
VEEG
Ground
Ground for PLL: 0V.
VCCP
14
15
LPF1
LPF2
External
circuit
node
LPF1
LPF2
Connect to external loop filter.
VEEP
16
VCCP
Power supply for PLL:
3.3V ± 5%.
Power
supply
VCCG
17
18
PORT_SEL1N
PORT_SEL0N
Input
TTL
TTL_IN
Selection for PORT_OUT.
VEET
VEEG
–4–
CXB1595AN
Pin
No.
19
Symbol
VEEE
Type
Equivalent circuit
Description
Ground
Ground for ECL I/O: 0V.
VCCE
20
21
PORT_OUTN
PORT_OUT
ECL_OUT
Output
ECL
Differential serial data output.
ECL_OUTN
VEEE
22
VCCE
Power supply for ECL I/O:
3.3V ± 5%.
Power
supply
VCCE
23
24
LOOP_OUTN
LOOP_OUT
ECL_OUT
Output
ECL
Differential serial data output.
ECL_OUTN
VEEE
25
VCCG
Power
supply
Power supply for internal logic
gate: 3.3V ± 5%.
VCCE
VCCG
ECL_IN
26
27
DIAG_INN
DIAG_IN
Input
ECL
VCCE – 1.3V
Differential serial data input.
ECL_INN
VEEE
VEEG
VCCG
28
LOOP_SELN
29
DIAG_SELN
30
CDR_SELN
Input
TTL
Selection for LOOP_OUT.
See table 9.
Selection for DIAG_OUT.
See table 9.
TTL_IN
VEET
VEEG
–5–
Selection for CDR input.
See table 9.
CXB1595AN
Electrical Characteristics
Table 1. Absolute Maximum Ratings
Item
Symbol
(VEEE, VEET, VEEG, VEEP = GND)
Min.
Typ.
Max.
Unit
Power supply voltage
VCC
–0.3
4
V
TTL DC input voltage
VI_T
–0.5
5.5
V
ECL DC input voltage
VI_E
VCC – 2
VCC
V
ECL input voltage between
differential signal
II_E
–4
4
V
TTL output current (High)
IOH_T
–20
0
mA
TTL output current (Low)
IOL_T
0
20
mA
ECL output current
IO_E
–30
0
mA
Storage temperature
Tstg
–65
150
°C
Comments
Table 2. Recommended Operating Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
3.3
3.465
V
70
°C
Power supply voltage
VCC
3.135
Ambient temperature
Ta
0
–6–
Comments
CXB1595AN
Table 3. DC Characteristics
Item
(Over recommended operating conditions)
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input high voltage (TTL)
VIH_T
2.8
5.5
V
Input low voltage (TTL)
VIL_T
0
0.8
V
Input high current (TTL)
IIH_T
VIN = VCC
20
µA
Input low current (TTL)
IIL_T
VIN = 0
Output high voltage (TTL)
VOH_T
IOH = –0.4mA
Output low voltage (TTL)
VOL_T
IOL = 2mA
Differential input voltage swing
VIS_E
Differential output voltage peak-to-peak
–400
µA
2.2
VCC
V
0
0.5
V
AC coupling input
200
1000
mV
VOS_E
50Ω to Vcc – 2V
1200
2000
mV
Supply current
ICC
Outputs open
154
mA
Power dissipation
PD
Outputs open
534
mW
Table 4. AC Characteristics
Item
(Over recommended operating conditions)
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input TTL rise time of REFCLK
Tir_RC
0.8 to 2.0V
4.8
ns
Input TTL fall time of REFCLK
Tif_RC
2.0 to 0.8V
4.8
ns
Output TTL rise time
Tor_T
0.8 to 2.0V, CL = 10pF
3.5
ns
Output TTL fall time
Tof_T
2.0 to 0.8V, CL = 10pF
3.5
ns
Output ECL rise time
Tor_E
20 to 80%, CL = 2pF
400
ps
Output ECL fall time
Tof_E
20 to 80%, CL = 2pF
400
ps
Serial data rate
SDR
1.0UI = 941ps
REFCKL frequency tolerance
RC_TOL 53.125MHz REFCLK
REFCKL duty cycle tolerance
RC_DC
Total Jitter tolerance peak-to-peak,
10E-12BER
TJT
∗1
Deterministic jitter output peak-to-peak
DJgen
±K28.5 serial data,
637kHz HPF ∗1
Random jitter output, rms
RJgen
Jitter transfer peaking
JXFR_PK
–100
Bit sync time
Frequency acquisition time
Tfa
∗1
Lock detect range
LDR
Frequency difference
between recovered
Clock and REFCLK
PPM
10
%
UI
0.07
UI
0.0125 UIrms
0.2
–2
dB
kHz
640
∗1 The values of LPF R/2 is 200Ω and LPF C is 0.022µF.
∗2 CXB1595AN starts Bit synchronization in 10µs after LKREFN changed to high.
–7–
100
0.7
00110011 serial data,
637kHz HPF ∗1
00110011 input ∗1
JXFR_3dB 00110011 input ∗1
Tbs
FC Idle pattern ∗1, ∗2
Jitter transfer 3dB bandwidth
MBd
1062.5
2500
bit
800
µs
2
%
CXB1595AN
Table 5. Function of LOOP_OUT
LOOP_SELN
LOOP_OUT
H
Recovered Data
L
LOOP_IN
Table 6. Function of DIAG_OUT
DIAG_SELN
DIAG_OUT
H
Recovered Data
L
DIAG_IN
Table 7. Function of PORT_OUT
PORT_SEL0N
PORT_SEL1N
PORT_OUT
H
H
Low
L
H
Recovered Data
H
L
DIAG_IN
L
L
LOOP_IN
Table 8. Function of Recovered data
PORT_SEL0N
PORT_SEL1N
CDR_SELN
Recovered Data
H
H
H
Low
L
H
H
—
H
L
H
DIAG_IN
L
L
H
LOOP_IN
H
H
L
PORT_IN
L
H
L
PORT_IN
H
L
L
PORT_IN
L
L
L
PORT_IN
–8–
CXB1595AN
Table 9. Selection of Signal
PORT_SEL0N PORT_SEL1N LOOP_SELN DIAG_SELN CDR_SELN PORT_OUT LOOP_OUT DIAG_OUT
1
1
1
1
1
Low
Low
Low
0
1
1
1
1
Low
Low
Low
1
0
1
1
1
Low
DIAG_IN
DIAG_IN
0
0
1
1
1
Low
LOOP_IN
LOOP_IN
1
1
0
1
1
Low
LOOP_IN
Low
0
1
0
1
1
Low
LOOP_IN
Low
1
0
0
1
1
Low
LOOP_IN
DIAG_IN
0
0
0
1
1
Low
LOOP_IN
LOOP_IN
1
1
1
0
1
Low
Low
DIAG_IN
0
1
1
0
1
Low
Low
DIAG_IN
1
0
1
0
1
Low
DIAG_IN
DIAG_IN
0
0
1
0
1
Low
LOOP_IN
DIAG_IN
1
1
0
0
1
Low
LOOP_IN
DIAG_IN
0
1
0
0
1
Low
LOOP_IN
DIAG_IN
1
0
0
0
1
Low
LOOP_IN
DIAG_IN
0
0
0
0
1
Low
LOOP_IN
DIAG_IN
1
1
1
1
0
Low
PORT_IN
PORT_IN
0
1
1
1
0
PORT_IN
PORT_IN
PORT_IN
1
0
1
1
0
DIAG_IN
PORT_IN
PORT_IN
0
0
1
1
0
LOOP_IN
PORT_IN
PORT_IN
1
1
0
1
0
Low
LOOP_IN
PORT_IN
0
1
0
1
0
PORT_IN
LOOP_IN
PORT_IN
1
0
0
1
0
DIAG_IN
LOOP_IN
PORT_IN
0
0
0
1
0
LOOP_IN
LOOP_IN
PORT_IN
1
1
1
0
0
Low
PORT_IN
DIAG_IN
0
1
1
0
0
PORT_IN
PORT_IN
DIAG_IN
1
0
1
0
0
DIAG_IN
PORT_IN
DIAG_IN
0
0
1
0
0
LOOP_IN
PORT_IN
DIAG_IN
1
1
0
0
0
Low
LOOP_IN
DIAG_IN
0
1
0
0
0
PORT_IN
LOOP_IN
DIAG_IN
1
0
0
0
0
DIAG_IN
LOOP_IN
DIAG_IN
0
0
0
0
0
LOOP_IN
LOOP_IN
DIAG_IN
∗ Boldface type is recovered data.
–9–
CXB1595AN
Application Circuit
1. Power and loop filter
3.3V
22µF
GND
1
REFCLK
CDR_SELN 30
2
LKDT
DIAG_SELN 29
3
VEET
LOOP_SELN 28
4
DIAG_OUT
5
DIAG_OUTN
6
VCCE
7
LOOP_IN
8
LOOP_INN
9
VEEG
DIAG_IN 27
DIAG_INN 26
VCCG 25
LOOP_OUT 24
LOOP_OUTN 23
VCCE 22
10 PORT_IN
11 PORT_INN
PORT_OUT 21
PORT_OUTN 20
12 LKREFN
200Ω
VEEE 19
13 VEEP
PORT_SEL0N 18
14 LPF1
PORT_SEL1N 17
0.022µF
15 LPF2
VCCP
16
200Ω
VCC
VCC
0.1µF
0.1µF
VEE
VEE
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
2. Serial input and output
VCC = 3.3V
VEE = GND
ZO = 75Ω
0.01µF
150Ω
150Ω
0.01µF
150Ω
CXB1595AN output
CXB1595AN input
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 10 –
CXB1595AN
Description of Operation
1. Clock and data recovery
The PLL in the clock and data recovery block must be frequency locked to the external REFCLK before locking
to the data.
The LKREFN pin is used to lock the frequency. When the LKREFN pin is low, the PLL frequency is locked to
the external REFCLK and when high, it is locked to the input serial data. Up to 800µs is required to lock the
frequency.
2. Frequency detector
The frequency detector constantly monitors the offset between the clock obtained by 1/20 frequency-dividing
the recovered clock and the external REFCLK. It outputs high when this offset is less than 1.6%, and low when
this offset is 1.6% or more.
Note on Operation
The following values are recommended for the external resistors and capacitor used as the loop filter.
200Ω
14
0.022µF
15
200Ω
– 11 –
CXB1595AN
Example of Jitter Transfer Measurement
Jitter Transfer
5
Jitter ratio [dB]
0
–5
–10
–15
–20
100
Input data = 00110011...
Loop filter resistor = 200Ω
Loop filter capacitor = 0.022µF
1000
104
105
Frequency [Hz]
– 12 –
106
107
CXB1595AN
Example of Representative Characteristics
PORT-OUT Output Eye Pattern
(1.0625Gbps Retimed data)
X: 200ps/div
Y: 200mV/div
Example of Random Jitter Measurement
X: 100ps/div
Y: 200mV/div
Input data = 010101...
Random Jitter = 9.1ps (rms)
– 13 –
CXB1595AN
Package Outline
Unit: mm
30PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
∗9.7 ± 0.1
0.10
1
A
15
0.65
+ 0.1
b=0.22 – 0.05
(0.15)
(0.22)
0.5 ± 0.2
0.1 ± 0.1
b=0.22 ± 0.03
+ 0.03
0.15 – 0.01
0.13 M
+ 0.05
0.15 – 0.02
b
7.6 ± 0.2
16
∗5.6 ± 0.1
30
DETAIL B : SOLDER
DETAIL B : PALLADIUM
NOTE: Dimension “∗” does not include mold protrusion.
0° to 10°
PACKAGE STRUCTURE
DETAIL A
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
SSOP-30P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
SSOP030-P-0056
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.1g
– 14 –