データシート

ASAHI KASEI
[AK4589]
AK4589
2/8-Channel Audio CODEC with DIR
AK4589
2ch ADC
8ch DAC
1
24bit CODEC
DAC
ADC
AK4589
102dB
ADC
192kHz 24 bit
DIR
8
AK4589 AK4588
114dB
(AC-3)
DAC
AK4589
*
(DIR)
(DIT)
Non-PCM
(AC-3)
Dolby Laboratories
ADC, DAC
• 2ch 24bit ADC
-64
:
96kHz
-S/(N+D): 92dB
, S/N: 102dB
HPF
2
S,
TDM
-I/F
:
,I
• 8ch 24bit DAC
-128
:
192kHz
-24
8
SCF
-S/(N+D): 94dB
, S/N: 114dB
-I/F
:
,
(20bit, 24bit), I2S, TDM
(128
, 0.5dB
(32kHz, 44.1kHz, 48kHz
)
•
•
: 256fs, 384fs, 512fs (fs=32kHz ∼ 48kHz)
128fs, 192fs, 256fs (fs=64kHz ∼ 96kHz)
128fs (fs=120kHz~ 192kHz)
MS0339-J-00
)
2004/09
-1-
ASAHI KASEI
[AK4589]
DIR,DIT
• AES3, IEC60958, S/PDIF, EIAJ CP1201
•
PLL
• PLL
: 32kHz ∼ 192kHz
• PLL/X'tal
•
8
•
2
(
or
)
•
•
(32kHz, 44.1kHz, 48kHz, 96kHz)
•
- Non-PCM
- DTS-CD
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
- Unlock & Parity Error
- Validity
• 24
•
I/F:
/
•
40
• Non-PCM
Pc, Pd
• CD Q-subcode
• 64fs/128fs/256fs/512fs
TTL
I/F
)
µP I/F
(I2C, 4
: 4.75 ∼ 5.25V
: 2.7 ∼ 5.25V
: 80pin LQFP(0.5mm pitch)
AK4588
(
)
MS0339-J-00
2004/09
-2-
ASAHI KASEI
[AK4589]
PVSS PVDD
R
XTI
XTO
RX0
RX1
RX2
RX3
RX4
RX5
X'tal
Oscillator
Clock
Recovery
8 to 3
Input
Clock
MCKO1
Generator
MCKO2
Selector
DEM
RX6
RX7
DAIF
Audio
I/F
Decoder
LRCK2
BICK2
SDTO2
TX0
DAUX2
PDN
TX1
AVDD
AVSS
DVDD
I2C
DIT
DVSS
TVDD
VIN
AC-3/MPEG
Detect
Error &
STATUS
Detect
Q-subcode
buffer
ADC
LIN
RIN
SCF
HPF
HPF
DAC
DATT
DEM
MCLK
MCLK
LRCK
BICK
LRCK1
BICK1
SCF
DAC
DATT
DEM
SCF
DAC
DATT
DEM
SCF
DAC
DATT
DEM
SCF
DAC
DATT
DEM
ROUT3+
ROUT3-
SCF
DAC
DATT
DEM
LOUT4+
LOUT4-
SCF
DAC
DATT
DEM
ROUT4+
SCF
DAC
DATT
DEM
ROUT1LOUT2+
LOUT2ROUT2+
ROUT2LOUT3+
LOUT3-
ROUT4-
Audio
I/F
ADC
LOUT1ROUT1+
CDTO
CDTI
INT0
INT1
B,C,U,
VOUT
LOUT1+
µP I/F
CSN
CCLK
DAUX1
Format
Converter
SDOUT
SDTO1
SDIN1
SDIN2
SDIN3
SDIN4
MS0339-J-00
SDTI1
SDTI2
SDTI3
SDTI4
2004/09
-3-
ASAHI KASEI
-10 ∼ +70°C
80pin LQFP(0.5mm pitch)
(Top View)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
TEST1
RX1
NC
RX0
AVSS
AVDD
VREFH
VCOM
RIN
LIN
ROUT1+
ROUT1LOUT1+
LOUT1ROUT2+
ROUT2LOUT2+
LOUT2ROUT3+
ROUT3-
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CCLK/SCL
CDTI/SDA
CSN
DAUX1
SDTI4
SDTI3
SDTI2
SDTI1
XTL1
XTL0
PDN
MASTER
DZF2
DZF1
LOUT4LOUT4+
ROUT4ROUT4+
LOUT3LOUT3+
INT1
BOUT
TVDD
DVDD
DVSS
XTO
XT I
TEST3
MCKO2
MCKO1
COUT
UOUT
VOUT
SDTO2
BICK2
LRCK2
SDTO1
BICK1
LRCK1
CDTO
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
80
79
INT0
TX1
TX0
MCLK
VIN
DAUX2
I2C
RX7
CAD1
RX6
CAD0
RX5
TEST2
RX4
PVDD
R
PVSS
RX3
NC
RX2
AK4589VQ
AKD4589
[AK4589]
MS0339-J-00
2004/09
-4-
ASAHI KASEI
[AK4589]
AK4588
Functions
DAC
DAC S/(N+D)
DAC S/N
DAC Output voltage
DAC AOUT
Load Resistance
Frequency Response 80kHz
(
)AK4589
)
ADC/DAC
AK4588
AK4589
90dB
106dB
Typ 3.0Vpp
AOUT=0.6xVREFH
5k ohm
±1.0
#35, #37, #39,#41,#43,#45,#47,#49
Min=4.5V, Max=5.5V
94dB
114dB
Typ ±2.7Vpp
AOUT=0.54xVREFH
2k ohm
+0/-0.6
#35 - #50
Min=4.75V, Max=5.25V
(AK4588
MS0339-J-00
)
DIR/DIT
(AK4588
2004/09
-5-
ASAHI KASEI
No.
1
Pin Name
INT1
[AK4589]
I/O
O
2
3
4
5
6
7
BOUT
O
TVDD
DVDD
DVSS
XTO
XTI
O
I
8
TEST3
I
9
10
11
12
13
14
15
16
17
18
19
20
MCKO2
MCKO1
COUT
UOUT
VOUT
SDTO2
BICK2
LRCK2
SDTO1
BICK1
LRCK1
CDTO
CCLK
SCL
CDTI
SDA
O
O
O
O
O
O
I/O
I/O
O
I/O
I/O
O
I
I
I
I/O
I
I
I
I
I
I
I
I
I
21
22
23
CSN
24
25
26
27
28
29
30
DAUX1
SDTI4
SDTI3
SDTI2
SDTI1
XTL1
XTL0
Function
Interrupt 1 Pin
Block-Start Output Pin for Receiver Input
“H” during first 40 flames.
Output Buffer Power Supply Pin, 2.7V∼5.25V
Digital Power Supply Pin, 4.75V∼5.25V
Digital Ground Pin
X'tal Output Pin
X'tal Input Pin
Test 3 Pin
This pin should be connected to DVSS.
Master Clock Output 2 Pin
Master Clock Output 1 Pin
C-bit Output Pin for Receiver Input
U-bit Output Pin for Receiver Input
V-bit Output Pin for Receiver Input
Audio Serial Data Output Pin (DIR/DIT part)
Audio Serial Data Clock Pin (DIR/DIT part)
Channel Clock Pin (DIR/DIT part)
Audio Serial Data Output Pin (ADC/DAC part)
Audio Serial Data Clock Pin (ADC/DAC part)
Input Channel Clock Pin
Control Data Output Pin in Serial Mode, I2C= “L”.
Control Data Clock Pin in Serial Mode, I2C= “L”
Control Data Clock Pin in Serial Mode, I2C= “H”
Control Data Input Pin in Serial Mode, I2C= “L”.
Control Data Pin in Serial Mode, I2C= “H”.
Chip Select Pin in Serial Mode, I2C= “L”.
This pin should be connected to DVSS, I2C= “H”.
AUX Audio Serial Data Input Pin (ADC/DAC part)
DAC4 Audio Serial Data Input Pin
DAC3 Audio Serial Data Input Pin
DAC2 Audio Serial Data Input Pin
DAC1 Audio Serial Data Input Pin
X’tal Frequency Select 0 Pin
X’tal Frequency Select 1 Pin
MS0339-J-00
2004/09
-6-
ASAHI KASEI
[AK4589]
No.
Pin Name
I/O
31
PDN
I
32
MASTER
I
DZF2
O
OVF
O
34
DZF1
O
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
LOUT4LOUT4+
ROUT4ROUT4+
LOUT3LOUT3+
ROUT3ROUT3+
LOUT2LOUT2+
ROUT2ROUT2+
LOUT1LOUT1+
ROUT1ROUT1+
LIN
RIN
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
53
VCOM
-
54
VREFH
-
33
Function
Power-Down Mode Pin
When “L”, the AK4589 is powered-down, all digital output pins go “L”, all registers
are reset. When CAD1/0 pins are changed, the AK4589 should be reset by PDN pin.
Master Mode Select Pin
“H”: Master mode, “L”: Slave mode
Zero Input Detect 2 Pin
(Table 13)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input
data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN bit is “0”, this pin
goes to “H”. It always is in “L” when P/S pin is “H”.
Analog Input Overflow Detect Pin
This pin goes to “H” if the analog input of Lch or Rch overflows.
Zero Input Detect 1 Pin
(Table 13)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input
data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN bit is “0”, this pin
goes to “H”. Output is selected by setting DZFE pin when P/S pin is “H”.
470pF capacitor should be connected
DAC4 Lch Negative Analog Output Pin
between LOUT4- and LOUT4+.
DAC4 Lch Positive Analog Output Pin
470pF capacitor should be connected
DAC4 Rch Negative Analog Output Pin
between ROUT4- and ROUT4+.
DAC4 Rch Positive Analog Output Pin
470pF capacitor should be connected
DAC3 Lch Negative Analog Output Pin
between LOUT3- and LOUT3+.
DAC3 Lch Positive Analog Output Pin
470pF capacitor should be connected
DAC3 Rch Negative Analog Output Pin
between ROUT3- and ROUT3+.
DAC3 Rch Positive Analog Output Pin
470pF capacitor should be connected
DAC2 Lch Negative Analog Output Pin
between LOUT2- and LOUT2+.
DAC2 Lch Positive Analog Output Pin
470pF capacitor should be connected
DAC2 Rch Negative Analog Output Pin
between ROUT2- and ROUT2+.
DAC2 Rch Positive Analog Output Pin
470pF capacitor should be connected
DAC1 Lch Negative Analog Output Pin
between LOUT1- and LOUT1+.
DAC1 Lch Positive Analog Output Pin
470pF capacitor should be connected
DAC1 Rch Negative Analog Output Pin
between ROUT1- and ROUT1+.
DAC1 Rch Positive Analog Output Pin
Lch Analog Input Pin
Rch Analog Input Pin
Common Voltage Output Pin
2.2µF capacitor should be connected to AVSS externally.
Positive Voltage Reference Input Pin, AVDD
MS0339-J-00
2004/09
-7-
ASAHI KASEI
[AK4589]
No.
55
56
57
Pin Name
AVDD
AVSS
RX0
58
NC
-
59
RX1
I
60
TEST1
I
61
RX2
I
62
NC
-
63
64
RX3
PVSS
I
-
65
R
-
66
67
PVDD
RX4
I
68
TEST2
I
69
70
71
72
73
RX5
CAD0
RX6
CAD1
RX7
I
I
I
I
I
74
I2C
I
75
76
77
78
DAUX2
VIN
MCLK
TX0
I
I
I
O
79
TX1
O
INT0
O
80
Notes:
I/O
I
Function
Analog Power Supply Pin, 4.75V∼5.25V
Analog Ground Pin, 0V
Receiver Channel 0 Pin (Internal biased pin. Internally biased at PVDD/2)
No Connect pin
No internal bonding. This pin should be connected to PVSS.
Receiver Channel 1 Pin (Internal biased pin. Internally biased at PVDD/2)
Test 1 Pin
This pin should be connected to PVSS.
Receiver Channel 2 Pin (Internal biased pin. Internally biased at PVDD/2)
No Connect pin
No internal bonding. This pin should be connected to PVSS.
Receiver Channel 3 Pin (Internal biased pin. Internally biased at PVDD/2)
PLL Ground pin
External Resistor Pin
12kΩ +/-1% resistor should be connected to PVSS externally.
PLL Power supply Pin, 4.75V∼5.25V
Receiver Channel 4 Pin (Internal biased pin. Internally biased at PVDD/2)
Test 2 Pin
This pin should be connected to PVSS.
Receiver Channel 5 Pin (Internal biased pin. Internally biased at PVDD/2)
Chip Address 0 Pin (ADC/DAC part)
Receiver Channel 6 Pin (Internal biased pin. Internally biased at PVDD/2)
Chip Address 1 Pin (ADC/DAC part)
Receiver Channel 7 Pin (Internal biased pin. Internally biased at PVDD/2)
Control Mode Select Pin.
“L”: 4-wire Serial, “H”: I2C Bus
Auxiliary Audio Data Input Pin (DIR/DIT part)
V-bit Input Pin for Transmitter Output
Master Clock Input Pin
Transmit Channel (Through Data) Output 0 Pin
Transmit Channel Output1 pin
When DIT bit = “0”, Through Data.
When DIT bit = “1”, DAUX2 Data.
Interrupt 0 Pin
(RX0-7, LIN, RIN)
PVDD
RX pin
20k(typ)
20k(typ)
PVSS
VCOM
Internal biased pin Circuit
MS0339-J-00
2004/09
-8-
ASAHI KASEI
Classification
Analog
Digital
[AK4589]
Pin Name
RX0-7, LOUT1-4, ROUT1-4, LIN, RIN
INT0-1, BOUT, XTO, MCKO1-2, COUT, UOUT,
VOUT, SDTO1-2, CDTO, DZF1-2, TX1-0
CSN, DAUX1-2, SDTI1-4, XTL0-1
TEST1-3
MS0339-J-00
Setting
These pins should be open.
These pins should be open.
These pins should be connected to DVSS.
These pins should be connected to PVSS.
2004/09
-9-
ASAHI KASEI
(AVSS, DVSS, PVSS=0V; Note 1)
Parameter
Power Supplies
Analog
Digital
PLL
Output buffer
|AVSS-DVSS|
(Note 2)
|AVSS-PVSS|
(Note 2)
Input Current (any pins except for supplies)
Analog Input Voltage
(LIN, RIN pins)
Digital Input Voltage
Except LRCK1-2, BICK1-2, RX0-7, CAD0-1,
TEST1-2 pins
LRCK1-2, BICK1-2 pins
RX0-7, CAD0-1, TEST1-2 pins
Ambient Temperature (power applied)
Storage Temperature
[AK4589]
Symbol
AVDD
DVDD
PVDD
TVDD
∆GND1
∆GND2
IIN
min
-0.3
-0.3
-0.3
-0.3
-
max
6.0
6.0
6.0
6.0
0.3
0.3
±10
Units
V
V
V
V
V
V
mA
VINA
-0.3
AVDD+0.3
V
VIND1
-0.3
DVDD+0.3
V
VIND2
VIND3
Ta
Tstg
-0.3
-0.3
-10
-65
TVDD+0.3
PVDD+0.3
70
150
V
V
°C
°C
Notes:
1.
2. AVSS, DVSS, PVSS
:
(AVSS, DVSS, PVSS=0V; Note 3)
Parameter
Power Supplies
Analog
(Note 4)
Digital
PLL
Output buffer
Symbol
AVDD
DVDD
PVDD
TVDD
Notes:
3.
4. AVDD, DVDD, PVDD, TVDD
0.5V
min
4.75
4.75
4.75
2.7
typ
5.0
5.0
5.0
5.0
max
5.25
AVDD
AVDD
DVDD
Units
V
V
V
V
AVDD, DVDD, PVDD
:
MS0339-J-00
2004/09
- 10 -
ASAHI KASEI
[AK4589]
(Ta=25°C; AVDD, DVDD, PVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz;
20Hz~40kHz at fs=192kHz, unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics
Resolution
24
Bits
dB
S/(N+D)
(-0.5dBFS) fs=48kHz
84
92
dB
fs=96kHz
86
DR
(-60dBFS) fs=48kHz, A-weighted
dB
94
102
fs=96kHz
dB
88
96
fs=96kHz, A-weighted
dB
93
102
S/N
(Note 5)
fs=48kHz, A-weighted
dB
93
102
fs=96kHz
dB
88
96
fs=96kHz, A-weighted
dB
93
102
Interchannel Isolation
90
110
dB
DC Accuracy
Interchannel Gain Mismatch
0.2
0.3
dB
Gain Drift
20
ppm/°C
AIN=0.62xVREFH
2.90
3.10
3.30
Vpp
Input Voltage
Input Resistance
fs=48kHz
15
25
kΩ
fs=96kHz
9
16
kΩ
Power Supply Rejection
(Note 7)
50
dB
DAC Analog Output Characteristics
Resolution
24
Bits
S/(N+D)
fs=48kHz
86
94
dB
84
92
fs=96kHz
dB
92
fs=192kHz
dB
DR
(-60dBFS)
fs=48kHz, A-weighted
104
114
dB
98
108
fs=96kHz
dB
104
114
fs=96kHz, A-weighted
dB
108
fs=192kHz
dB
114
fs=192kHz, A-weighted
dB
S/N
(Note 8)
fs=48kHz, A-weighted
104
114
dB
98
108
fs=96kHz
dB
104
114
fs=96kHz, A-weighted
dB
108
fs=192kHz
dB
114
fs=192kHz, A-weighted
dB
Interchannel Isolation
90
100
dB
DC Accuracy
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
20
ppm/°C
Output Voltage
AOUT=0.54xVREFH
Vpp
±2.5
±2.7
±2.9
Load Resistance
(AC Load)
(Note 6)
2
kΩ
Power Supply Rejection
(Note 7)
50
dB
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
(Note 9)
70
98
AVDD
fs=48kHz,fs=96kHz
mA
57
80
fs=192kHz
mA
12
17
PVDD
mA
44
62
DVDD+TVDD
fs=48kHz
(Note 10)
mA
57
80
fs=96kHz
mA
68
95
fs=192kHz
mA
0.1
1
Power-down mode (PDN pin = “L”)
(Note 11)
mA
MS0339-J-00
2004/09
- 11 -
ASAHI KASEI
[AK4589]
Notes:
5. CCIR-ARM
96dB(@fs=48kHz)
4kΩ
6. DC
7. VREFH +5.0V
AVDD, DVDD, PVDD, TVDD 1kHz, 50mVpp
8. CCIR-ARM
102dB (typ. @fs=48kHz)
9. CL=20pF, X'tal=24.576MHz, CM1-0=“10”, CM1-0=“10”, OCKS1-0=“10”@48kHz,“00”@96kHz, “11”@192kHz.
10. TVDD=13mA(typ).
11.
RX
DVSS
TEST3= “L”
TEST3= “H”
(Ta=25°C; AVDD, DVDD, PVDD=4.75∼5.25V; TVDD=2.7∼5.25V; fs=48kHz)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
Passband
(Note 12)
PB
0
±0.1dB
-0.2dB
-3.0dB
Stopband
SB
28.0
Passband Ripple
PR
Stopband Attenuation
SA
68
Group Delay
(Note 13)
GD
Group Delay Distortion
∆GD
ADC Digital Filter (HPF):
Frequency Response (Note 12)
-3dB
FR
-0.1dB
DAC Digital Filter:
Passband
(Note 12)
-0.1dB
PB
0
-6.0dB
Stopband
SB
26.2
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay
(Note 13)
GD
DAC Digital Filter + Analog Filter:
FR
Frequency Response:
0 ∼ 20.0kHz
FR
40.0kHz
(Note 14)
FR
80.0kHz
(Note 14)
Notes:
12.
typ
max
Units
20.0
23.0
18.9
-
16
0
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
1.0
6.5
Hz
Hz
±0.04
19.2
kHz
kHz
kHz
dB
dB
1/fs
±0.2
±0.3
+0/-0.6
dB
dB
dB
24.0
21.8
±0.02
fs
-0.1dB
21.8kHz
0.454 x fs(DAC)
13.
24
ADC
DAC
20/24
DAC
14. 40.0kHz@fs=96kHz , 80.0kHz@fs=192kHz.
MS0339-J-00
2004/09
- 12 -
ASAHI KASEI
[AK4589]
DC
(Ta=25°C; AVDD, DVDD, PVDD=4.75∼5.25V; TVDD=2.7∼5.25V)
Parameter
Symbol
VIH
High-Level Input Voltage
(Except XTI pin)
VIH
(XTI pin)
VIL
Low-Level Input Voltage
(Except XTI pin)
VIL
(XTI pin)
Input Voltage at AC Coupling (XTI pin) (Note15)
VAC
High-Level Output Voltage
VOH
(Except TX0-1, DZF pins: Iout=-400µA)
VOH
(TX0-1 pin: Iout=-400µA)
VOH
(DZF pin: Iout=-400µA)
VOL
Low-Level Output Voltage
(Iout=400µA)
Iin
Input Leakage Current
Note:
15. XTI pin
(0.1µF)
min
2.2
70%DVDD
-
typ
-
max
0.8
30%DVDD
Units
V
V
V
V
40%DVDD
-
-
Vpp
TVDD-0.4
DVDD-0.4
AVDD-0.4
-
-
0.4
±10
V
V
V
V
µA
typ
10
max
Units
kΩ
mVpp
mV
kHz
S/PDIF
(Ta=25°C; AVDD, DVDD, PVDD=4.75~5.25V;TVDD=2.7~5.25V)
Parameter
Symbol
min
Input Resistance
Zin
Input Voltage (Internally biased at PVDD/2)
VTH
200
Input Hysteresis
VHY
Input Sample Frequency
fs
32
50
-
192
PVDD
RX pin
20k(typ)
20k(typ)
PVSS
VCOM
Internal biased pin Circuit
MS0339-J-00
2004/09
- 13 -
ASAHI KASEI
[AK4589]
ADC/DAC
(Ta=25°C; AVDD, DVDD, PVDD=4.75∼5.25V; TVDD=2.7∼5.25V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Master Clock
256fsn, 128fsd:
fCLK
8.192
Pulse Width Low
tCLKL
27
Pulse Width High
tCLKH
27
384fsn, 192fsd:
fCLK
12.288
Pulse Width Low
tCLKL
20
Pulse Width High
tCLKH
20
512fsn, 256fsd, 128fsq:
fCLK
16.384
Pulse Width Low
tCLKL
15
Pulse Width High
tCLKH
15
LRCK1 Timing (Slave Mode)
Normal mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
TDM 256 mode
LRCK1 frequency
“H” time
“L” time
TDM 128 mode
LRCK1 frequency
“H” time
“L” time
LRCK1 Timing (Master Mode)
Normal mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
TDM 256 mode
LRCK1 frequency
“H” time
TDM 128 mode
LRCK1 frequency
“H” time
Power-down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO1 valid
Notes:
16. I2S
17.
18. PDN pin
typ
max
Units
12.288
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
18.432
24.576
fsn
fsd
fsq
Duty
32
64
120
45
48
96
192
55
kHz
kHz
kHz
%
fsd
tLRH
tLRL
32
1/256fs
1/256fs
48
kHz
ns
ns
fsd
tLRH
tLRL
64
1/128fs
1/128fs
96
kHz
ns
ns
fsn
fsd
fsq
Duty
32
64
120
48
96
192
kHz
kHz
kHz
%
fsn
tLRH
32
48
(Note 16)
kHz
ns
fsd
tLRH
64
96
(Note 16)
1/4fs
kHz
ns
(Note 17)
(Note 18)
tPD
tPDV
150
522
ns
1/fs
50
1/8fs
“L” time
PDN pin
“L”
“H”
LRCK1
MS0339-J-00
2004/09
- 14 -
ASAHI KASEI
[AK4589]
Parameter
Audio Interface Timing (Slave Mode)
Normal mode
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑”
(Note 19)
BICK1 “↑” to LRCK1 Edge
(Note 19)
LRCK1 to SDTO1(MSB)
BICK1 “↓” to SDTO1
SDTI1-4,DAUX1 Hold Time
SDTI1-4,DAUX1 Setup Time
TDM 256 mode
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑”
(Note 19)
BICK1 “↑” to LRCK1 Edge
(Note 19)
BICK1 “↓” to SDTO1
SDTI1 Hold Time
SDTI1 Setup Time
TDM 128 mode
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑”
(Note 19)
BICK1 “↑” to LRCK1 Edge
(Note 19)
BICK1 “↓” to SDTO1
SDTI1-2 Hold Time
SDTI1-2 Setup Time
Audio Interface Timing (Master Mode)
Normal mode
BICK1 Frequency
BICK1 Duty
BICK1 “↓” to LRCK1 Edge
BICK1“↓” to SDTO1
SDTI1-4,DAUX1 Hold Time
SDTI1-4,DAUX1 Setup Time
TDM 256 mode
BICK1 Frequency
BICK1 Duty
(Note 20)
BICK1 “↓” to LRCK1 Edge
BICK1 “↓” to SDTO1
SDTI1 Hold Time
SDTI1 Setup Time
TDM 128 mode
BICK1 Frequency
BICK1 Duty
(Note 21)
BICK1 “↓” to LRCK1 Edge
BICK1 “↓” to SDTO1
SDTI1-2 Hold Time
SDTI1-2 Setup Time
Notes:
19.
LRCK1
20. MCLK 512fs
21. MCLK 256fs
Symbol
min
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
32
32
20
20
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
typ
max
40
40
20
20
20
10
10
20
10
10
64fs
50
-20
ns
ns
ns
ns
ns
ns
ns
ns
12
20
Hz
%
ns
ns
ns
ns
12
20
Hz
%
ns
ns
ns
ns
10
10
128fs
50
10
10
ns
ns
ns
ns
ns
ns
ns
ns
20
40
256fs
50
-12
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
20
20
-12
Units
BICK1
(384fs,256fs
(128fs
MS0339-J-00
Duty
Duty
)
)
2004/09
- 15 -
ASAHI KASEI
[AK4589]
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fsn, 1/fsd, 1/fsq
VIH
LRCK1
VIL
tBCK
VIH
BICK1
VIL
tBCKH
tBCKL
(Normal mode)
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK1
VIL
tLRH
tLRL
tBCK
VIH
BICK1
VIL
tBCKH
tBCKL
(TDM 256 mode, TDM 128 mode)
MS0339-J-00
2004/09
- 16 -
ASAHI KASEI
[AK4589]
VIH
LRCK1
VIL
tBLR
tLRB
VIH
BICK1
VIL
tLRS
tBSD
50%TVDD
SDTO1
tSDS
tSDH
VIH
SDTI
VIL
(Normal mode)
VIH
LRCK1
VIL
tBLR
tLRB
VIH
BICK1
VIL
tBSD
SDTO1
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
(TDM 256 mode, TDM 128 mode)
MS0339-J-00
2004/09
- 17 -
ASAHI KASEI
[AK4589]
LRCK1
50%TVDD
tMBLR
50%TVDD
BICK1
tBSD
50%TVDD
SDTO1
tDXS
tDXH
VIH
DAUX1
VIL
(Master Mode)
MS0339-J-00
2004/09
- 18 -
ASAHI KASEI
[AK4589]
(DIR/DIT )
(Ta=25°C; DVDD, AVDD, PVDD=4.75~5.25V, TVDD=2.7~5.25V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Crystal Resonator Frequency
fXTAL
11.2896
External Clock
Frequency
fECLK
11.2896
Duty
dECLK
40
MCKO1 Output
Frequency
fMCK1
4.096
Duty
dMCK1
40
MCKO2 Output
Frequency
fMCK2
2.048
Duty
dMCK2
40
PLL Clock Recover Frequency (RX0-7)
fpll
32
LRCK2 Frequency
fs
32
Duty Cycle
dLCK
45
Audio Interface Timing
Slave Mode
tBCK
BICK2 Period
80
tBCKL
BICK2 Pulse Width Low
30
tBCKH
Pulse Width High
30
tLRB
20
LRCK2 Edge to BICK2 “↑”
(Note 22)
tBLR
20
BICK2 “↑” to LRCK2 Edge
(Note 22)
tLRM
LRCK2 to SDTO2 (MSB)
tBSD
BICK2 “↓” to SDTO2
tDXH
20
DAUX2 Hold Time
tDXS
20
DAUX2 Setup Time
Master Mode
BICK2 Frequency
fBCK
BICK2 Duty
dBCK
tMBLR
-20
BICK2 “↓” to LRCK2
tBSD
BICK2 “↓” to SDTO2
tDXH
20
DAUX2 Hold Time
tDXS
20
DAUX2 Setup Time
Notes:
22.
LRCK2
BICK2
MS0339-J-00
typ
50
50
50
-
max
Units
24.576
24.576
60
24.576
60
24.576
60
192
192
55
MHz
MHz
%
MHz
%
MHz
%
kHz
kHz
%
30
30
64fs
50
20
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
2004/09
- 19 -
ASAHI KASEI
[AK4589]
1/fECLK
VIH
XTI
VIL
tECLKH
tECLKL
dECLK = tECLKH x fECLK x 100
= tECLKL x fECLK x 100
1/fMCK1
MCKO1
50%TVDD
tMCKH1
tMCKL1
dMCK1 = tMCKH1 x fMCK1 x 100
= tMCKL1 x fMCK1 x 100
1/fMCK2
MCKO2
50%TVDD
tMCKH2
tMCKL2
dMCK2 = tMCKH2 x fMCK2 x 100
= tMCKL2 x fMCK2 x 100
1/fs
VIH
LRCK2
VIL
tLRH
tLRL
dLCK = tLRH x fs x 100
= tLRL x fs x 100
VIH
LRCK2
VIL
tBCK
tBLR
tLRB
tBCKL
tBCKH
VIH
BICK2
VIL
tBSD
tLRM
50%TVDD
SDTO2
tDXS
tDXH
VIH
DAUX2
VIL
(Slave Mode)
MS0339-J-00
2004/09
- 20 -
ASAHI KASEI
[AK4589]
LRCK2
50%TVDD
tMBLR
50%TVDD
BICK2
tBSD
50%TVDD
SDTO2
tDXS
tDXH
VIH
DAUX2
VIL
(Master Mode)
tPW
PDN
VIL
MS0339-J-00
2004/09
- 21 -
ASAHI KASEI
[AK4589]
ADC/DAC , DIR/DIT
(Ta=25°C; AVDD, DVDD, PVDD=4.75∼5.25V; TVDD=2.7∼5.25V; CL=20pF)
Parameter
Symbol
Control Interface Timing (4-wire serial mode)
CCLK Period
tCCK
CCLK Pulse Width Low
tCCKL
Pulse Width High
tCCKH
CDTI Setup Time
tCDS
CDTI Hold Time
tCDH
CSN “H” Time
tCSW
tCSS
CSN “↓” to CCLK “↑”
tCSH
CCLK “↑” to CSN “↑”
tDCD
CDTO Delay
tCCZ
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I2C Bus mode)
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
Clock Low Time
tLOW
Clock High Time
tHIGH
Setup Time for Repeated Start Condition
tSU:STA
SDA Hold Time from SCL Falling
(Note 23)
tHD:DAT
SDA Setup Time from SCL Rising
tSU:DAT
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
Capacitive load on bus
Cb
Notes:
23.
300ns (SCL
24. I2C Philips Semiconductors
min
typ
max
Units
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
1.0
0.3
50
400
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
pF
200
80
80
50
50
150
50
50
4.7
4.0
4.7
4.0
4.7
0
0.25
4.0
0
-
)
I2C
Philips
I2C
2
IC
Philips
I2C
MS0339-J-00
2004/09
- 22 -
ASAHI KASEI
[AK4589]
(ADC/DAC
DIR/DIT )
VIH
CSN
VIL
tCSS
tCCK
tCCKL tCCKH
VIH
CCLK
VIL
tCDH
tCDS
C1
CDTI
C0
A4
R/W
VIH
VIL
Hi-Z
CDTO
WRITE/READ
ADC/DAC
(4-wire serial mode)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
VIH
D0
VIL
Hi-Z
CDTO
WRITE
(4-wire serial mode)
VIH
CSN
VIL
VIH
CCLK
VIL
CDTI
A1
VIH
A0
VIL
tDCD
CDTO
Hi-Z
D7
READ
ADC/DAC
D6
D5
50%TVDD
1 (4-wire serial mode)
MS0339-J-00
2004/09
- 23 -
ASAHI KASEI
[AK4589]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D3
D2
D1
READ
ADC/DAC
50%TVDD
D0
2 (4-wire serial mode)
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
I2 C
ADC/DAC
tPD
VIH
PDN
VIL
tPDV
SDTO
50%TVDD
MS0339-J-00
2004/09
- 24 -
ASAHI KASEI
[AK4589]
(ADC/DAC )
MCLK, LRCK1, BICK1
MCLK LRCK1
MCLK
DFS0, DFS1 bit
(Manual Setting Mode)
(Auto Setting Mode) 2
Manual
Setting Mode (ACKS bit = “0”: Default)
DFS1-0 bit
(Table 1)
MCLK
(Table 3,4,5) Auto
Setting Mode (ACKS bit = “1”)
MCLK
(Table 6)
(Table 7)
DFS bit
MCLK
DFS1-0 bit(Table 1)
BICK1
CKS1-0 bit(Table 2)
CKS1-0 bit DFS1-0 bit
LRCK1
(PDN pin = “H”)
(RSTN1 bit = “0”)
(MCLK,BICK1,LRCK1)
(PDN pin = “L”)
(PDN pin = “↑”) MCLK, LRCK1
ON
(MCLK)
(PDN pin = “ ”)
ON
MCLK
DFS1
0
0
1
DFS0
0
1
0
Sampling Speed (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
120kHz~192kHz
Table 1.
CKS1
0
0
1
1
Table 2.
LRCK1
fs
32.0kHz
44.1kHz
48.0kHz
Table 3.
Default
(Manual Setting Mode)
CKS0
0
1
0
1
256fs
8.1920
11.2896
12.2880
Normal
256fs
384fs
512fs
256fs
Double
128fs
192fs
256fs
256fs
(Master Mode)
Quad
128fs
128fs
128fs
128fs
Default
MCLK (MHz)
BICK1 (MHz)
384fs
512fs
64fs
12.2880
16.3840
2.0480
16.9344
22.5792
2.8224
18.4320
24.5760
3.0720
(Normal Speed Mode @Manual Setting Mode)
LRCK1
MCLK (MHz)
BICK1 (MHz)
fs
128fs
192fs
256fs
64fs
88.2kHz
11.2896
16.9344
22.5792
5.6448
96.0kHz
12.2880
18.4320
24.5760
6.1440
Table 4.
(Double Speed Mode @Manual Setting Mode)
( :Double Speed Mode (DFS1=“0”, DFS0=“1”) 128fs 192fs
,
ADC
)
MS0339-J-00
2004/09
- 25 -
ASAHI KASEI
[AK4589]
LRCK1
MCLK (MHz)
BICK1 (MHz)
fs
128fs
192fs
256fs
64fs
176.4kHz
22.5792
11.2896
192.0kHz
24.5760
12.2880
Table 5.
(Quad Speed Mode @Manual Setting Mode)
( :Quad Speed Mode (DFS1=“1”, DFS1=“0”)
ADC
MCLK
512fs
256fs
128fs
Table 6.
LRCK1
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
Table 7.
128fs
22.5792
24.5760
Sampling Speed
Normal
Double
Quad
(Auto Setting Mode)
MCLK (MHz)
256fs
512fs
16.3840
22.5792
24.5760
22.5792
24.5760
(Auto Setting Mode)
IIR
3
(32kHz, 44.1kHz, 48kHz)
Double Speed Mode Quad Speed Mode
DAC1(SDTI1), DAC2(SDTI2), DAC3(SDTI3), DAC4(SDTI4)
Mode
0
1
2
3
Sampling Speed
Normal Speed
Normal Speed
Normal Speed
Normal Speed
Table 8.
)
DEM1
0
0
1
1
Sampling
Speed
Normal
Double
Quad
(50/15µs
)
OFF
DEM0
0
1
0
1
DEM
44.1kHz
OFF
48kHz
32kHz
Default
HPF
ADC
DC
HPF
HPF fc
fs=48kHz
1.0Hz
fs
MS0339-J-00
2004/09
- 26 -
ASAHI KASEI
[AK4589]
MASTER pin
(MASTER pin = “H” )
(MASTER pin = “L” )
LRCK1 pin, BICK1 pin
Table 9
PDN pin
MASTER pin
L
H
L
“00”
H
L
“00”
H
Table 9. LRCK1 pin, BICK1 pin
H
H
LRCK1pin
Input
“L”
Input
“L”
Input
Output
TDM1-0 bit = “00”
8
(Table 10) DIF1-0 bit
MSB
2’s compliment
SDTO1 BICK1
SDTI/DAUX1 BICK1
Figure 1∼4 SDOS bit = “0”
SDTO1
ADC
SDOS bit = “1”
DAUX1
SDTO
mode2, 3, 6, 7,10,11,14,15,18,19,22,23 16 ∼ 20bit
Table 10 Default Mode 2
Mode
MASTER
0
1
2
3
4
5
6
7
Table 10
TDM1-0 bit
SDTI2-4
0
0
0
0
1
1
1
1
TDM1
TDM0
DIF1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
“01”
compliment
TDM
(96kHz)
TDM1-0 bit
DAC(4ch;L3,R3,L4,R4)
“L”
LRCK1 pin, BICK1 pin
LRCK1 pin, BICK1 pin
PWADN bit, PWDAN bit
L
“H”
DIF0
SDTO1
BICK1 pin
Input
L”
Input
L”
Input
Output
SDTI
LSB
“0”
SDTI1-4,
DAUX1
LRCK1
BICK1
I/O
I/O
0
24bit, M J
20bit, L J
H/L
I
I
≥ 48fs
1
24bit, M J
24bit, L J
H/L
I
I
≥ 48fs
0
24bit, M J
24bit, M J
H/L
I
I
≥ 48fs
2
2
1
24bit, I S
24bit, I S
L/H
I
I
≥ 48fs
0
24bit, M J
20bit, L J
H/L
O
64fs
O
1
24bit, M J
24bit, L J
H/L
O
64fs
O
0
24bit, M J
24bit, M J
H/L
O
64fs
O
1
24bit, I2S
24bit, I2S
L/H
O
64fs
O
(Normal mode, M J shows MSB justified, L J means LSB justified.)
TDM 256 mode
SDTI1 pin
DAC(8ch)
BICK1 256fs
LRCK1
“H”
“L”
1/256fs(min)
8
(Table 11) DIF1-0 bit
MSB
2’s
SDTO1 BICK1
SDTI1 BICK1
SDOS bit, LOOP1-0 bit
“0”
TDM 128 mode
“10”
SDTI1 pin DAC(4ch; L1,R1,L2,R2) SDTI2 pin
MS0339-J-00
2004/09
- 27 -
ASAHI KASEI
Mode
MASTER
TDM 1
TDM0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MASTER
TDM 1
TDM0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
9
10
11
12
13
14
15
Table 11.
Mode
[AK4589]
16
17
18
19
20
21
22
23
Table 12.
0
0
0
0
1
1
1
1
DIF1
DIF0
SDTO1
DIF1
DIF0
SDTO1
SDTI1
LRCK1
BICK1
I/O
I/O
0
0
24bit, M J
20bit, L J
I
256fs
I
↑
0
1
24bit, M J
24bit, L J
I
256fs
I
↑
1
0
24bit, M J
24bit, M J
I
256fs
I
↑
1
1
24bit, I2S
24bit, I2S
I
256fs
I
↓
0
0
24bit, M J
20bit, L J
O
256fs
O
↑
0
1
24bit, M J
24bit, L J
O
256fs
O
↑
1
0
24bit, M J
24bit, M J
O
256fs
O
↑
1
1
24bit, I2S
24bit, I2S
O
256fs
O
↓
TDM 256 mode, M J shows MSB justified, L J means LSB justified.
SDTI1,
LRCK1
BICK1
SDTI2
I/O
I/O
0
0
24bit, M J
20bit, L J
I
128fs
I
↑
0
1
24bit, M J
24bit, L J
I
128fs
I
↑
1
0
24bit, M J
24bit, M J
I
128fs
I
↑
1
1
24bit, I2S
24bit, I2S
I
128fs
I
↓
0
0
24bit, M J
20bit, L J
O
128fs
O
↑
0
1
24bit, M J
24bit, L J
O
128fs
O
↑
1
0
24bit, M J
24bit, M J
O
128fs
O
↑
1
1
24bit, I2S
24bit, I2S
O
128fs
O
↓
TDM 128 mode, M J shows MSB justified, L J means LSB justified.
MS0339-J-00
2004/09
- 28 -
ASAHI KASEI
[AK4589]
LRCK1
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK1(64fs)
SDTO1(o)
23 22
SDTI(i)
12 11 10
0
19 18
Don’t Care
23 22
8
7
1
0
12
11 10
0
19 18
Don’t Care
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 1. Mode 0,4
LRCK1
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
24
25
31
0
1
BICK1(64fs)
SDTO1(o)
23 22
SDTI(i)
16 15 14
0
23 22
8
Don’t Care
23:MSB, 0:LSB
23 22
7
1
0
16 15 14
0
23 22
Don’t Care
Lch Data
23
8
7
1
0
Rch Data
Figure 2. Mode 1 ,5
LRCK1
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
28
29
30
31
0
1
BICK1(64fs)
SDTO1(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
23
23
Don’t Care
Rch Data
Figure 3.Mode 2,6
LRCK1
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK1(64fs)
SDTO1(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
Don’t Care
23 22
2
1
0
23 22
2
1
0
Don’t Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 ,7
MS0339-J-00
2004/09
- 29 -
ASAHI KASEI
[AK4589]
256 B ICK
LRCK1
(m ode 8)
LRCK1
(m ode 12)
BICK1(256fs)
SDTO 1(o)
23 22
0
23 22
Lch
32 B ICK
SDTI1(i)
0
23 22
Rch
19 18
32 B ICK
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
L1
R1
L2
R2
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
19
Figure 5. Mode 8 ,12
256 B ICK
LRCK1
(m ode 9)
LRCK1
(m ode 13)
BICK1(256fs)
SDTO 1(o)
SDTI1(i)
23 22
0
23 22
0
Lch
Rch
32 B ICK
32 B ICK
23 22
0
23 22
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23
Figure 6. Mode 9 ,13
256 B ICK
LRCK1
(m ode 10)
LRCK1
(m ode 14)
BICK1(256fs)
SDTO 1(o)
SDTI1(i)
23 22
0
23 22
0
Lch
Rch
32 B ICK
32 B ICK
23 22
0
23 22
0
23 22
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
Figure 7. Mode 10 ,14
256 B ICK
LRCK1
(m ode 11)
LRCK1
(m ode 15)
BICK1(256fs)
SDTO 1(o)
23
0
Lch
SDTI1(i)
0
23
Rch
32 B ICK
23
23
0
32 B ICK
23
0
L1
R1
32 B ICK
32 B ICK
23
0
23
0
L2
R2
32 B ICK
32 B ICK
23
0
23
0
23
0
23
0
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23
Figure 8. Mode 11 ,15
MS0339-J-00
2004/09
- 30 -
ASAHI KASEI
[AK4589]
128 B ICK
LRCK1
(m ode 16)
LRCK1
(m ode 20)
BICK1(128fs)
SDTO1(o)
23 22
0
SDTI2(i)
23 22
Rch
32 B ICK
SDTI1(i)
0
23 22
Lch
32 B ICK
19 18
0
19 18
0
19 18
0
19 18
L1
R1
L2
R2
32 B ICK
32 B ICK
32 B ICK
32 B ICK
19 18
0
19 18
0
0
19 18
19 18
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
0
19
0
19
Figure 9. Mode 16 ,20
128 B ICK
LRCK1
(m ode 17)
LRCK1
(m ode 21)
BICK1(128fs)
23 22
SDTI1(i)
SDTI2(i)
0
0
23 22
Lch
Rch
32 B ICK
32 B ICK
23 22
0
23 22
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
0
23 22
0
0
23 22
23 22
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
0
19
0
19
Figure 10. Mode 17 ,21
128 B ICK
LRCK1
(m ode 18)
LRCK1
(m ode 22)
BICK1(128fs)
SDTO 1(o)
SDTI1(i)
SDTI2(i)
23 22
0
0
23 22
Lch
Rch
32 B ICK
32 B ICK
23 22
0
23 22
0
23 22
23 22
0
23 22
L1
R1
L2
R2
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
0
23 22
0
23 22
0
23 22
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
0
23 22
0
23 22
Figure 11. Mode 18 ,22
MS0339-J-00
2004/09
- 31 -
ASAHI KASEI
[AK4589]
128 B ICK
LRCK1
(m ode 19)
LRCK1
(m ode 23)
BICK1(128fs)
SDTO1(o)
23 22
0
SDTI1(i)
SDTI2(i)
23
Rch
32 B ICK
23 22
0
23 22
Lch
32 B ICK
0
23 22
0
0
23 22
23 22
L1
R1
L2
R2
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
0
23 22
0
0
23 22
23 22
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
0
23
0
23
Figure 12. Mode 19 ,23
MS0339-J-00
2004/09
- 32 -
ASAHI KASEI
[AK4589]
AK4589
Lch
OVFE bit “1”
(-0.3dBFS
) OVF pin
OVF
ADC
(GD = 16/fs = 333µs
(PDN pin = “L” → “H”) 522/fs (=11.8ms @fs=48kHz)
OVF pin
Rch
“H”
@fs=48kHz)
“L”
AK4589 2
DZF1 pin Group1
DZF2 pin OVF pin
bit DZF
Table 14
Group1(Group2)
Group1(Group2)
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DZFM
2 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Group
DZF2 pin
mode 0
Group2
DZF1 pin
8192
8ch
“0”
“0”
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
L1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
R1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF1
DZF1
DZF1
DZF1
DZFM3-0 bit
AND
(Table 13)
OVFE bit “1”
DZF2 pin
(“L”)
OVFE
DZF1(DZF2) pin
“L”
AOUT
L2
R2
L3
R3
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF1
DZF1
DZF2
DZF2
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
Disable (DZF1=DZF2 = “L”)
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
“H”
L4
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
R4
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF1
DZF2
DZF2
DZF2
Default
Disable (DZF1=DZF2 = “L”)
Table 13.
OVFE bit
0
1
DZF1 pin
Selectable (Table 13)
Selectable (Table 13)
DZF2/OVF pin
Selectable (Table 13)
OVF output
Table 14. DZF1-2 pin
MS0339-J-00
2004/09
- 33 -
ASAHI KASEI
[AK4589]
AK4589
ATT7-0 bit
(128
(Table 15)
ATT7-0
00H
01H
02H
:
7DH
7EH
7FH
FEH
FFH
, 0.5dB
Attenuation Level
0dB
-0.5dB
-1.0dB
:
-62.5dB
-63dB
MUTE (-∞)
:
MUTE (-∞)
MUTE (-∞)
)
Default
Table 15.
ATT7-0
ATS1-0 bit
Mode
0
1
2
3
ATS1
0
0
1
1
(Table 16) Mode0 Mode1
ATS0
0
1
0
1
Table 16.
Mode0
ATT
(37.3ms@fs=48kHz)
bit
“0”
00H
1792
PDN pin
“L”
RSTN1 bit
ATT speed
1792/fs
896/fs
256/fs
256/fs
Default
ATT7-0
00H(0dB)
ATT7-0 00H
7FH(MUTE)
ATT7-0
1792/fs
RSTN1
“1”
MS0339-J-00
2004/09
- 34 -
ASAHI KASEI
[AK4589]
×ATT
-∞
ATT
SMUTE bit
-∞ (“0”)
(Table 16)
×ATT
“1”
ATT
SMUTE bit
-∞
ATT
ATT
“0”
ATT
SMUTE bit
(1)
ATT Level
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
(4)
8192/fs
DZF1,2
:
(1)ATT
×ATT
(2)
(3)
(Table 16)
ATT
Mode 0
00H 7FH
(GD)
ATT
“00H”
1792/fs
-∞
ATT
(4)
8192
“0”
“0”
DZF pin
“H”
DZF pin
“L”
Figure 13.
ON
PDN pin
LRCK1
“L”
“↑”
MCLK
LRCK1
MS0339-J-00
2004/09
- 35 -
ASAHI KASEI
AK4589
ADC
[AK4589]
DAC
(PDN pin) “L”
PDN pin = “L”
SDTO1,DZF1-2 pin
VCOM
ADC
, SDTO1 522 x LRCK1
ADC
DAC
PWADN bit
“L”
DAC
VCOM
Table 14
PWDAN bit
SDTO1 pin
“L”
DZF1-2 pin
“H”
PWDAN bit = “0”
DAC1-4 PD1-4 bit
PWADN bit = “0”
VCOM
PD1-4 bit = “0”
Power
PDN pin
(1)
522/fs
ADC Internal
State
Init Cycle
516/fs
DAC Internal
State
Normal Operation
Power-down
Normal Operation
Power-down
(2)
Init Cycle
GD (3)
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data (4)
DAC In
(Digital)
“0”data
(5)
“0”data
“0”data
GD
(3)
(6)
DAC Out
(Analog)
GD
(6)
(7)
Clock In
MCLK,LRCK1,
BICK1
Don’t care
Don’t care
10∼11/fs (10)
(8)
DZF1/DZF2
External
Mute
(1) ADC
(2) DAC
(3)
(4)
(5)
(6) PDN
(7)
(8)
(9)
(6)
(10) PDN
(9)
Mute ON
Mute ON
(GD)
ADC
“0”
ADC
PDN
(PDN pin = “L”)
(PDN pin = “L”)
“↑”
10∼11/fs
DZF1-2 pin
512/fs
(MCLK, BICK1, LRCK1)
“L”
DZF pin = “L”
Figure 14.
MS0339-J-00
2004/09
- 36 -
ASAHI KASEI
[AK4589]
RSTN1 bit = “0”
VCOM
ADC DAC
DZF1-2 pin
“H”
SDTO1 pin “L”
Table 15 RSTN1 bit
RSTN1 bit
1~2/fs (9)
4~5/fs (9)
Internal
RSTN1 bit
516/fs (1)
ADC Internal
State
Normal Operation
Digital Block Power-down
DAC Internal
State
Normal Operation
Digital Block Power-down
Normal Operation
Init Cycle
Normal Operation
GD (2)
GD
ADC In
(Analog)
(3)
ADC Out
(Digital)
(4)
“0”data
DAC In
(Digital)
“0”data
(2)
GD
GD
(6)
DAC Out
(Analog)
(6)
(5)
(7)
Clock In
Don’t care
MCLK,LRCK1,
BICK1
4∼5/fs (8)
DZF1/DZF2
(1) ADC
(2)
(3)
(4)
(GD)
ADC
“0”
ADC
(5) RSTN1 bit = “0”
(6) RSTN1 bit “0”
(7)
VCOM
4∼5/fs
(RSTN1 bit = “0”)
(8) DZF1-2 pin
RSTN1 bit
(9) RSTN1 bit
“0”
RSTN1 bit
“1”
1∼2/fs
(MCLK, BICK1, LRCK1)
(MCLK, BICK1, LRCK1)
“0”
“H”
LSI
RSTN1 bit
RSTN
RSTN1 bit = “1”
“1”
6~7/fs
“L”
4~5/fs
Figure 15.
MS0339-J-00
2004/09
- 37 -
ASAHI KASEI
[AK4589]
DAC
AK4589
DAC
“1”
PD1-4 bit
DZF
PD1-4 bit
DAC
DAC
VCOM
DZF
DZF1-2 pin
PWDAN bit = “0”
PD1-4 bit
Figure 16
RSTN1 bit = “0”
PD1-4 bit
PD1-4 bit
Power Down Channel
DAC Digital
Internal State
DAC Analog
Internal State
Normal Operation
Normal Operation
DAC In
(Digital)
Normal Operation
Power-down
Normal
Operation
Normal
Operation
Power-down
“0”data
(1)
GD
GD
(3) (2)
DAC Out
(Analog)
(3)
(3)
(2)
(3)
8192/fs
DZF Detect
Internal State
(4)
(4)
Normal Operation Channel
DAC In
(Digital)
“0”data
GD
GD
DAC Out
(Analog)
8192/fs
DZF Detect
Internal State
Clock In
MCLK,LRCK1,
BICK1
(5)
(6)
DZF1/DZF2
(1)
(2) PD1-4 bit
(3) PD1-4 bit
(4)
(GD)
DAC
DAC
PD bit
DZF
(5)
(6)
VCOM
DAC
DZF1-2 pin
DAC
DAC
DZF
DZF1-2 pin
”H”
DZF1-2 pin
”H”
Figure 16. DAC
MS0339-J-00
2004/09
- 38 -
ASAHI KASEI
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
:
[AK4589]
Register Name
Control 1
Control 2
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
LOUT3 Volume Control
ROUT3 Volume Control
De-emphasis
ATT speed
& Power Down Control
Zero detect
LOUT4 Volume Control
ROUT4 Volume Control
D7
0
CKS1
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
DEMD1
D6
0
DFS1
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
DEMD0
D5
TDM1
LOOP1
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
DEMA1
D4
TDM0
LOOP0
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
DEMA0
D3
DIF1
SDOS
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
DEMB1
D2
DIF0
DFS0
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
DEMB0
D1
0
ACKS
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
DEMC1
D0
SMUTE
CKS0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
DEMC0
0
PD4
ATS1
ATS0
PD3
PD2
PD1
RSTN1
OVFE
ATT7
ATT7
DZFM3
ATT6
ATT6
DZFM2
ATT5
ATT5
DZFM1
ATT4
ATT4
DZFM0
ATT3
ATT3
PWVRN
ATT2
ATT2
PWADN
ATT1
ATT1
PWDAN
ATT0
ATT0
0DH∼1FH
PDN pin
“L”
RSTN bit
“0”
Addr
00H
DZF1-2 pin
Register Name
Control 1
Default
SMUTE:
0:
1:
D7
0
0
D6
0
0
D5
TDM1
0
D4
TDM0
0
D3
DIF1
1
“H”
D2
DIF0
0
D1
0
0
D0
SMUTE
0
DAC
DIF1-0:
(Table 10)
: “10”, mode 2
TDM1-0: TDM
Mode
0
1
2
(Table 11,12)
TDM1 TDM0
0
0
0
1
1
1
SDTI
1-4
1
1-2
Sampling Speed
Normal, Double, Quad Times Speed
Normal Speed
Normal, Double Speed
MS0339-J-00
2004/09
- 39 -
ASAHI KASEI
Addr
01H
[AK4589]
Register Name
Control 2
Default
D7
CKS1
0
D6
DFS1
0
D5
LOOP1
0
D4
LOOP0
0
D3
SDOS
0
D2
DFS0
0
D1
ACKS
0
D0
CKS0
0
ACKS:
0:
, Manual Setting Mode
1:
, Auto Setting Mode
ACKS bit = “1”
MCLK
ACKS bit = “0”
MCLK
DFS1-0:
ACKS bit = “1”
CKS0-1:
SDOS: SDTO1
0: ADC
1: DAUX1
TDM0 bit = “1”
PWADN bit =”0”
ADC
DFS
DFS0,1 bit
(Table 1)
DFS
(MASTER Mode, Table 2)
SDOS bit
“0”
PWDAN bit =”0”
PWADN bit =”0”
SDOS
SDTO1 pin
”L”
LOOP1-0:
00:
(
)
01: LIN → LOUT1, LOUT2, LOUT3, LOUT4
RIN → ROUT1, ROUT2, ROUT3, ROUT4
ADC
(SDOS bit = “1”
DAUX1
) DAC
SDTI1-4
DAC
SDTO1
mode0
mode2 mode1
mode3
10: SDTI1(L) → SDTI2(L), SDTI3(L), SDTI4(L)
SDTI1(R) → SDTI2(R), SDTI3(R), SDTI4(R)
DAC
SDTI2-4
11: N/A
TDM0 bit = “1”
LOOP1-0 bit
“00”
PWADN bit =”0”
PWDAN bit =”0”
LOOP1-0 bit
(
)
MS0339-J-00
2004/09
- 40 -
ASAHI KASEI
Addr
02H
03H
04H
05H
06H
07H
0BH
0CH
[AK4589]
Register Name
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
LOUT3 Volume Control
ROUT3 Volume Control
LOUT4 Volume Control
ROUT4 Volume Control
Default
ATT7-0:
Addr
08H
Register Name
De-emphasis
Default
D7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
0
D6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
0
D5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
0
D4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
0
D3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
0
D2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
0
D1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
0
D0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
0
(Table 15)
D7
DEMD1
0
D6
DEMD0
1
D5
DEMA1
0
D4
DEMA0
1
D3
DEMB1
0
DEMA1-0: DAC1
: “01”, OFF
(Table 8)
DEMB1-0: DAC2
: “01”, OFF
(Table 8)
DEMC1-0: DAC3
: “01”, OFF
(Table 8)
DEMD1-0: DAC4
: “01”, OFF
(Table 8)
MS0339-J-00
D2
DEMB0
1
D1
DEMC1
0
D0
DEMC0
1
2004/09
- 41 -
ASAHI KASEI
Addr
09H
[AK4589]
Register Name
ATT speed
& Power Down Control
Default
RSTN1:
0:
1:
D7
D6
D5
D4
D3
D2
D1
D0
0
PD4
ATS1
ATS0
PD3
PD2
PD1
RSTN1
0
0
0
0
0
0
0
1
DZF1-2 pin
“H”
ATS1-0:
(Table 16)
: “00”, mode 0
PD1-0: Power-down control (0: Power-up, 1: Power-down)
PD1: Power down control of DAC1
PD2: Power down control of DAC2
PD3: Power down control of DAC3
PD4: Power down control of DAC4
Addr
0AH
Register Name
Zero detect
Default
D7
OVFE
0
D6
DZFM3
0
D5
DZFM2
1
D4
DZFM1
1
D3
DZFM0
1
D2
PWVRN
1
D1
PWADN
1
D0
PWDAN
1
PWDAN: DAC1-4
0:
1:
PWADN: ADC
0:
1:
PWVRN:
0:
1:
DZFM3-0:
(Table 13)
: “0111”,
OVFE:
0:
1:
, pin#33 DZF2 pin
, pin#33 OVF pin
MS0339-J-00
2004/09
- 42 -
ASAHI KASEI
[AK4589]
(DIR/DIT
)
Non-PCM/DTS-CD
AK4589
Non-PCM
Dolby “AC-3 Data Stream in IEC60958 Interface”
32
Mode Non-PCM
AUTO bit
“1”
96
sync code 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F
4096
sync code
sync code
AUTO bit
“0”
sync code
2
(Pc, Pd)
DTS-CD
DTSCD bit “1”
4096
sync code
sync code
DTSCD bit “0”
192kHz
PLL 32kHz
192kHz
20ms
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
AK4589
2
PLL
X'tal
MCKO2)
X’tal
No.
0
1
2
3
fs
OCKS1
0
0
1
1
OCKS0
0
1
0
1
Table 17.
MCKO1
256fs
256fs
512fs
128fs
MCKO2
256fs
128fs
256fs
64fs
RX
Mode 2
X’tal
PLL
X'tal
RX
CM1
0
0
2
1
3
1
Note: X’tal
CM0
0
1
512fs 192kHz
X’tal
fs (max)
256fs
96 kHz
256fs
96 kHz
512fs
48 kHz
128fs
192 kHz
(Stereo mode )
DAUX2
Unlock
Mode
0
1
(Table 17)
96kHz
OCKS1-0 bit
(MCKO1,
256fs,512fs
Default
CM1-0 bit
Mode 3
Mode 2, 3
PLL X'tal
UNLOCK
PLL
X'tal
Clock source SDTO
ON
ON(Note)
PLL
RX
OFF
ON
X'tal
DAUX2
0
ON
ON
PLL
RX
0
1
ON
ON
X'tal
DAUX2
1
ON
ON
X'tal
DAUX2
ON:
(Power-up), OFF:
(Power-Down)
(XTL1-0 pin = “H,H”) OFF
Default
Table 18.
MS0339-J-00
2004/09
- 43 -
ASAHI KASEI
AK4589
[AK4589]
XTI pin
1) X’tal
XTI
C
25kΩ(typ)
C
XTO
AK4589
Figure 17. X’tal
Note:
(Typ.10-40pF)
2)
- Note: DVDD
C
XTI
External
Clock
XTI
External
Clock
25kΩ(typ)
25kΩ(typ)
XTO
XTO
AK4589
AK4589
Figure 18
(Input :CMOS Level)
Figure 19 AC
(Input : 40%DVDD, C=0.1µF)
3) XTI/XTO
XTI
25kΩ(typ)
XTO
AK4589
Figure 20. OFF
MS0339-J-00
2004/09
- 44 -
ASAHI KASEI
[AK4589]
AK4589
2
XTL1-0 pin
X’tal
X’tal
FS0, FS1, FS2, FS3 bit
XTL1-0 pin = ”H,H”
FS0, FS1, FS2, FS3, PEM bit
XTL1
0
0
1
1
XTL0
0
1
0
1
X’tal Frequency
11.2896MHz
12.288MHz
24.576MHz
Default
Table 19.
XTL1,0= “1,1”
XTL1,0= “1,1”
Register output
fs
Clock comparison
(Note 1)
FS3
FS2
FS1
FS0
0
0
0
0
1
1
1
1
Note 1:
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
44.1kHz
Reserved
48kHz
32kHz
88.2kHz
96kHz
176.4kHz
192kHz
±3%
44.1kHz
Reserved
48kHz
32kHz
88.2kHz
96kHz
176.4kHz
192kHz
Consumer
mode
(Note 2)
Byte3
Bit3,2,1,0
0000
0001
0010
0011
(1000)
(1010)
(1100)
(1110)
Table
32kHz∼192kHz
Professional mode
Byte0
Bit7,6
01
10
11
00
00
00
00
Byte4
Bit6,5,4,3
0000
(Others)
0000
0000
1010
0010
1011
0011
FS3-0 bit =
“0001”
Note 2:
Byte3 Bit3-0
FS3-0 bit
Table 20.
PEM bit
(CS12=0
)
1
CS12 bit = “1”
2
PEM
0
1
Table 21.
PEM
0
1
Table 22.
Pre-emphasis
OFF
ON
Pre-emphasis
OFF
ON
MS0339-J-00
Byte 0
Bits 3-5
≠ 0X100
0X100
Byte 0
Bits 2-4
≠110
110
2004/09
- 45 -
ASAHI KASEI
IIR
[AK4589]
4
(32kHz, 44.1kHz, 48kHz, 96kHz)
DEAU bit = “1”
FS3-0 bit
(50/15µs
)
DEAU bit = “0”
OFF
PEM bit =
DEM0/1, DFS bit
“0”
PEM
1
1
1
1
1
0
FS3
0
0
0
1
FS1
0
1
1
1
FS0
0
0
1
0
Mode
44.1kHz
48kHz
32kHz
96kHz
OFF
x
OFF
(DEAU bit = “1”: Default)
(Others)
x
Table 23.
PEM
1
1
1
1
1
1
1
1
0
Table 24.
AK4589
FS2
0
0
0
0
x
x
DFS
0
0
0
0
1
1
1
1
x
DEM1
0
0
1
1
0
0
1
1
x
PDN pin
DEM0
0
1
0
1
0
1
0
1
x
Mode
44.1kHz
OFF
48kHz
32kHz
OFF
OFF
96kHz
OFF
OFF
(DEAU bit = “0”)
PWN bit
PDN pin
Default
RSTN bit
“L”
PDN pin:
“L”
PDN pin ADC/DAC
RSTN bit (
00H D0):
“0”
PWN bit RSTN bit
“0”
PWN bit (
SDTO2 pin
“L”
PWN bit
RSTN bit
00H D1):
“0”
PLL
X’tal
MS0339-J-00
2004/09
- 46 -
ASAHI KASEI
[AK4589]
8
(RX0-7)
IPS2-0 bit
200mVpp
“1”
BCU bit =
Block start, C,U bit
IPS2
0
0
0
0
1
1
1
1
IPS1
0
0
1
1
0
0
1
1
Table 25.
IPS0
0
1
0
1
0
1
0
1
INPUT Data
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
Default
B
1/4fs
COUT (or U,V)
SDTO2
C(R191)
C(L0)
R190
C(R0)
L191
C(L1)
R191
L0
C(L39)
L38
C(R39) C(L40)
R38
L39
LRCK2
2
(except I S)
LRCK2
2
(I S)
Figure 21. B, C, U, V
MS0339-J-00
2004/09
- 47 -
ASAHI KASEI
TX0/1 pin
[AK4589]
RX
DAUX2
IEC60958
DIT bit
TX1
bit
TX0
OPS00, 01, 02
TX0/1 pin
DAUX2
(Figure 22) C bit
5Byte
bit20-23(Audio channel)
CT20
“1000”
, Sub frame 2 “0100”
“0000”
U bit UDIT bit
“0”
UDIT bit = “1”
U bit
PLL
OPS10, 11, 12 bit
8
V bit VIN pin
bit0= “0”(consumer mode)
Sub frame 1
CT20 bit
“0”
UDIT bit= “0”
U bit DIR-DIT
“1”
2
DIT
DIT
0
0
0
0
0
0
0
0
1
OPS02
0
0
0
0
1
1
1
1
OPS01
0
0
1
1
0
0
1
1
Table 26.
OPS00
0
1
0
1
0
1
0
1
Output Data
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
(TX0)
OPS12
0
0
0
0
1
1
1
1
x
OPS11
0
0
1
1
0
0
1
1
x
Table 27.
OPS10
0
1
0
1
0
1
0
1
x
Output Data
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
DAUX2
(TX1)
Default
Default
LRCK2
2
(except I S)
LRCK2
2
(I S)
DAUX2
L0
R0
L1
R1
VIN
R191
L0
R0
L1
Figure 22. DAUX2, VIN
MS0339-J-00
2004/09
- 48 -
ASAHI KASEI
[AK4589]
0.1uF
RX
75Ω
Coax
75Ω
AK4589
Figure 23.
Note: Coaxial
50mV
(Coaxial
)
RX
Optical Receiver
Optical
Fiber
470
RX
O/E
AK4589
Figure 24.
Coaxial
(
RX
RX
“H”
AK4589
)
“L”
TX
0.5V+/-20%
330
Figure 25
T1
1:1
2%
TX
100
75Ω cable
2%
DVSS
T1
Figure 25. TX
MS0339-J-00
2004/09
- 49 -
ASAHI KASEI
[AK4589]
Q-subcode
U bit
CD Q-subcode
1. Subcode sync word (S0,S1)
2. Start bit
“1”
3. Q-W 7 bit start bit
4. Start bit
8-16 bit
Q-subcode
S0
S1
S2
S3
:
S97
S0
S1
S2
S3
:
1
0
0
1
1
:
1
0
0
1
1
:
16
QINT
Q3 Q4
CTRL
Q5
Q6
Q7 Q8
ADRS
QINT bit
“0”
2
3
4
5
6
7
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Q2
R2
S2
T2
U2
V2 W2
Q3
R3
S3
T3
U3
V3 W3
:
:
:
:
:
:
:
Q97 R97 S97 T97 U97 V97 W97
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Q2
R2
S2
T2
U2
V2 W2
Q3
R3
S3
T3
U3
V3 W3
:
:
:
:
:
:
:
(*) number of "0" : min=0; max=8.
Q
Q2
“0” bit
Q9
Figure 26. U-
*
0…
0…
0…
0…
:
0…
0…
0…
0…
0…
:
(CD)
Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
TRACK NUMBER
INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49
MINUTE
SECOND
FRAME
Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73
ZERO
ABSOLUTE MINUTE
ABSOLUTE SECOND
Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97
ABSOLUTE FRAME
CRC
G(x)=x16+x12+x5+1
Figure 27.
Addr
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
D7
Q9
Q17
D6
Q8
Q16
Q
D5
D4
Q81
Q80
Figure 28. Q-subcode register
MS0339-J-00
D3
D2
D1
Q3
Q11
D0
Q2
Q10
Q75
Q74
2004/09
- 50 -
ASAHI KASEI
[AK4589]
INT1-0 pin
“H”
1. UNLOCK : PLL
2. PAR
8
“1”
:
“1”
“1”
3. AUTO
5. AUDION
: Non-Linear PCM
4096
: DTS-CD
DTS-CD sync
: AUDIO
6. PEM
:
7. QINT
:Q-subcode bit Sync
Sync
4. DTSCD
8. CINT
:
U-
“1”
Sync
“1”
PLL OFF
1024/fs (EFH0/1 bit
INT pin
1
(Clock Operation Mode 1) INT0/1 pin
“L”
)
“H”
INT1 pin
INT0 pin
“L”
“1”
PAR, QINT, CINT bit
8
OR
INT pin
INT pin
(
06H
1024/fs (EFH0/1 bit
“1”
)
)
06H
“H”
INT0 pin
PAR, QINT, CINT bit
INT0 UNLOCK, PAR
bit
UNLOCK
1
0
0
0
0
0
0
0
INT1 AUTO, DTSCD, AUDION bit
PAR
x
1
0
0
0
0
0
0
AUTO
x
x
1
x
x
x
x
x
Event
DTSCD AUDION
x
x
x
x
x
x
1
x
x
1
x
x
x
x
x
x
Pin
PEM
x
x
x
x
x
1
x
x
QINT
x
x
x
x
x
x
1
x
CINT
x
x
x
x
x
x
x
1
SDTO
“L”
Previous Data
Output
Output
Output
Output
Output
Output
V
“L”
Output
Output
Output
Output
Output
Output
Output
TX
Output
Output
Output
Output
Output
Output
Output
Output
Table 28.
MS0339-J-00
2004/09
- 51 -
ASAHI KASEI
Error
(UNLOCK, PAR,..)
[AK4589]
(Error)
INT0 pin
Hold Time (max: 4096/fs)
INT1 pin
Hold Time = 0
Register
(PAR,CINT,QINT)
Reset
Hold ”1”
Register
(others)
Command
MCKO,BICK2,LRCK2
(UNLOCK)
MCKO,BICK2,LRCK2
(except UNLOCK)
READ 06H
Free Run
(fs: around 20kHz)
SDTO2 (UNLOCK)
SDTO2
(PAR error)
Previous Data
SDTO2
(others)
Vpin
(UNLOCK)
Vpin
(except UNLOCK)
Normal Operation
Figure 29. INT0-1 pin
MS0339-J-00
2004/09
- 52 -
ASAHI KASEI
[AK4589]
PDN pin ="L" to "H"
Initialize
Read 06H
INT0/1 pin ="H"
No
Yes
Release
Muting
Mute DAC output
Read 06H
(Each Error Handling)
Read 06H
(Resets registers)
No
INT0/1 pin ="H"
Yes
Figure 30.
1
MS0339-J-00
2004/09
- 53 -
ASAHI KASEI
[AK4589]
PDN pin ="L" to "H"
Initialize
Read 06H
No
INT1 pin ="H"
Yes
Read 06H
and
Detect QSUB= “1”
(Read Q-buffer)
QCRC = “0”
No
New data
is invalid
Yes
INT1 pin ="L"
No
Yes
New data
is valid
Figure 31.
2 (Q/CINT)
MS0339-J-00
2004/09
- 54 -
ASAHI KASEI
[AK4589]
8
(Table 29)
SDTO2 BICK2 1
BICK2 64fs
20
4
Aux
Mode0-5
128fs
Mode 3-7
(
MSB
DAUX2
Mode 6-7 Mode 4-5
(Mode0-2)
Figure 32
)
BICK2
Parity Error
BICK2
LSB
(PDN pin = “L”)
LRCK2
Hi-Z
SDTO2
“L”
“0”
SDTO2
DAUX2 pin
, Left justified
SDTO2
I2 S
LRCK2 BICK2
Clock Mode 2
Clock Mode 3
Mode 5, 7
24
Mode 5, 7
Mode4-5
fs=48kHz
(PDN pin = “H”)
PLL
unlock
2’s complement
DAUX2
Clock Mode 1 PLL
DAUX2
Mode 6-7
MCKO1/2
sub-frame of IEC60958
0
3 4
preamble
7 8
11 12
27 28 29 30 31
Aux.
V U C P
LSB
MSB
MSB
LSB
23
0
AK4589 Audio Data (MSB First)
Figure 32.
Mode
DIF2
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
DIF1 DIF0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAUX2
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
Table 29.
SDTO2
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
MS0339-J-00
LRCK2
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
H/L
I
L/H
I
BICK2
64fs
64fs
64fs
64fs
64fs
64fs
64-128fs
64-128fs
I/O
O
O
O
O
O
O
I
I
Default
2004/09
- 55 -
ASAHI KASEI
[AK4589]
LRCK2
0
1
2
15
16
17
31
0
1
2
15
16
17
31
0
1
0
1
0
1
BICK2
(0:64fs)
15
SDTO2
14
1
0
15
14
1
0
15:MSB, 0:LSB
Rch Data
Lch Data
Figure 33. Mode 0
LRCK2
0
1
2
9
10
12
11
31
0
1
2
9
10
11
31
12
BICK2
(0:64fs)
23
SDTO2
1
20
21
22
0
23
22
21
1
20
0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 34. Mode 3
LRCK2
0
1
2
21
22
24
23
31
0
1
2
21
22
23
31
24
BICK2
(64fs)
22 21
23
SDTO2
2
23 22
0
1
3
1
2
0
23 22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 35. Mode 4, 6
Mode4 : LRCK2, BICK2 : Output
Mode6 : LRCK2, BICK2 : Input
LRCK2
0
1
2
22
24
23
25
31
0
1
2
21
22
23
24
25
31
0
1
BICK2
(64fs)
SDTO2
23
22 21
2
1
23 22
0
3
2
1
0
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 36. Mode 5, 7
MS0339-J-00
Mode5 : LRCK2, BICK2 : Output
Mode7 : LRCK2, BICK2 : Input
2004/09
- 56 -
ASAHI KASEI
Addr
[AK4589]
D7
D6
D5
D4
D3
D2
D1
D0
CS12
BCU
CM1
CM0
OCKS1
OCKS0
PWN
RSTN2
01H
Register Name
CLK & Power Down
Control
Format & De-em Control
0
DIF2
DIF1
DIF0
DEAU
DEM1
DEM0
DFS
02H
Input/ Output Control 0
TX1E
OPS12
OPS11
OPS10
TX0E
OPS02
OPS01
OPS00
03H
Input/ Output Control 1
EFH1
EFH0
UDIT
0
DIT
IPS2
IPS1
IPS0
04H
INT0 MASK
MQIT0 MAUT0 MCIT0
MULK0 MDTS0
MPE0
MAUD0
MPAR0
05H
INT1 MASK
MQIT1 MAUT1 MCIT1
MULK1 MDTS1
MPE1
MAUD1
MPAR1
06H
Receiver status 0
QINT
AUTO
CINT
UNLCK DTSCD
PEM
AUDION
PAR
07H
Receiver status 1
FS3
FS2
FS1
FS0
0
V
QCRC
CCRC
08H
RX Channel Status Byte 0
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
09H
RX Channel Status Byte 1
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
0AH
RX Channel Status Byte 2
CR23
CR22
CR21
CR20
CR19
CR18
CR17
CR16
0BH
RX Channel Status Byte 3
CR31
CR30
CR29
CR28
CR27
CR26
CR25
CR24
0CH
RX Channel Status Byte 4
CR39
CR38
CR37
CR36
CR35
CR34
CR33
CR32
0DH
TX Channel Status Byte 0
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
0EH
TX Channel Status Byte 1
CT15
CT14
CT13
CT12
CT11
CT10
CT9
CT8
0FH
TX Channel Status Byte 2
CT23
CT22
CT21
CT20
CT19
CT18
CT17
CT16
10H
TX Channel Status Byte 3
CT31
CT30
CT29
CT28
CT27
CT26
CT25
CT24
11H
TX Channel Status Byte 4
CT39
CT39
CT39
CT39
CT39
CT39
CT39
CT32
12H
Burst Preamble Pc Byte 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
13H
Burst Preamble Pc Byte 1
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
14H
Burst Preamble Pd Byte 0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
15H
Burst Preamble Pd Byte 1
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
16H
Q-subcode Address / Control
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
17H
Q-subcode Track
Q17
Q16
Q15
Q14
Q13
Q12
Q11
Q10
18H
Q-subcode Index
Q25
Q24
Q23
Q22
Q21
Q20
Q19
Q18
19H
Q-subcode Minute
Q33
Q32
Q31
Q30
Q29
Q28
Q27
Q26
1AH
Q-subcode Second
Q41
Q40
Q39
Q38
Q37
Q36
Q35
Q34
1BH
Q-subcode Frame
Q49
Q48
Q47
Q46
Q45
Q44
Q43
Q42
1CH
Q-subcode Zero
Q57
Q56
Q55
Q54
Q53
Q52
Q51
Q50
1DH
Q-subcode ABS Minute
Q65
Q64
Q63
Q62
Q61
Q60
Q59
Q58
1EH
Q-subcode ABS Second
Q73
Q72
Q71
Q70
Q69
Q68
Q67
Q66
1FH
Q-subcode ABS Frame
Q81
Q80
Q79
Q78
Q77
Q76
Q75
Q74
00H
: PDN pin
“L”
RSTN2 bit
“0”
PWN bit
“0”
“0”
“0”
MS0339-J-00
2004/09
- 57 -
ASAHI KASEI
[AK4589]
Reset & Initialize
Addr
Register Name
00H CLK & Power Down Control
R/W
Default
D7
CS12
R/W
0
D6
BCU
R/W
1
D5
CM1
R/W
0
D4
CM0
R/W
0
D3
D2
OCKS1 OCKS0
R/W
R/W
0
0
D1
PWN
R/W
1
D0
RSTN2
R/W
1
RSTN2:
0:
1:
&
PWN:
0:
1:
OCKS1-0:
CM1-0:
BCU:
, C, U
BCU bit = 1
3
(BOUT, COUT, UOUT)
frame 39
frame 0
“H”
CS12:
0: Channel 1
1: Channel 2
C bit, AUDION, PEM, FS3-0, Pc, Pd
Format & De-emphasis Control
Addr
Register Name
01H Format & De-em Control
R/W
Default
D7
0
R/W
0
D6
DIF2
R/W
1
DFS: 96kHz
DEM1-0: 32, 44.1, 48kHz
DEAU:
0: Disable
1: Enable
DIF2-0:
D5
DIF1
R/W
1
D4
DIF0
R/W
0
D3
DEAU
R/W
1
D2
DEM1
R/W
0
D1
DEM0
R/W
1
D0
DFS
R/W
0
(Table 24)
(Table 29)
MS0339-J-00
2004/09
- 58 -
ASAHI KASEI
[AK4589]
Input/Output Control
Addr
Register Name
02H Input/ Output Control 0
R/W
Default
OPS02-00:
OPS12-10:
TX0E: TX0
0:
1:
TX1E: TX1
0:
1:
D7
TX1E
R/W
1
D6
D5
D4
OPS12 OPS11 OPS10
R/W
R/W
R/W
0
0
0
D3
TX0E
R/W
1
D2
D1
D0
OPS02 OPS01 OPS00
R/W
R/W
R/W
0
0
0
(TX0 pin)
(TX1 pin)
TX0 pin
“L”
TX1 pin
“L”
Addr
Register Name
03H Input/ Output Control 1
R/W
Default
D7
EFH1
R/W
0
D6
EFH0
R/W
1
D5
UDIT
R/W
0
IPS2-0:
DIT: TX1 pin
0:
(RX
)
1:
(DAUX2
)
UDIT: DIT U bit
0: U bit
“0”
1:
U bit
EFH1-0: INT0 pin
00: 512 LRCK2
01: 1024 LRCK2
10: 2048 LRCK2:
11: 4096 LRCK2
MS0339-J-00
D4
0
R/W
0
D3
DIT
R/W
1
(U bit
D2
IPS2
R/W
0
D1
IPS1
R/W
0
D0
IPS0
R/W
0
)
2004/09
- 59 -
ASAHI KASEI
[AK4589]
Mask Control for INT0
Addr
Register Name
04H INT0 MASK
R/W
Default
MPR0:
MAN0:
MPE0:
MDTS0:
MUL0:
MCI0:
MAT0:
MQI0:
D7
MQI0
R/W
1
D6
MAT0
R/W
1
D5
MCI0
R/W
1
D4
MUL0
R/W
0
D3
MDTS0
R/W
1
D2
MPE0
R/W
1
D1
MAN0
R/W
1
D0
MPR0
R/W
0
D7
MQI1
R/W
1
D6
MAT1
R/W
0
D5
MCI1
R/W
1
D4
MUL1
R/W
1
D3
MDTS1
R/W
0
D2
MPE1
R/W
1
D1
MAN1
R/W
0
D0
MPR1
R/W
1
PAR bit
AUDN bit
PEM bit
DTSCD bit
UNLOCK bit
CINT bit
AUTO bit
QINT bit
0:
1:
Mask Control for INT1
Addr
Register Name
05H INT1 MASK
R/W
Default
MPR1:
MAN1:
MPE1:
MDTS1:
MUL1:
MCI1:
MAT1:
MQI1:
PAR bit
AUDN bit
PEM bit
DTSCD bit
UNLOCK bit
CINT bit
AUTO bit
QINT bit
0:
1:
MS0339-J-00
2004/09
- 60 -
ASAHI KASEI
[AK4589]
Receiver Status 0
Addr
Register Name
06H Receiver status 0
R/W
Default
D7
QINT
RD
0
D6
AUTO
RD
0
D5
CINT
RD
0
D4
D3
UNLCK DTSCD
RD
RD
0
0
D2
PEM
RD
0
D1
AUDION
RD
0
D0
PAR
RD
0
PAR:
0:No Error
1:Error
PAR bit
AUDION: Audio bit
0: Audio
“1”
1: Non Audio
PEM:
0: OFF
1: ON
DTSCD: DTS-CD
0:
UNLCK: PLL
0:
CINT:
0:
AUTO: Non-PCM
0:
QINT: Q
0:
QINT, CINT, PAR bit
1:
1:
1:
1:
1:
06H READ
Receiver Status 1
Addr
Register Name
07H Receiver status 1
R/W
Default
D7
FS3
RD
0
CCRC:
D6
FS2
RD
0
D5
FS1
RD
0
D4
FS0
RD
1
D3
0
RD
0
D2
V
RD
0
D1
QCRC
RD
0
D0
CCRC
RD
0
CRC
0:
QCRC: Q
1:
CRC
0:
1:
V:
0:Valid
FS3-0:
1:Invalid
(Table 20)
MS0339-J-00
2004/09
- 61 -
ASAHI KASEI
[AK4589]
Receiver Channel Status
Addr
08H
09H
0AH
0BH
0CH
Register Name
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
R/W
Default
D7
CR7
CR15
CR23
CR31
CR39
D6
CR6
CR14
CR22
CR30
CR38
D5
CR5
CR13
CR21
CR29
CR37
D4
CR4
CR12
CR20
CR28
CR36
D3
CR3
CR11
CR19
CR27
CR35
D2
CR2
CR10
CR18
CR26
CR34
D1
CR1
CR9
CR17
CR25
CR33
D0
CR0
CR8
CR16
CR24
CR32
D2
CT2
CT10
CT18
CT26
CT34
D1
CT1
CT9
CT17
CT25
CT335
D0
CT0
CT8
CT16
CT24
CT32
D2
PC2
PC10
PD2
PD10
D1
PC1
PC9
PD1
PD9
D0
PC0
PC8
PD0
PD8
RD
Not initialized
CR39-0:
Byte 4-0
Transmitter Channel Status
Addr
0DH
0EH
0FH
10H
11H
Register Name
TX Channel Status Byte 0
TX Channel Status Byte 1
TX Channel Status Byte 2
TX Channel Status Byte 3
TX Channel Status Byte 3
R/W
Default
D7
CT7
CT15
CT23
CT31
CT39
D6
CT6
CT14
CT22
CT30
CT38
CT39-0:
D5
CT5
CT13
CT21
CT29
CT37
D4
D3
CT4
CT3
CT12 CT11
CT20 CT19
CT28 CT27
CT36 CT35
R/W
0
Byte 4-0
Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams
Addr
12H
13H
14H
15H
Register Name
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
R/W
Default
D7
PC7
PC15
PD7
PD15
D6
PC6
PC14
PD6
PD14
PC15-0:
PD15-0:
Pc Byte 0, 1
Pd Byte 0, 1
D5
PC5
PC13
PD5
PD13
D4
PC4
PC12
PD4
PD12
D3
PC3
PC11
PD3
PD11
RD
Not initialized
MS0339-J-00
2004/09
- 62 -
ASAHI KASEI
[AK4589]
Q-subcode Buffer
Addr
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
R/W
Default
D7
Q9
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
Q81
D6
Q8
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
Q80
D5
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
D4
Q6
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
D3
Q5
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
D2
Q4
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
D1
Q3
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
D0
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
RD
Not initialized
MS0339-J-00
2004/09
- 63 -
ASAHI KASEI
[AK4589]
Non-PCM
sub-frame of IEC60958
0
3 4
preamble
7 8
11 12
Aux.
27 28 29 30 31
LSB
MSB V U C P
16 bits of bitstream
0
Pa Pb Pc Pd
15
Burst_payload
stuffing
repetition time of the burst
Figure 37. IEC60958
Preamble word
Pa
Pb
Pc
Pd
Length of field
16 bits
16 bits
16 bits
16 bits
Table 30.
Contents
sync word 1
sync word 2
Burst info
Length code
MS0339-J-00
Value
0xF872
0x4E1F
see Table 31
numbers of bits
2004/09
- 64 -
ASAHI KASEI
Bits of Pc
Value
0-4
5, 6
7
8-12
13-15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
0
0
1
0
[AK4589]
Contents
Repetition time of burst
in IEC60958 frames
data type
NULL data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 without extension
MPEG-2 data with extension
MPEG-2 AAC ADTS
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
reserved, shall be set to “0”
error-flag indicating a valid burst_payload
error-flag indicating that the burst_payload may contain
errors
data type dependent info
bit stream number, shall be set to “0”
Table 31.
Pc
MS0339-J-00
≤4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
2004/09
- 65 -
ASAHI KASEI
[AK4589]
Non-PCM
1) Non-PCM
4096
PDN pin
Bit stream
Pa Pb Pc1 Pd1
Pa Pb Pc2 Pd2
Repetition time
Pa Pb Pc3 Pd3
>4096 frames
AUTO bit
Pc Register
“0”
Pd Register
“0”
Pc1
Pc2
Pd1
Pd2
Figure 38.
2) Non-PCM
Pc3
Pd3
1
(MULK0=0
)
INT0 hold time
INT0 pin
<20mS (Lock time)
Bit stream
Pa Pb Pc1 Pd1
Stop
Pa Pb Pcn Pdn
2~3 Syncs (B,M or W)
<Repetition time
AUTO bit
Pc Register
Pd Register
Pc0
Pc1
Pd0
Pcn
Pd1
Figure 39.
Pdn
2
MS0339-J-00
2004/09
- 66 -
ASAHI KASEI
[AK4589]
(ADC/DAC
AK4589
ADC/DAC
, DIR/DIT
(AK4588
(1) 4
)
)
DI/DIT
(AK4588
)
(I2C pin = “L”)
4
I/F (CSN, CCLK, CDTI, CDTO)
I/F
Chip address (2bits, AK4589
ADC/DAC
CAD1-0 pin
DIR/DIT
”00”
), Read/Write (1bit), Register address (MSB first, 5bits)
Control Data (MSB first, 8bits)
CCLK “↓”
“↑”
CSN “↑”
CSN “↑”
Hi-Z
CCLK
5MHz (max)
PDN pin= “L”
ADC/DAC
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
WRITE
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
CDTI
READ
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
C1,C0:
R/W:
A4-A0:
D7-D0:
D7 D6 D5 D4 D3 D2 D1 D0
Chip Address: (ADC/DAC
CAD1,CAD0 pin
CAD1=CAD0 = ”L”
(DIR/DIT
”00”
)
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
Figure 40. 4
Hi-Z
)
I/F
MS0339-J-00
2004/09
- 67 -
ASAHI KASEI
[AK4589]
(2) I2C
AK4589
(I2C pin = “H”)
I2C
(max:100kHz)
(max:400kHz)
ADC/DAC
(2)-1
·
1
·
READ
WRITE
·
(2)-1-1.
SDA
SCL
“L”
“L”
“H”
“H”
“H”
SCL
“L”
SDA
SDA
SCL
·
·
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 41.
(2)-1-2.
SCL
“H”
SDA
“H”
·
“L”
SCL
·
·
“H”
·
SDA
“L”
“H”
SCL
SDA
START CONDITION
Figure 42.
STOP CONDITION
·
·
MS0339-J-00
2004/09
- 68 -
ASAHI KASEI
[AK4589]
(2)-1-3.
IC
1
SDA
IC
SDA
(HIGH
)
“L”
AK4589
WRITE
AK4589
·
READ
SDA
·
SDA
AK4589
·
AK4589
(
)ADC,DAC
READ
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 43.
(2)-1-4.
1
1
·
·
5
pin
“1”
“00100”
2
7
IC
·
1
R/W bit= “0”
READ
0
0
1
8
WRITE
0
0
(
CAD1
(ADC,DAC
CAD1,CAD0
CAD1=CAD0=”0”
(DIR
”00”
)
Figure 44.
)
CAD0
CAD1,CAD0
IC
R/W bit
R/W bit=
R/W
)
1
MS0339-J-00
2004/09
- 69 -
ASAHI KASEI
[AK4589]
(2)-2. WRITE
R/W bit
“0”
AK4589
2
Don’t care
3
*
WRITE
WRITE
2
MSB first
*
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 45.
2
3
8
D7
D6
D5
D4
Figure 46.
D3
MSB first
D2
D1
D0
3
AK4589
1
1FH
S
T
A
R
T
SDA
·
Register
Address(n)
Slave
Address
·
00H
S
T
Data(n+x) O
P
Data(n+1)
Data(n)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 47. WRITE
MS0339-J-00
2004/09
- 70 -
ASAHI KASEI
[AK4589]
(2)-3. READ
R/W bit
“1”
·
AK4589
READ
1FH
00H
ADC/DAC
AK4589
·
·
·
READ
(2)-3-1.
AK4589
·
·
·
AK4589 READ
·
·
·
(READ
WRITE
n+1
(R/W bit = “1”)
·
)
n
·
·
·
1
1
READ
·
S
T
A
R
T
SDA
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+2)
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 48. CURRENT ADDRESS READ
(2)-3-2.
·
·
·
(R/W bit = “1”)
·
·
WRITE
WRITE
·
READ
(R/W bit = “0”)
AK4589
·
READ
·
(R/W bit = “1”)
AK4589
·
1
·
READ
S
T
A
R
T
SDA
Slave
Address
S
T
A
R
T
Word
Address(n)
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 49. RANDOM READ
MS0339-J-00
2004/09
- 71 -
ASAHI KASEI
[AK4589]
Figure 50
(AKD4589)
:I2C
5
Micro
Controller
S/PDIF out
(S/PDIF
sources)
S/PDIF sources
+
C1
NC 62
RX3 63
PVSS 64
R 65
RX4 67
PVDD 66
RX5 69
TEST2 68
RX6 71
CAD0 70
CAD1 72
I2C 74
RX7 73
VIN 76
TX0 78
DAUX2 75
TEST1 60
1
INT1
2
BOUT
3
TVDD
NC 58
4
DVDD
RX0 57
5
DVSS
AVSS 56
6
XTO
AVDD 55
7
XTI
VREFH 54
RX1 59
X’tal
C1
8
TEST3
9
MCKO2
(Micro
Controller)
(Shield)
+
0.1u 10u
Analog 5V
0.1u 2.2u
VCOM 53
+
RIN 52
AK4589
10 MCKO1
11 COUT
LIN 51
C2
ROUT1+ 50
12 UOUT
ROUT1- 49
13 VOUT
LOUT1+ 48
14 SDTO2
LOUT1- 47
LPF
MUTE
LPF
MUTE
LPF
MUTE
LPF
MUTE
LPF
MUTE
C2
C2
15 BICK2
ROUT2+ 46
16 LRCK2
ROUT2- 45
C2
17 SDTO1
LOUT2+ 44
18 BICK1
LOUT2- 43
ROUT3+ 42
Audio DSP
(MPEG/AC3)
LOUT3+
ROUT3-
41
LPF
MUTE
C2
LPF
MUTE
Micro
Controller
C2
LPF
MUTE
C2
39 LOUT3-
38 ROUT4+
37 ROUT4-
36 LOUT4+
35 LOUT4-
34 DZF1
33 DZF2
32 MASTER
31 PDN
29 XTL1
30 XTL0
27 SDTI2
28 SDTI1
26 SDTI3
25 SDTI4
23 CSN
21 SCL
22 SDA
20 CDTO
24 DAUX1
19 LRCK1
C2
40
Audio DSP
(MPEG/AC3)
(S/PDIF
Source)
Digital 5V
MCLK 77
12k
0.1u
+
TX1 79
INT0 80
10u
RX2 61
0.1u
Audio DSP
(MPEG/AC3)
3.3V to 5V
Digital
(Shield)
10u
+
Micro Controller
Digital Ground
Analog Ground
Figure 50
Note
- C1
- C2
470pF
- AVSS, DVSS, PVSS
-
R
RCA
AK4589
MS0339-J-00
PVSS
2004/09
- 72 -
ASAHI KASEI
[AK4589]
1.
AVDD, DVDD, PVDD
AVDD, DVDD, PVDD
AVSS, DVSS, PVSS
PC
2.
VREFH pin
AVSS pin
VREFH pin AVDD pin
VCOM pin AVDD/2
2.2µF
0.1µF
0.1µF
AVSS
VCOM pin
VREFH pin,VCOM pin
3.
ADC
VREFH Vpp (typ)@fs=48kHz
AK4589
2’s complement(2
AK4589
AVSS
)
VCOM
AVDD
DC
0.62 x
HPF
64fs
64fs
AK4589
(RC
64fs
)
4.
DAC
(typ)
AOUT+ AOUT5.4Vpp (typ @VREF=5V)
2’s complement
1
800000H(@24bit)
AOUT+/AOUT)
MS0339-J-00
DC
AVDD/2
0.54 x VREF Vpp
VAOUT=(AOUT+)-(AOUT-)
7FFFFFH(@24bit)
000000H(@24bit)
AOUT
(
=
0V
AVDD/2
C
2004/09
- 73 -
ASAHI KASEI
[AK4589]
5.
AK4589
LPF
NJM5534D
+15
3.3n
+
100u
+
10k
AOUTL-
180
330
7
3
2 +
4
3.9n
-15
10u
0.1u
6
NJM5534D
+
10u
0.1u
620
+
3
+
2 -
+
330
3.9n
- 4
3 + 7
Lch
1.0n NJM5534D
10u
6
4
680
100
6
0.1u
7
NJM5534D
1.2k
10k
AOUTL+
180
2
560
620
3.3n
100u
+10u
1.0n
1.2k
680
0.1u
560
+
0.1u
10u
+
10u
0.1u
Figure 51. External 2nd order LPF Circuit Example
MS0339-J-00
2004/09
- 74 -
ASAHI KASEI
[AK4589]
80-pin LQFP
( Unit : mm )
14.0±0.2
12.0±0.2
41
61
40
80
21
12.0±0.2
1
20
0.08
0.125+0.10
-0.05
0.50±0.1
0.10
(
M
+0.15
0.10 -0.10
0.50
1.25TYP
1.85MAX
0° ~ 10°
0.20±0.1
1.40±0.2
14.0±0.2
60
)
MS0339-J-00
2004/09
- 75 -
ASAHI KASEI
[AK4589]
AK4589VQ
XXXXXXX
1) Pin #1 indication
2) Asahi Kasei Logo
3) Marking Code: AK4589VQ
4) Date Code: XXXXXXX(7 digits)
Date (YY/MM/DD)
04/09/06
Revision
00
Reason
First Edition
Page
Contents
•
•
•
•
•
•
MS0339-J-00
2004/09
- 76 -