データシート

[AK4588]
AK4588
2/8-Channel Audio CODEC with DIR
AK4588
2ch ADC
8ch DAC
1
24bit CODEC
DAC
ADC
AK4588
102dB
AK4588
*Dolby Digital
ADC
192kHz 24 bit
DIR
8
AK4588
AK4628A
106dB
DAC
Dolby Digital(AC-3)
(DIR)
(DIT)
Non-PCM
AK4114
Dolby Laboratories
† ADC, DAC
† 2ch 24bit ADC
- 64
:
96kHz
- S/(N+D): 92dB
, S/N: 102dB
HPF
- I/F
:
, I2S, TDM
† 8ch 24bit DAC
- 128
:
192kHz
- 24
8
- S/(N+D): 90dB
, S/N: 106dB
- I/F
:
,
(20bit,24bit), I2S, TDM
(128
, 0.5dB
(32kHz, 44.1kHz, 48kHz
)
†
†
: 256fs, 384fs, 512fs (fs=32kHz ∼ 48kHz)
128fs, 192fs, 256fs (fs=64kHz ∼ 96kHz)
128fs (fs=120kHz~ 192kHz)
MS0287-J-03
)
2009/05
-1-
[AK4588]
† DIR,DIT
† AES3, IEC60958, S/PDIF, EIAJ CP1201
†
PLL
† PLL
: 32kHz ∼ 192kHz
† PLL/X'tal
†
8
†
2
(
or
)
†
†
(32kHz, 44.1kHz, 48kHz, 96kHz)
†
- Non-PCM
- DTS-CD
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
- Unlock & Parity Error
- Validity
† 24
†
I/F:
/
†
40
† Non-PCM
Pc, Pd
† CD Q-subcode
† 64fs/128fs/256fs/512fs
† TTL
†
†
†
†
I/F
µP I/F
(I2C, 4
)
: 4.5 ∼ 5.5V
: 2.7 ∼ 5.5V
: 80pin LQFP(0.5mm pitch)
MS0287-J-03
2009/05
-2-
[AK4588]
■
PVSS PVDD
R
XTI
XTO
RX0
X'tal
Clock
Recovery
RX1
RX2
RX3
RX4
RX5
8 to 3
Oscillator
Clock
Generator
Input
MCKO1
MCKO2
Selector
DEM
RX6
DAIF
RX7
Audio
Decoder
I/F
LRCK2
BICK2
SDTO2
TX0
DAUX2
PDN
TX1
AVDD
I2C
DIT
AVSS
DVDD
CSN
AC-3/MPEG
DVSS
TVDD
VIN
Detect
Error &
STATUS
Detect
Q-subcode
buffer
CCLK
CDTO
CDTI
INT0
INT1
B,C,U,
VOUT
ADC
LIN
RIN
LOUT1
μP I/F
LPF
HPF
Audio
I/F
ADC
HPF
DAC
DATT
DEM
MCLK
MCLK
LRCK
BICK
LRCK1
BICK1
ROUT1
LPF
DAC
DATT
DEM
LOUT2
LPF
DAC
DATT
DEM
ROUT2
LPF
DAC
DATT
DEM
LOUT3
LPF
DAC
DATT
DEM
ROUT3
LPF
DAC
DATT
DEM
LOUT4
LPF
DAC
DATT
DEM
ROUT4
LPF
DAC
DATT
DEM
DAUX1
Format
Converter
SDOUT
SDTO1
SDIN1
SDIN2
SDIN3
SDIN4
MS0287-J-03
SDTI1
SDTI2
SDTI3
SDTI4
2009/05
-3-
[AK4588]
■
-40 ∼ +85°C
AK4588VQ
AKD4588
80pin LQFP(0.5mm pitch)
(Top View)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
LOUT3
NC
ROUT4
NC
LOUT4
DZF1
DZF2
MASTER
PDN
XTL0
XTL1
SDTI1
SDTI2
SDTI3
SDTI4
DAUX1
CSN
CDTI/SDA
CCLK/SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
INT1
BOUT
TVDD
DVDD
DVSS
XTO
XTI
TEST3
MCKO2
MCKO1
COUT
UOUT
VOUT
SDTO2
BICK2
LRCK2
SDTO1
BICK1
LRCK1
CDTO
RX2
NC
RX3
PVSS
R
PVDD
RX4
TEST2
RX5
CAD0
RX6
CAD1
RX7
I2C
DAUX2
VIN
MCLK
TX0
TX1
INT0
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
60
59
TEST1
RX1
NC
RX0
AVSS
AVDD
VREFH
VCOM
RIN
LIN
NC
ROUT1
NC
LOUT1
NC
ROUT2
NC
LOUT2
NC
ROUT3
■
MS0287-J-03
2009/05
-4-
[AK4588]
■ AK4628 + AK4114
Functions
AK4628+ AK4114
AK4588
TDM0, DFS0, DZFE, SDOS,
SMUTE pin
4 wire serial
(I2C pin= “L”)
(*)
( )AK4588
)
AK4628: CAD1-0 pin
AK4114: “00”
I2C Bus
AK4628: CAD1-0 pin
(I2C pin= “H”)
AK4114: CAD1-0 pin
ADC/DAC
(AK4628
MS0287-J-03
ADC/DAC part:CAD1-0 pin
DIR/DIT part:“00”
ADC/DAC part:CAD1-0 pin
DIR/DIT part:“00”
) DIR/DIT
(AK4114
2009/05
-5-
[AK4588]
No.
1
Pin Name
INT1
I/O
O
2
3
4
5
6
7
BOUT
O
TVDD
DVDD
DVSS
XTO
XTI
O
I
8
TEST3
I
9
10
11
12
13
14
15
16
17
18
19
20
MCKO2
MCKO1
COUT
UOUT
VOUT
SDTO2
BICK2
LRCK2
SDTO1
BICK1
LRCK1
CDTO
CCLK
SCL
CDTI
SDA
21
22
23
CSN
24
25
26
27
28
29
30
DAUX1
SDTI4
SDTI3
SDTI2
SDTI1
XTL1
XTL0
O
O
O
O
O
O
I/O
I/O
O
I/O
I/O
O
I
I
I
I/O
I
I
I
I
I
I
I
I
I
Function
Interrupt 1 Pin
Block-Start Output Pin for Receiver Input
“H” during first 40 flames.
Output Buffer Power Supply Pin, 2.7V∼5.5V
Digital Power Supply Pin, 4.5V∼5.5V
Digital Ground Pin
X'tal clock Output Pin
X'tal / External clock Input Pin
Test 3 Pin
This pin should be connected to DVSS.
Master Clock Output 2 Pin
Master Clock Output 1 Pin
C-bit Output Pin for Receiver Input
U-bit Output Pin for Receiver Input
V-bit Output Pin for Receiver Input
Audio Serial Data Output Pin (DIR/DIT part)
Audio Serial Data Clock Pin (DIR/DIT part)
Channel Clock Pin (DIR/DIT part)
Audio Serial Data Output Pin (ADC/DAC part)
Audio Serial Data Clock Pin (ADC/DAC part)
Input Channel Clock Pin
Control Data Output Pin in Serial Mode, I2C pin= “L”.
Control Data Clock Pin in Serial Mode, I2C pin= “L”
Control Data Clock Pin in Serial Mode, I2C pin= “H”
Control Data Input Pin in Serial Mode, I2C pin= “L”.
Control Data Pin in Serial Mode, I2C pin= “H”.
Chip Select Pin in Serial Mode, I2C pin=”L”.
This pin should be connected to DVSS, I2C pin=”H”.
AUX Audio Serial Data Input Pin (ADC/DAC part)
DAC4 Audio Serial Data Input Pin
DAC3 Audio Serial Data Input Pin
DAC2 Audio Serial Data Input Pin
DAC1 Audio Serial Data Input Pin
X’tal Frequency Select 0 Pin
X’tal Frequency Select 1 Pin
MS0287-J-03
2009/05
-6-
[AK4588]
No.
Pin Name
I/O
31
PDN
I
32
MASTER
I
DZF2
O
OVF
O
34
DZF1
O
35
LOUT4
O
36
NC
-
37
ROUT4
O
38
NC
-
39
LOUT3
O
40
NC
-
41
ROUT3
O
42
NC
-
43
LOUT2
O
44
NC
-
45
ROUT2
O
46
NC
-
47
LOUT1
O
48
NC
-
49
ROUT1
O
50
NC
-
51
52
LIN
RIN
I
I
53
VCOM
-
54
VREFH
-
33
Function
Power-Down Mode Pin
When “L”, the AK4588 is powered-down, all output pin goes “L”, all registers are
reset. When CAD1-0 pins are changed, the AK4588 should be reset by the PDN pin.
Master Mode Select Pin
“H”: Master mode, “L”: Slave mode
Zero Input Detect 2 Pin
(Table 13)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input
data, this pin goes to “H”. When RSTN1 bit is “0” or PWDAN bit is “0”, this pin
goes to “H”.
Analog Input Overflow Detect Pin
This pin goes to “H” if the analog input of Lch or Rch overflows. This pin becomes
OVF pin if OVFE bit is set to 1.
Zero Input Detect 1 Pin
(Table 13)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input
data, this pin goes to “H”. When RSTN1 bit is “0” or PWDAN bit is “0”, this pin goes
to “H”.
DAC4 Lch Analog Output Pin
No Connect pin
No internal bonding. This pin should be opened.
DAC4 Rch Analog Output Pin
No Connect pin
No internal bonding. This pin should be opened.
DAC3 Lch Analog Output Pin
No Connect pin
No internal bonding. This pin should be opened.
DAC3 Rch Analog Output Pin
No Connect pin
No internal bonding. This pin should be opened.
DAC2 Lch Analog Output Pin
No Connect pin
No internal bonding. This pin should be opened.
DAC2 Rch Analog Output Pin
No Connect pin
No internal bonding. This pin should be opened.
DAC1 Lch Analog Output Pin
No Connect pin
No internal bonding. This pin should be opened.
DAC1 Rch Analog Output Pin
No Connect pin
No internal bonding. This pin should be opened.
Lch Analog Input Pin
Rch Analog Input Pin
Common Voltage Output Pin
2.2μF capacitor should be connected to AVSS externally.
Positive Voltage Reference Input Pin, AVDD
MS0287-J-03
2009/05
-7-
[AK4588]
No.
55
56
57
Pin Name
AVDD
AVSS
RX0
58
NC
-
59
RX1
I
60
TEST1
I
61
RX2
I
62
NC
-
63
64
RX3
PVSS
I
-
65
R
-
66
67
PVDD
RX4
I
68
TEST2
I
69
70
71
72
73
RX5
CAD0
RX6
CAD1
RX7
I
I
I
I
I
74
I2C
I
75
76
77
78
DAUX2
VIN
MCLK
TX0
I
I
I
O
79
TX1
O
INT0
O
80
Note:
I/O
I
Function
Analog Power Supply Pin, 4.5V∼5.5V
Analog Ground Pin, 0V
Receiver Channel 0 Pin (Internal biased pin. Internally biased at PVDD/2)
No Connect pin
No internal bonding. This pin should be connected to PVSS.
Receiver Channel 1 Pin (Internal biased pin. Internally biased at PVDD/2)
Test 1 Pin
This pin should be connected to PVSS.
Receiver Channel 2 Pin (Internal biased pin. Internally biased at PVDD/2)
No Connect pin
No internal bonding. This pin should be connected to PVSS.
Receiver Channel 3 Pin (Internal biased pin. Internally biased at PVDD/2)
PLL Ground pin
External Resistor Pin
12kΩ +/-1% resistor should be connected to PVSS externally.
PLL Power supply Pin, 4.5V∼5.5V
Receiver Channel 4 Pin (Internal biased pin. Internally biased at PVDD/2)
Test 2 Pin
This pin should be connected to PVSS.
Receiver Channel 5 Pin (Internal biased pin. Internally biased at PVDD/2)
Chip Address 0 Pin (ADC/DAC part)
Receiver Channel 6 Pin (Internal biased pin. Internally biased at PVDD/2)
Chip Address 1 Pin (ADC/DAC part)
Receiver Channel 7 Pin (Internal biased pin. Internally biased at PVDD/2)
Control Mode Select Pin.
“L”: 4-wire Serial, “H”: I2C Bus
Auxiliary Audio Data Input Pin (DIR/DIT part)
V-bit Input Pin for Transmitter Output
Master Clock Input Pin
Transmit Channel (Through Data) Output 0 Pin
Transmit Channel Output1 pin
When TX bit = “0”, Transmit Channel (Through Data) Output 1 Pin.
When TX bit = “1”, Transmit Channel (DAUX2 Data) Output Pin (default).
Interrupt 0 Pin
PVDD
RX pin
20k(typ)
20k(typ)
PVSS
VCOM
Internal biased pin Circuit
MS0287-J-03
2009/05
-8-
[AK4588]
■
Classification
Analog
Digital
Pin Name
RX7-0, LOUT4-1, ROUT4-1, LIN, RIN
INT1-0, BOUT, XTO, MCKO2-1, COUT, UOUT,
VOUT, SDTO2-1, CDTO, DZF2-1, TX1-0
CSN, DAUX2-1, SDTI4-1, XTL1-0, TEST3
TEST1-2
MS0287-J-03
Setting
These pins should be open.
These pins should be open.
These pins should be connected to DVSS.
These pins should be connected to PVSS.
2009/05
-9-
[AK4588]
(AVSS=DVSS=PVSS=0V; Note 1)
Parameter
Power Supplies
Analog
Digital
PLL
Output buffer
|AVSS-DVSS|
(Note 2)
|AVSS-PVSS|
(Note 2)
Input Current (any pins except for supplies)
Analog Input Voltage
(LIN, RIN pins)
Digital Input Voltage
Except LRCK1-2, BICK1-2, RX0-7, CAD0-1,
TEST1-2 pins
LRCK1-2, BICK1-2 pins
RX0-7, CAD0-1, TEST1-2
Ambient Temperature (power applied)
Storage Temperature
Symbol
AVDD
DVDD
PVDD
TVDD
ΔGND1
ΔGND2
IIN
min
-0.3
-0.3
-0.3
-0.3
-
max
6.0
6.0
6.0
6.0
0.3
0.3
±10
Units
V
V
V
V
V
V
mA
VINA
-0.3
AVDD+0.3
V
VIND1
-0.3
DVDD+0.3
V
VIND2
VIND3
Ta
Tstg
-0.3
-0.3
-40
-65
TVDD+0.3
PVDD+0.3
85
150
V
V
°C
°C
Note 1.
Note 2. AVSS, DVSS, PVSS
:
(AVSS=DVSS=PVSS=0V; Note 3)
Parameter
Analog
Power Supplies
Digital
(Note 4)
PLL
Output buffer
Symbol
AVDD
DVDD
PVDD
TVDD
Note 3.
Note 4. AVDD, DVDD, PVDD, TVDD
0.5V
min
4.5
4.5
4.5
2.7
typ
5.0
5.0
5.0
5.0
max
5.5
AVDD
AVDD
DVDD
Units
V
V
V
V
AVDD, DVDD, PVDD
:
MS0287-J-03
2009/05
- 10 -
[AK4588]
(Ta=25°C; AVDD=DVDD=PVDD=TVDD=5V; AVSS=DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz;
20Hz~40kHz at fs=192kHz, unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics
Resolution
24
Bits
S/(N+D)
(-0.5dBFS) fs=48kHz
84
92
dB
fs=96kHz
86
dB
DR
(-60dBFS) fs=48kHz, A-weighted
dB
94
102
fs=96kHz
dB
88
96
fs=96kHz, A-weighted
dB
93
102
S/N
(Note 5)
fs=48kHz, A-weighted
dB
94
102
fs=96kHz
dB
88
96
fs=96kHz, A-weighted
dB
93
102
Interchannel Isolation
90
110
dB
DC Accuracy
Interchannel Gain Mismatch
0.2
0.3
dB
Gain Drift
20
ppm/°C
AIN=0.62xVREFH
2.90
3.10
3.30
Vpp
Input Voltage
Input Resistance
fs=48kHz
15
25
kΩ
fs=96kHz
9
16
kΩ
Power Supply Rejection
(Note 6)
50
dB
DAC Analog Output Characteristics
Resolution
24
Bits
S/(N+D)
fs=48kHz
dB
80
90
fs=96kHz
dB
78
88
fs=192kHz
dB
88
DR
(-60dBFS)
fs=48kHz, A-weighted
95
106
dB
fs=96kHz
88
100
dB
fs=96kHz, A-weighted
94
106
dB
fs=192kHz
100
dB
fs=192kHz, A-weighted
106
dB
S/N
(Note 7)
fs=48kHz, A-weighted
95
106
dB
fs=96kHz
88
100
dB
fs=96kHz, A-weighted
94
106
dB
fs=192kHz
100
dB
fs=192kHz, A-weighted
106
dB
Interchannel Isolation
90
110
dB
DC Accuracy
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
20
ppm/°C
Output Voltage
AOUT=0.6xVREFH
2.75
3.0
3.25
Vpp
Load Resistance
5
kΩ
Power Supply Rejection
(Note 6)
50
dB
Power Supplies
Power Supply Current
Normal Operation (PDN = “H”)
(Note 8)
50
AVDD
fs=48kHz,fs=96kHz
70
mA
37
fs=192kHz
52
mA
12
PVDD
17
mA
44
DVDD+TVDD
fs=48kHz
(Note 9)
62
mA
fs=96kHz
57
80
mA
fs=192kHz
68
95
mA
Power-down mode (PDN = “L”)
(Note 10)
80
200
μA
MS0287-J-03
2009/05
- 11 -
[AK4588]
Note 5. CCIR-ARM
98dB(typ)(@fs=48kHz)
Note 6. VREFH +5.0V
AVDD, DVDD, PVDD, TVDD 1kHz, 50mVpp
Note 7. CCIR-ARM
102dB(typ)(@fs=48kHz)
Note 8. CL=20pF, X’tal=24.576MHz, CM1-0= “10”, CM1-0= “10”, OCKS1-0= “10”@48kHz, “00”@96kHz,
“11”@192kHz.
Note 9. TVDD=13mA(typ).
Note 10.
RX
DVSS
(Ta=25°C; AVDD=DVDD=PVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
Passband
PB
0
±0.1dB
(Note 11)
-0.2dB
-3.0dB
Stopband
SB
28.0
Passband Ripple
PR
Stopband Attenuation
SA
68
Group Delay
(Note 12)
GD
Group Delay Distortion
ΔGD
ADC Digital Filter (HPF):
Frequency Response (Note 11)
-3dB
FR
-0.1dB
DAC Digital Filter:
Passband
(Note 11)
-0.1dB
PB
0
-6.0dB
Stopband
SB
26.2
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay
(Note 12)
GD
DAC Digital Filter + Analog Filter:
FR
Frequency Response:
0 ∼ 20.0kHz
FR
40.0kHz (Note 13)
FR
80.0kHz (Note 13)
Note 11.
Note 12.
fs
-0.1dB
typ
max
Units
20.0
23.0
18.9
-
16
0
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
1.0
6.5
Hz
Hz
±0.04
21.8
-
19.2
kHz
kHz
kHz
dB
dB
1/fs
±0.2
±0.3
±1.0
dB
dB
dB
24.0
±0.02
21.8kHz 0.454 x fs(DAC)
24
ADC
DAC
20/24
DAC
Note 13. 40.0kHz@fs=96kHz, 80.0kHz@fs=192kHz.
MS0287-J-03
2009/05
- 12 -
[AK4588]
DC
(Ta=25°C; AVDD=DVDD=PVDD=4.5∼5.5V; TVDD=2.7∼5.5V)
Parameter
Symbol
VIH
High-Level Input Voltage (Except XTI pin)
VIH
(XTI pin)
VIL
Low-Level Input Voltage (Except XTI pin)
VIL
(XTI pin)
Input Voltage at AC Coupling (XTI pin) (Note 14)
VAC
High-Level Output Voltage
VOH
(Except TX0-1, DZF pins :
Iout=-400μA)
VOH
(TX0-1 pin :
Iout=-400μA)
VOH
(DZF pin :
Iout=-400μA)
VOL
Low-Level Output Voltage
(Iout=400μA)
Iin
Input Leakage Current
Note 14. XTI pin
S/PDIF
(Ta=25°C; AVDD=DVDD=PVDD=4.5~5.5V; TVDD=2.7~5.5V)
Parameter
Symbol
Input Resistance
Zin
Input Voltage (Internally biased at PVDD/2)
VTH
Input Hysteresis
VHY
Input Sample Frequency
fs
min
2.2
70%DVDD
40%DVDD
typ
-
max
0.8
30%DVDD
-
Units
V
V
V
V
Vpp
TVDD-0.4
DVDD-0.4
AVDD-0.4
-
-
0.4
±10
V
V
V
V
μA
typ
10
max
Units
kΩ
mVpp
mV
kHz
min
200
32
50
-
192
PVDD
RX pin
20k(typ)
20k(typ)
PVSS
VCOM
Internal biased pin Circuit
MS0287-J-03
2009/05
- 13 -
[AK4588]
(ADC/DAC )
(Ta=25°C; AVDD=DVDD=PVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Master Clock
256fsn, 128fsd:
fCLK
8.192
Pulse Width Low
tCLKL
27
Pulse Width High
tCLKH
27
384fsn, 192fsd:
fCLK
12.288
Pulse Width Low
tCLKL
20
Pulse Width High
tCLKH
20
512fsn, 256fsd:
fCLK
16.384
Pulse Width Low
tCLKL
15
Pulse Width High
tCLKH
15
LRCK1 Timing (Slave Mode)
Normal mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
TDM 256 mode
LRCK1 frequency
“H” time
“L” time
TDM 128 mode
LRCK1 frequency
“H” time
“L” time
LRCK1 Timing (Master Mode)
Normal mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
TDM 256 mode
LRCK1 frequency
“H” time
(Note 15)
TDM 128 mode
LRCK1 frequency
“H” time
(Note 15)
Power-down & Reset Timing
PDN Pulse Width
(Note 16)
PDN “↑” to SDTO1 valid
(Note 17)
Note 15. I2S
Note 16.
Note 17. PDN pin
typ
max
Units
12.288
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
18.432
24.576
fsn
fsd
fsq
Duty
32
64
120
45
48
96
192
55
kHz
kHz
kHz
%
fsd
tLRH
tLRL
32
1/256fs
1/256fs
48
kHz
ns
ns
fsd
tLRH
tLRL
64
1/128fs
1/128fs
96
kHz
ns
ns
fsn
fsd
fsq
Duty
32
64
120
48
96
192
kHz
kHz
kHz
%
fsn
tLRH
32
48
kHz
ns
fsd
tLRH
64
96
1/4fs
kHz
ns
tPD
tPDV
150
522
ns
1/fs
50
1/8fs
“L” time
PDN pin “L”
“H”
LRCK1
MS0287-J-03
2009/05
- 14 -
[AK4588]
Parameter
Audio Interface Timing (Slave Mode)
Normal mode
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑”
(Note 18)
BICK1 “↑” to LRCK1 Edge
(Note 18)
LRCK1 to SDTO1(MSB)
BICK1 “↓” to SDTO1
SDTI1-4,DAUX1 Hold Time
SDTI1-4,DAUX1 Setup Time
TDM 256 mode
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑”
(Note 18)
BICK1 “↑” to LRCK1 Edge
(Note 18)
BICK1 “↓” to SDTO1
SDTI1 Hold Time
SDTI1 Setup Time
TDM 128 mode
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑”
(Note 18)
BICK1 “↑” to LRCK1 Edge
(Note 18)
BICK1 “↓” to SDTO1
SDTI1-2 Hold Time
SDTI1-2 Setup Time
Audio Interface Timing (Master Mode)
Normal mode
BICK1 Frequency
BICK1 Duty
BICK1 “↓” to LRCK1 Edge
BICK1“↓” to SDTO1
SDTI1-4,DAUX1 Hold Time
SDTI1-4,DAUX1 setup Time
TDM 256 mode
BICK1 Frequency
BICK1 Duty
(Note 19)
BICK1 “↓” to LRCK1 Edge
BICK1 “↓” to SDTO1
SDTI1 Hold Time
SDTI1 Setup Time
TDM 128 mode
BICK1 Frequency
BICK1 Duty
(Note 20)
BICK1 “↓” to LRCK1 Edge
BICK1 “↓” to SDTO1
SDTI1-2 Hold Time
SDTI1-2 Setup Time
Note 18.
LRCK1
Note 19. MCLK pin 512fs
)
Note 20. MCLK pin 256fs
Symbol
min
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
32
32
20
20
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
typ
max
40
40
20
20
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
20
10
10
20
10
10
64fs
50
-20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
40
12
20
Hz
%
ns
ns
ns
ns
12
20
Hz
%
ns
ns
ns
ns
256fs
50
10
10
128fs
50
-12
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
20
20
-12
Units
10
10
BICK1
(384fs,256fs
(128fs
MS0287-J-03
Duty
Duty
)
2009/05
- 15 -
[AK4588]
■
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fsn, 1/fsd, 1/fsq
VIH
LRCK1
VIL
tBCK
VIH
BICK1
VIL
tBCKH
tBCKL
(Normal mode)
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK1
VIL
tLRH
tLRL
tBCK
VIH
BICK1
VIL
tBCKH
tBCKL
(TDM 256 mode, TDM 128 mode)
MS0287-J-03
2009/05
- 16 -
[AK4588]
VIH
LRCK1
VIL
tBLR
tLRB
VIH
BICK1
VIL
tLRS
tBSD
50%TVDD
SDTO1
tSDS
tSDH
VIH
SDTI
VIL
(Normal mode)
VIH
LRCK1
VIL
tBLR
tLRB
VIH
BICK1
VIL
tBSD
SDTO1
50%TVDD
tSDS
tSDH
VIH
SDTI
VIL
(TDM 256 mode, TDM 128 mode)
MS0287-J-03
2009/05
- 17 -
[AK4588]
LRCK1
50%TVDD
tMBLR
50%TVDD
BICK1
tBSD
50%TVDD
SDTO1
tDXS
tDXH
VIH
DAUX1
VIL
(Master Mode)
MS0287-J-03
2009/05
- 18 -
[AK4588]
(DIR/DIT )
(Ta=25°C; DVDD=AVDD=PVDD=4.5~5.5V, TVDD=2.7~5.5V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Crystal Resonator Frequency
fXTAL
11.2896
External Clock
Frequency
fECLK
11.2896
Duty
dECLK
40
MCKO1 Output
Frequency
fMCK1
4.096
Duty
dMCK1
40
MCKO2 Output
Frequency
fMCK2
2.048
Duty
dMCK2
40
PLL Clock Recover Frequency (RX0-7)
fpll
32
LRCK2 Frequency
fs
32
Duty Cycle
dLCK
45
Audio Interface Timing
Slave Mode
BICK2 Period
tBCK
80
BICK2 Pulse Width Low
tBCKL
30
Pulse Width High
tBCKH
30
tLRB
20
LRCK2 Edge to BICK2 “↑”
(Note 21)
tBLR
20
BICK2 “↑” to LRCK2 Edge
(Note 21)
tLRM
LRCK2 to SDTO2 (MSB)
tBSD
BICK2 “↓” to SDTO2
tDXH
20
DAUX2 Hold Time
tDXS
20
DAUX2 Setup Time
Master Mode
BICK2 Frequency
fBCK
BICK2 Duty
dBCK
tMBLR
-20
BICK2 “↓” to LRCK2
tBSD
BICK2 “↓” to SDTO2
tDXH
20
DAUX2 Hold Time
tDXS
20
DAUX2 Setup Time
Note 21.
LRCK2
BICK2
MS0287-J-03
typ
50
50
50
-
max
Units
24.576
24.576
60
24.576
60
24.576
60
192
192
55
MHz
MHz
%
MHz
%
MHz
%
kHz
kHz
%
30
30
64fs
50
20
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
2009/05
- 19 -
[AK4588]
■
1/fECLK
VIH
XTI
VIL
tECLKH
tECLKL
dECLK = tECLKH x fECLK x 100
= tECLKL x fECLK x 100
1/fMCK1
MCKO1
50%TVDD
tMCKH1
tMCKL1
dMCK1 = tMCKH1 x fMCK1 x 100
= tMCKL1 x fMCK1 x 100
1/fMCK2
MCKO2
50%TVDD
tMCKH2
tMCKL2
dMCK2 = tMCKH2 x fMCK2 x 100
= tMCKL2 x fMCK2 x 100
1/fs
VIH
LRCK2
VIL
tLRH
tLRL
dLCK = tLRH x fs x 100
= tLRL x fs x 100
VIH
LRCK2
VIL
tBCK
tBLR
tLRB
tBCKL
tBCKH
VIH
BICK2
VIL
tLRM
tBSD
50%TVDD
SDTO2
tDXS
tDXH
VIH
DAUX2
VIL
(Slave Mode)
MS0287-J-03
2009/05
- 20 -
[AK4588]
LRCK2
50%TVDD
tMBLR
50%TVDD
BICK2
tBSD
50%TVDD
SDTO2
tDXS
tDXH
VIH
DAUX2
VIL
(Master Mode)
tPD
PDN
VIL
MS0287-J-03
2009/05
- 21 -
[AK4588]
ADC/DAC , DIR/DIT
(Ta=25°C; AVDD=DVDD=PVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF)
Parameter
Symbol
Control Interface Timing (4-wire serial mode)
CCLK Period
tCCK
CCLK Pulse Width Low
tCCKL
Pulse Width High
tCCKH
CDTI Setup Time
tCDS
CDTI Hold Time
tCDH
CSN “H” Time
tCSW
tCSS
CSN “↓” to CCLK “↑”
tCSH
CCLK “↑” to CSN “↑”
tDCD
CDTO Delay
tCCZ
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I2C Bus mode)
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
Clock Low Time
tLOW
Clock High Time
tHIGH
Setup Time for Repeated Start Condition
tSU:STA
SDA Hold Time from SCL Falling
(Note 22)
tHD:DAT
SDA Setup Time from SCL Rising
tSU:DAT
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
Capacitive load on bus
Cb
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
Note 22.
300ns (SCL
Note 23. I2C Philips Semiconductors
min
typ
max
Units
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
1.0
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
200
80
80
50
50
150
50
50
4.7
4.0
4.7
4.0
4.7
0
0.25
4.0
0
)
MS0287-J-03
2009/05
- 22 -
[AK4588]
■
(ADC/DAC
DIR/DIT
)
VIH
CSN
VIL
tCSS
tCCK
tCCKL tCCKH
VIH
CCLK
VIL
tCDH
tCDS
C1
CDTI
C0
A4
R/W
VIH
VIL
Hi-Z
CDTO
WRITE/READ
ADC/DAC
(4-wire serial mode)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
VIH
D0
VIL
Hi-Z
CDTO
WRITE
(4-wire serial mode)
VIH
CSN
VIL
VIH
CCLK
VIL
CDTI
A1
VIH
A0
VIL
tDCD
CDTO
Hi-Z
D7
READ
ADC/DAC
D6
D5
50%TVDD
1 (4-wire serial mode)
MS0287-J-03
2009/05
- 23 -
[AK4588]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D3
D2
D1
READ
ADC/DAC
50%TVDD
D0
2 (4-wire serial mode)
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
I2C
ADC/DAC
tPD
VIH
PDN
VIL
tPDV
50%TVDD
SDTO
MS0287-J-03
2009/05
- 24 -
[AK4588]
(ADC/DAC
)
■
MCLK, LRCK1, BICK1
MCLK LRCK1
MCLK
DFS0, DFS1 bit
(Manual Setting Mode)
(Auto Setting Mode) 2
Manual
Setting Mode (ACKS bit = “0”: Default)
DFS1-0 bit
(Table 1)
MCLK
(Table 3, Table 4, Table
5) Auto Setting Mode (ACKS bit = “1”)
MCLK
(Table 6)
(Table 7)
DFS bit
MCLK
DFS1-0 bit(Table 1)
CKS1-0 bit(Table 2)
CKS1-0 bit DFS1-0 bit
BICK1 LRCK1
(PDN pin = “H”)
(RSTN1 bit = “0”)
(MCLK,BICK1,LRCK1)
(PDN pin = “L”)
(PDN pin = “↑”) MCLK, LRCK1
ON
(MCLK)
(PDN pin = “ ”)
DFS1
0
0
1
DFS0
0
1
0
Sampling Speed (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
120kHz~192kHz
Table 1.
CKS1
0
0
1
1
Table 2.
LRCK1
fs
32.0kHz
44.1kHz
48.0kHz
Table 3.
(
ON
MCLK
LRCK1
fs
88.2kHz
96.0kHz
Table 4.
:Double Speed Mode
(default)
(Manual Setting Mode)
CKS0
0
1
0
1
256fs
8.1920
11.2896
12.2880
Normal
256fs
384fs
512fs
256fs
Double
128fs
192fs
256fs
256fs
(Master Mode)
Quad
128fs
128fs
128fs
128fs
(default)
MCLK (MHz)
BICK1 (MHz)
384fs
512fs
64fs
12.2880
16.3840
2.0480
16.9344
22.5792
2.8224
18.4320
24.5760
3.0720
(Normal Speed Mode @Manual Setting Mode)
MCLK (MHz)
BICK1 (MHz)
192fs
256fs
64fs
16.9344
22.5792
5.6448
18.4320
24.5760
6.1440
(Double Speed Mode @Manual Setting Mode)
(DFS1=“0”, DFS0=“1”) 128fs 192fs
, ADC
128fs
11.2896
12.2880
MS0287-J-03
)
2009/05
- 25 -
[AK4588]
LRCK1
MCLK (MHz)
BICK1 (MHz)
fs
128fs
192fs
256fs
64fs
176.4kHz
22.5792
11.2896
192.0kHz
24.5760
12.2880
Table 5.
(Quad Speed Mode @Manual Setting Mode)
( :Quad Speed Mode (DFS1=“1”, DFS1=“0”)
ADC
MCLK
512fs
256fs
128fs
Table 6.
LRCK1
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
Table 7.
128fs
22.5792
24.5760
)
Sampling Speed
Normal
Double
Quad
(Auto Setting Mode)
MCLK (MHz)
256fs
512fs
16.3840
22.5792
24.5760
22.5792
24.5760
(Auto Setting Mode)
Sampling
Speed
Normal
Double
Quad
■
IIR
3
(32kHz, 44.1kHz, 48kHz)
Double Speed Mode Quad Speed Mode
DAC1(SDTI1), DAC2(SDTI2), DAC3(SDTI3), DAC4(SDTI4)
Mode
0
1
2
3
Sampling Speed
Normal Speed
Normal Speed
Normal Speed
Normal Speed
DEM1
0
0
1
1
(50/15μs
)
OFF
DEM0
0
1
0
1
DEM
44.1kHz
OFF
48kHz
32kHz
(default)
Table 8.
■
HPF
ADC DC
HPF
HPF
fc
fs=48kHz
1.0Hz
fs
MS0287-J-03
2009/05
- 26 -
[AK4588]
■
MASTER pin
“H”
(MASTER pin = “H” )
LRCK1 pin, BICK1 pin
(MASTER pin = “L” )
LRCK1 pin, BICK1 pin
LRCK1 pin, BICK1 pin
“L”
Table 9
PDN pin
PWADN bit, PWDAN bit
MASTER pin
L
H
L
“00”
H
L
“00”
H
Table 9. LRCK1 pin, BICK1 pin
L
H
H
LRCK1pin
Input
“L”
Input
“L”
Input
Output
BICK1 pin
Input
L”
Input
L”
Input
Output
■
TDM1-0 bit = “00”
8
MSB
2’s compliment
SDTI/DAUX1 BICK1
SDTO1
ADC
SDTO
mode2/3/6/7/10/11/14/15/18/19/22/23 16 ∼ 20bit
Mode
MASTER
TDM 1
TDM0
DIF1
DIF0
0
0
0
0
0
0
1
0
0
0
0
1
2
0
0
0
1
0
3
0
0
0
1
1
4
1
0
0
0
0
5
1
0
0
0
1
6
1
0
0
1
0
7
1
0
0
1
Table 10.
1
TDM1-0 bit
SDTI2-4
(Table 10) DIF1-0 bit
SDTO1 BICK1
Figure 1∼Figure 4 SDOS bit = “0”
SDOS bit = “1”
DAUX1
SDTI
LSB
“0”
SDTO1
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
SDTI1-4,
DAUX1
LRCK1
I/O
20bit, Right
H/L
I
justified
24bit, Right
H/L
I
justified
24bit, Left
H/L
I
justified
2
24bit, I S
L/H
I
20bit, Right
H/L
O
justified
24bit, Right
H/L
O
justified
24bit, Left
H/L
O
justified
2
24bit, I S
L/H
O
(Normal mode)
BICK1
I/O
≥ 48fs
I
≥ 48fs
I
≥ 48fs
I
≥ 48fs
I
64fs
O
64fs
O
64fs
O
64fs
O
(default)
“01”
TDM 256 mode
SDTI1 pin
DAC(8ch)
BICK1 256fs
LRCK1 “H”
“L”
1/256fs(min)
(Table 11) DIF1-0 bit
MSB
2’s
compliment
SDTO1 BICK1
SDTI1 BICK1
TDM
SDOS bit, LOOP1-0 bit “0”
TDM 128 mode
(96kHz)
TDM1-0 bit “10”
SDTI1 pin DAC(4ch; L1, R1, L2, R2) SDTI2 pin
DAC(4ch; L3, R3, L4, R4)
MS0287-J-03
8
2009/05
- 27 -
[AK4588]
Mode
MASTER
TDM 1
TDM0
DIF1
DIF0
8
0
0
1
0
0
9
0
0
1
0
1
10
0
0
1
1
0
11
0
0
1
1
1
12
1
0
1
0
0
13
1
0
1
0
1
14
1
0
1
1
0
15
1
0
1
1
Mode
MASTER
TDM 1
TDM0
DIF1
DIF0
16
0
1
1
0
0
17
0
1
1
0
1
18
0
1
1
1
0
19
0
1
1
1
1
20
1
1
1
0
0
21
1
1
1
0
1
22
1
1
1
1
0
23
1
1
1
1
1
Table 11.
1
Table 12.
SDTO1
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
SDTO1
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I2S
MS0287-J-03
SDTI1
LRCK1
I/O
20bit, Right
↑
justified
24bit, Right
↑
justified
24bit, Left
↑
justified
2
24bit, I S
↓
20bit, Right
↑
justified
24bit, Right
↑
justified
24bit, Left
↑
justified
2
24bit, I S
↓
TDM 256 mode
SDTI1,
SDTI2
I
256fs
I
I
256fs
I
I
256fs
I
I
256fs
I
O
256fs
O
O
256fs
O
O
256fs
O
O
256fs
O
LRCK1
I/O
20bit, Right
↑
justified
24bit, Right
↑
justified
24bit, Left
↑
justified
2
24bit, I S
↓
20bit, Right
↑
justified
24bit, Right
↑
justified
24bit, Left
↑
justified
2
24bit, I S
↓
TDM 128 mode
BICK1
I/O
BICK1
I/O
I
128fs
I
I
128fs
I
I
128fs
I
I
128fs
I
O
128fs
O
O
128fs
O
O
128fs
O
O
128fs
O
2009/05
- 28 -
[AK4588]
LRCK1
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK1(64fs)
SDTO1(o)
23 22
SDTI(i)
12 11 10
0
19 18
8
Don’t Care
23 22
7
1
12
11 10
Don’t Care
0
0
19 18
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 1. Mode 0/4
LRCK1
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
24
25
31
0
1
BICK1(64fs)
SDTO1(o)
23 22
SDTI(i)
16 15 14
Don’t Care
0
23 22
23:MSB, 0:LSB
23 22
8
7
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
8
7
1
0
Rch Data
Figure 2. Mode 1/5
LRCK1
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
28
29
30
31
0
1
BICK1(64fs)
SDTO1(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
23
Don’t Care
23
Rch Data
Figure 3.Mode 2/6
LRCK1
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK1(64fs)
SDTO1(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
Lch Data
23 22
2
1
0
23 22
2
1
0
Don’t Care
Rch Data
Figure 4. Mode 3/7
MS0287-J-03
2009/05
- 29 -
[AK4588]
256 B ICK
LRCK1
(m ode 8)
LRCK1
(m ode 12)
BICK1(256fs)
SDTO1(o)
23 22
0
23 22
Lch
32 B ICK
SDTI1(i)
0
23 22
Rch
19 18
32 B ICK
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
19 18
0
L1
R1
L2
R2
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
19
Figure 5. Mode 8/12
256 B ICK
LRCK1
(m ode 9)
LRCK1
(m ode 13)
BICK1(256fs)
SDTO1(o)
23 22
0
23 22
Lch
32 B ICK
SDTI1(i)
0
23 22
Rch
23 22
32 B ICK
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23
Figure 6. Mode 9/13
256 B ICK
LRCK1
(m ode 10)
LRCK1
(m ode 14)
BICK1(256fs)
SDTO1(o)
SDTI1(i)
23 22
0
23 22
0
Lch
Rch
32 B ICK
32 B ICK
23 22
0
23 22
0
L1
R1
32 B ICK
32 B ICK
23 22
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
L2
R2
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
Figure 7. Mode 10/14
256 B ICK
LRCK1
(m ode 11)
LRCK1
(m ode 15)
BICK1(256fs)
SDTO1(o)
23
0
Lch
23
0
23
Rch
32 B ICK
SDTI1(i)
23
0
32 B ICK
23
0
23
0
23
0
23
0
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23
Figure 8. Mode 11/15
MS0287-J-03
2009/05
- 30 -
[AK4588]
128 B ICK
LRCK1
(m ode 16)
LRCK1
(m ode 20)
BICK1(128fs)
SDTO1(o)
23 22
0
SDTI2(i)
23 22
Rch
32 B ICK
SDTI1(i)
0
23 22
Lch
32 BICK
19 18
0
19 18
0
19 18
0
L1
R1
L2
32 B ICK
32 B ICK
32 B ICK
19 18
0
19 18
0
19 18
0
19 18
R2
32 B ICK
19 18
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
0
19
0
19
Figure 9. Mode 16/20
128 B ICK
LRCK1
(m ode 17)
LRCK1
(m ode 21)
BICK1(128fs)
23 22
SDTI1(i)
SDTI2(i)
0
0
23 22
Lch
Rch
32 B ICK
32 BICK
23 22
0
23 22
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
0
23 22
0
23 22
0
23 22
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
0
19
0
19
Figure 10. Mode 17/21
128 B ICK
LRCK1
(m ode 18)
LRCK1
(m ode 22)
BICK1(128fs)
SDTO1(o)
SDTI1(i)
SDTI2(i)
23 22
0
0
23 22
Lch
Rch
32 B ICK
32 BICK
23 22
0
23 22
0
23 22
23 22
0
23 22
L1
R1
L2
R2
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
0
23 22
0
23 22
0
23 22
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
0
23 22
0
23 22
Figure 11. Mode 18/22
MS0287-J-03
2009/05
- 31 -
[AK4588]
128 B ICK
LRCK1
(m ode 19)
LRCK1
(m ode 23)
BICK1(128fs)
SDTO1(o)
23 22
0
SDTI1(i)
SDTI2(i)
23
Rch
32 B ICK
23 22
0
23 22
Lch
32 BICK
0
23 22
0
0
23 22
23 22
L1
R1
L2
R2
32 B ICK
32 B ICK
32 B ICK
32 B ICK
23 22
0
23 22
0
0
23 22
23 22
L3
R3
L4
R4
32 B ICK
32 B ICK
32 B ICK
32 B ICK
0
23
0
23
Figure 12. Mode 19/23
MS0287-J-03
2009/05
- 32 -
[AK4588]
■
AK4588
Lch
Rch
“H”
@fs=48kHz)
“L”
OVFE bit “1”
(-0.3dBFS
) OVF pin
OVF
ADC
(GD = 19.1/fs = 398μs
(PDN pin = “L” → “H”) 522/fs (=11.8ms @fs=48kHz)
OVF pin
■
AK4588 2
DZF1 pin Group1
DZF2 pin OVF pin
bit DZF
Table 14
Group
DZF2 pin Group2
mode 0
DZF1 pin
Group1(Group2)
Group1(Group2)
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DZFM
2 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
8192
8ch AND
“0”
“0”
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
L1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF1
DZF1
R1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF2
DZF1
DZF1
DZFM3-0 bit
(Table 13)
OVFE bit “1”
DZF2 pin
(“L”)
OVFE
DZF1(DZF2) pin
“L”
AOUT
L2
R2
L3
R3
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF2
DZF1
DZF1
DZF2
DZF2
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
disable (DZF1=DZF2 = “L”)
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
DZF1
“H”
L4
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
R4
DZF1
DZF2
DZF2
DZF2
DZF2
DZF2
DZF2
(default)
DZF1
DZF2
DZF2
DZF2
disable (DZF1=DZF2 = “L”)
Table 13.
OVFE bit
0
1
DZF1 pin
Selectable (Table 13)
Selectable (Table 13)
DZF2/OVF pin
Selectable (Table 13)
OVF output
Table 14. DZF1-2 pin
MS0287-J-03
2009/05
- 33 -
[AK4588]
■
AK4588
ATT7-0 bit
(128
(Table 15)
ATT7-0
00H
01H
02H
:
7DH
7EH
7FH
FEH
FFH
, 0.5dB
Attenuation Level
0dB
-0.5dB
-1.0dB
:
-62.5dB
-63dB
MUTE (-∞)
:
MUTE (-∞)
MUTE (-∞)
)
(default)
Table 15.
ATT7-0
ATS1-0 bit
Mode
0
1
2
3
ATS1
0
0
1
1
(Table 16) Mode0
ATS0
0
1
0
1
Table 16.
Mode0
ATT
(37.3ms@fs=48kHz)
bit
“0”
00H
1792
PDN pin
“L”
RSTN1 bit
Mode1
ATT speed
1792/fs
896/fs
256/fs
256/fs
(default)
ATT7-0
00H(0dB)
ATT7-0 00H
7FH(MUTE)
ATT7-0
1792/fs
RSTN1
“1”
MS0287-J-03
2009/05
- 34 -
[AK4588]
■
×ATT
-∞
ATT
SMUTE bit
-∞ (“0”)
(Table 16)
×ATT
“1”
ATT
SMUTE bit
-∞
ATT
ATT
“0”
ATT
SMUTE bit
(1)
ATT Level
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
(4)
8192/fs
DZF1,2
:
(1)ATT
×ATT
(2)
(3)
(Table 16)
ATT
Mode 0
00H 7FH
(GD)
ATT
“00H”
1792/fs
-∞
ATT
(4)
8192
“0”
“0”
DZF pin
“H”
DZF pin
“L”
Figure 13.
■
ON
PDN pin
LRCK1
“L”
“↑”
MCLK
LRCK1
MS0287-J-03
2009/05
- 35 -
[AK4588]
■
AK4588
ADC
DAC
(PDN)
“L”
PDN pin = “L”
SDTO1,DZF1-2 pin
VCOM
ADC
, SDTO1 522 x LRCK1
ADC
DAC
PWADN bit
“L”
DAC
VCOM
Figure 14
PWDAN bit
SDTO1 pin “L”
DZF1-2 pin “H”
PWDAN bit = “0”
DAC1-4 PD1-4 bit
PWADN bit = “0”
VCOM
PD1-4 bit = “0”
Power
PDN
(1)
522/fs
ADC Internal
State
Init Cycle
516/fs
DAC Internal
State
Normal Operation
Power-down
Normal Operation
Power-down
(2)
Init Cycle
GD (3)
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data (4)
DAC In
(Digital)
“0”data
(5)
“0”data
“0”data
GD
(3)
(6)
DAC Out
(Analog)
GD
(6)
(7)
Clock In
Don’t care
Don’t care
MCLK,LRCK,SCLK
10∼11/fs (10)
(8)
DZF1/DZF2
External
Mute
(1) ADC
(2) DAC
(3)
(4)
(5)
(6) PDN
(7)
(8)
(9)
(6)
(10) PDN “↑”
(9)
Mute ON
Mute ON
(GD)
ADC
“0”
ADC
PDN
(PDN pin = “L”)
(PDN pin = “L”)
10∼11/fs
DZF1-2 pin
512/fs
(MCLK, BICK1, LRCK1)
“L”
DZF pin = “L”
Figure 14.
MS0287-J-03
2009/05
- 36 -
[AK4588]
■
RSTN1 bit = “0”
VCOM
ADC DAC
DZF1-2 pin
“H”
SDTO1 pin
“L”
Figure 15 RSTN1 bit
RSTN bit
4~5/fs (9)
1~2/fs (9)
Internal
RSTN bit
516/fs (1)
ADC Internal
State
Normal Operation
Digital Block Power-down
DAC Internal
State
Normal Operation
Digital Block Power-down
Normal Operation
Init Cycle
Normal Operation
GD (2)
GD
ADC In
(Analog)
(3)
ADC Out
(Digital)
(4)
“0”data
DAC In
(Digital)
“0”data
(2)
GD
GD
(6)
DAC Out
(Analog)
(6)
(5)
(7)
Clock In
Don’t care
MCLK,LRCK,SCLK
4∼5/fs (8)
DZF1/DZF2
(1) ADC
(2)
(3)
(4)
(GD)
ADC
“0”
ADC
(5) RSTN1 bit = “0”
(6) RSTN1 bit “0”
(7)
VCOM
4∼5/fs
(RSTN1 bit = “0”)
(8) DZF1-2 pin
RSTN1 bit
(9) RSTN1 bit
“0”
RSTN1 bit
“1”
1∼2/fs
(MCLK, BICK1, LRCK1)
(MCLK, BICK1, LRCK1)
“0”
“H”
LSI
RSTN1 bit
RSTN
RSTN1 bit = “1”
“1”
6~7/fs
“L”
4~5/fs
Figure 15.
MS0287-J-03
2009/05
- 37 -
[AK4588]
■ DAC
AK4588
DAC
“1”
PD1-4 bit
DZF
PD1-4 bit
DAC
DAC
VCOM
DZF
DZF1-2 pin
PWDAN bit = “0”
Figure 16
RSTN1 bit = “0”
PD1-4 bit
PD1-4 bit
PD1-4 bit
Power Down Channel
DAC Digital
Internal State
DAC Analog
Internal State
Normal Operation
Normal Operation
Normal Operation
Power-down
DAC In
(Digital)
Power-down
Normal
Operation
Normal
Operation
“0”data
(1)
GD
GD
(3)
DAC Out
(Analog)
(2)
(3)
(3)
(2)
(3)
8192/fs
DZF Detect
Internal State
(4)
(4)
Normal Operation Channel
DAC In
(Digital)
“0”data
GD
GD
DAC Out
(Analog)
8192/fs
DZF Detect
Internal State
Clock In
MCLK,LRCK2,
BICK2
(5)
(6)
DZF1/DZF2
(1)
(2) PD1-4 bit
(3) PD1-4 bit
(4)
(GD)
DAC
DAC
PD bit
DZF
(5)
(6)
VCOM
DAC
DZF1-2 pin
DAC
DAC
DZF
DZF1-2 pin
“H”
DZF1-2 pin
“H”
Figure 16. DAC
MS0287-J-03
2009/05
- 38 -
[AK4588]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
:
Register Name
Control 1
Control 2
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
LOUT3 Volume Control
ROUT3 Volume Control
De-emphasis
ATT speed
& Power Down Control
Zero detect
LOUT4 Volume Control
ROUT4 Volume Control
D7
0
CKS1
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
DEMD1
D6
0
DFS1
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
DEMD0
D5
TDM1
LOOP1
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
DEMA1
D4
TDM0
LOOP0
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
DEMA0
D3
DIF1
SDOS
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
DEMB1
D2
DIF0
DFS0
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
DEMB0
D1
0
ACKS
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
DEMC1
D0
SMUTE
CKS0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
DEMC0
0
PD4
ATS1
ATS0
PD3
PD2
PD1
RSTN1
OVFE
ATT7
ATT7
DZFM3
ATT6
ATT6
DZFM2
ATT5
ATT5
DZFM1
ATT4
ATT4
DZFM0
ATT3
ATT3
PWVRN
ATT2
ATT2
PWADN
ATT1
ATT1
PWDAN
ATT0
ATT0
0DH∼1FH
PDN pin
“L”
RSTN1 bit “0”
DZF1-2 pin
“H”
■
Addr
00H
Register Name
Control 1
Default
SMUTE:
0:
1:
D7
0
0
D6
0
0
D5
TDM1
0
D4
TDM0
0
D3
DIF1
1
D2
DIF0
0
D1
0
0
D0
SMUTE
0
DAC
DIF1-0:
(Table 10)
: “10”, mode 2
TDM1-0: TDM
(Table 11, Table 12)
Mode
0
1
2
TDM1 TDM0
0
0
0
1
1
1
SDTI
1-4
1
1-2
MS0287-J-03
Sampling Speed
Normal, Double, Quad Speed
Normal Speed
Double Speed
2009/05
- 39 -
[AK4588]
Addr
01H
Register Name
Control 2
Default
D7
CKS1
0
D6
DFS1
0
D5
LOOP1
0
D4
LOOP0
0
D3
SDOS
0
D2
DFS0
0
D1
ACKS
0
D0
CKS0
0
ACKS:
0:
, Manual Setting Mode
1:
, Auto Setting Mode
ACKS bit = “1”
MCLK
ACKS bit = “0”
MCLK
DFS1-0:
ACKS bit = “1”
CKS1-0:
SDOS: SDTO1
0: ADC
1: DAUX1
TDM0 bit = “1”
PWADN bit = “0”
ADC
DFS
DFS1-0 bit
(Table 1)
DFS
(MASTER Mode, Table 2)
SDOS bit
“0”
PWDAN bit = “0”
PWADN bit = “0”
SDOS
SDTO1 pin
“L”
LOOP1-0:
00:
(
)
01: LIN → LOUT1, LOUT2, LOUT3, LOUT4
RIN → ROUT1, ROUT2, ROUT3, ROUT4
ADC
(SDOS bit = “1”
DAUX1
) DAC
DAC
SDTI1-4
SDTO1
mode0
mode2 mode1
mode3
10: SDTI1(L) → SDTI2(L), SDTI3(L), SDTI4(L)
SDTI1I → SDTI2I, SDTI3I, SDTI4I
DAC
SDTI2-4
11: N/A
TDM0 bit = “1”
LOOP1-0 bit
“00”
PWADN bit =”0”
PWDAN bit =”0”
LOOP1-0 bit
(
)
MS0287-J-03
2009/05
- 40 -
[AK4588]
Addr
02H
03H
04H
05H
06H
07H
0BH
0CH
Register Name
LOUT1 Volume Control
ROUT1 Volume Control
LOUT2 Volume Control
ROUT2 Volume Control
LOUT3 Volume Control
ROUT3 Volume Control
LOUT4 Volume Control
ROUT4 Volume Control
Default
ATT7-0:
Addr
08H
Register Name
De-emphasis
Default
D7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
0
D6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
0
D5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
0
D4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
0
D3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
0
D2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
0
D1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
0
D0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
0
(Table 15)
D7
DEMD1
0
D6
DEMD0
1
D5
DEMA1
0
D4
DEMA0
1
D3
DEMB1
0
DEMA1-0: DAC1
: “01”, OFF
(Table 8)
DEMB1-0: DAC2
: “01”, OFF
(Table 8)
DEMC1-0: DAC3
: “01”, OFF
(Table 8)
DEMD1-0: DAC4
: “01”, OFF
(Table 8)
MS0287-J-03
D2
DEMB0
1
D1
DEMC1
0
D0
DEMC0
1
2009/05
- 41 -
[AK4588]
Addr
09H
Register Name
ATT speed
& Power Down Control
Default
RSTN1:
0:
1:
D7
D6
D5
D4
D3
D2
D1
D0
0
PD4
ATS1
ATS0
PD3
PD2
PD1
RSTN1
0
0
0
0
0
0
0
1
DZF1-2 pin
“H”
ATS1-0:
(Table 16)
: “00”, mode 0
PD1-0: Power-down control (0: Power-up, 1: Power-down)
PD1: Power down control of DAC1
PD2: Power down control of DAC2
PD3: Power down control of DAC3
PD4: Power down control of DAC4
Addr
0AH
Register Name
Zero detect
Default
D7
OVFE
0
D6
DZFM3
0
D5
DZFM2
1
D4
DZFM1
1
D3
DZFM0
1
D2
PWVRN
1
D1
PWADN
1
D0
PWDAN
1
PWDAN: DAC1-4
0:
1:
PWADN: ADC
0:
1:
PWVRN:
0:
1:
DZFM3-0:
(Table 13)
: “0111”,
OVFE:
0:
1:
, pin#33 DZF2 pin
, pin#33 OVF pin
MS0287-J-03
2009/05
- 42 -
[AK4588]
(DIR/DIT
)
■ Non-PCM/DTS-CD
AK4588 Non-PCM
Dolby “AC-3 Data Stream in IEC60958 Interface”
32
Mode Non-PCM
AUTO bit
“1”
96
sync code 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F
4096
sync code
sync code
AUTO bit
“0”
sync code
2
(Pc, Pd)
DTS-CD
DTSCD bit “1”
4096
sync code
sync code
DTSCD bit
“0”
■ 192kHz
PLL 32kHz
192kHz
20ms
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
■
AK4588
2
PLL
X’tal
MCKO2)
X’tal
No.
0
1
2
3
fs
OCKS1
0
0
1
1
OCKS0
0
1
0
1
(Table 17)
96kHz
512fs 192kHz
OCKS1-0 bit
MCKO1
256fs
256fs
512fs
128fs
MCKO2
256fs
128fs
256fs
64fs
X’tal
256fs
256fs
512fs
128fs
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
(MCKO1,
256fs,512fs
(default)
Table 17.
■
RX
Mode 2
X’tal
PLL
DAUX2
Unlock
X’tal
RX
Mode
0
1
CM1
0
0
2
1
3
1
Note: X’tal
CM0
0
1
CM1-0 bit
Mode 3
Mode 2, 3
UNLOCK
PLL
X’tal
Clock source SDTO
ON
ON(Note)
PLL
RX
OFF
ON
X’tal
DAUX2
0
ON
ON
PLL
RX
0
1
ON
ON
X’tal
DAUX2
1
ON
ON
X’tal
DAUX2
ON:
(Power-up), OFF:
(Power-Down)
(XTL1-0 pin = “H,H”) OFF
PLL X’tal
(default)
Table 18.
MS0287-J-03
2009/05
- 43 -
[AK4588]
■
AK4588 XTI pin
1) X’tal
XTI
C
25kΩ(typ)
C
XTO
AK4588
Figure 17. X’tal
Note:
(Typ.10-40pF)
2)
C
XTI
XTI
External
Clock
External
Clock
25kΩ(typ)
25kΩ(typ)
XTO
XTO
AK4588
AK4588
Figure 18 (5V). (a).
(Input :CMOS Level)
- Note: DVDD
Figure 19 (3.3V). (b).
(Input : 40%DVDD)
3) XTI/XTO
XTI
25kΩ(typ)
XTO
AK4588
Figure 20. OFF
MS0287-J-03
2009/05
- 44 -
[AK4588]
■
AK4588
2
XTL1-0 pin
X’tal
X’tal
FS0, FS1, FS2, FS3 bit
XTL1-0 pin = ”H,H”
FS0, FS1, FS2, FS3, PEM bit
XTL1
0
0
1
1
XTL0
0
1
0
1
X’tal Frequency
11.2896MHz
12.288MHz
24.576MHz
(default)
Table 19.
XTL1,0= “1,1”
XTL1,0= “1,1”
Register output
fs
Clock comparison
(Note 24)
FS3
0
0
0
0
1
1
1
1
Note 24.
FS2
0
0
0
0
0
0
1
1
Note 25.
FS1
0
0
1
1
0
1
0
1
±3%
FS0
0
1
0
1
0
0
0
0
44.1kHz
Reserved
48kHz
32kHz
88.2kHz
96kHz
176.4kHz
192kHz
44.1kHz
Reserved
48kHz
32kHz
88.2kHz
96kHz
176.4kHz
192kHz
Consumer
mode
(Note 25)
Byte3
Bit3/2/1/0
0000
0001
0010
0011
(1000)
(1010)
(1100)
(1110)
Table
32kHz∼192kHz
Professional mode
Byte0
Bit7/6
01
10
11
00
00
00
00
Byte4
Bit6/5/4/3
0000
(Others)
0000
0000
1010
0010
1011
0011
FS3-0 bit = “0001”
Byte3 Bit3-0 FS3-0 bit
Table 20.
PEM bit
“1”
(CS12 bit = “0”
2
)
1
CS12 bit =
PEM
Pre-emphasis
0
1
OFF
ON
Byte 0
Bits 3-5
≠ 0X100
0X100
Table 21.
PEM
Pre-emphasis
0
1
OFF
ON
Byte 0
Bits 2-4
≠110
110
Table 22.
MS0287-J-03
2009/05
- 45 -
[AK4588]
■
IIR
4
(32kHz, 44.1kHz, 48kHz, 96kHz)
DEAU bit = “1”
FS3-0 bit
(50/15μs
)
DEAU bit = “0”
OFF
PEM bit =
DEM0/1, DFS bit
“0”
PEM
1
1
1
1
1
0
FS3
0
0
0
1
FS2
0
0
0
0
FS1
0
1
1
1
x
x
x
DFS
0
0
0
0
1
1
1
1
x
DEM1
0
0
1
1
0
0
1
1
x
FS0
0
0
1
0
Mode
44.1kHz
48kHz
32kHz
96kHz
OFF
x
OFF
(x: Don’t care)
(DEAU bit = “1”: Default)
(Others)
Table 23.
PEM
1
1
1
1
1
1
1
1
0
DEM0
0
1
0
1
0
1
0
1
x
Mode
44.1kHz
OFF
(default)
48kHz
32kHz
OFF
OFF
96kHz
OFF
OFF
(x: Don’t care)
(DEAU bit = “0”)
Table 24.
■
AK4588
PDN pin
PWN bit
PDN pin
RSTN2 bit
“L”
PDN pin:
“L”
RSTN2 bit (
“0”
PWN bit (
00H D0):
PWN bit RSTN2 bit
“0”
SDTO2
“L”
PWN bit RSTN2 bit
00H D1):
“0”
PLL
X’tal
MS0287-J-03
2009/05
- 46 -
[AK4588]
■
8
(RX0-7)
IPS2-0 bit
200mVpp
“1”
BCU bit =
Block start, C,U bit
IPS2
0
0
0
0
1
1
1
1
IPS1
0
0
1
1
0
0
1
1
IPS0
0
1
0
1
0
1
0
1
INPUT Data
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
(default)
Table 25.
B
1/4fs
COUT (or U,V)
SDTO2
C(R191)
C(L0)
R190
C(R0)
L191
C(L1)
R191
L0
C(L31)
L30
C(R31) C(L32)
R30
L31
LRCK2
(except I2S)
LRCK2
(I2S)
Figure 21. B, C, U, V
MS0287-J-03
2009/05
- 47 -
[AK4588]
■
TX0/1 pin
RX
DAUX2
DIT bit
TX1
bit
OPS00, 01, 02
TX0/1 pin
DAUX2
(Figure 22) C bit
5Byte
bit20-23(Audio channel)
CT20
“1000”
, Sub frame 2
“0100”
“0000”
U bit UDIT bit
“0”
UDIT bit = “1”
U bit
PLL
OPS10, 11, 12 bit
8
V bit VIN pin
bit0= “0”(consumer mode)
Sub frame 1
CT20 bit
“0”
UDIT bit= “0”
U bit DIR-DIT
“1”
2
DIT
OPS02
0
0
0
0
1
1
1
1
OPS01
0
0
1
1
0
0
1
1
OPS00
0
1
0
1
0
1
0
1
Output Data
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
Table 26.
DIT
0
0
0
0
0
0
0
0
1
OPS12
0
0
0
0
1
1
1
1
x
IEC60958
TX0
(default)
(TX0)
OPS11
0
0
1
1
0
0
1
1
x
OPS10
0
1
0
1
0
1
0
1
x
Output Data
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
DAUX2
Table 27.
(default)
(TX1)
LRCK2
(except I2S)
LRCK2
(I2S)
DAUX2
L0
R0
L1
R1
VIN
R191
L0
R0
L1
Figure 22. DAUX2, VIN
MS0287-J-03
2009/05
- 48 -
[AK4588]
■
0.1uF
RX
75Ω
Coax
75Ω
AK4588
Figure 23.
Note: Coaxial
50mV
(Coaxial
)
RX
Optical Receiver
Optical
Fiber
470
RX
O/E
AK4588
Figure 24.
Coaxial
RX
“H”
AK4588
(
)
RX
“L”
TX
0.5V+/-20%
330
Figure 25
T1
1:1
2%
TX
100
75Ω cable
2%
DVSS
T1
Figure 25. TX
MS0287-J-03
2009/05
- 49 -
[AK4588]
■ Q-subcode
U bit
CD Q-subcode
1. Subcode sync word (S0,S1)
2. Start bit
“1”
3. Q-W
7 bit
start bit
4. Start bit
8-16 bit
Q-subcode
S0
S1
S2
S3
:
S97
S0
S1
S2
S3
:
1
0
0
1
1
:
1
0
0
1
1
:
16
QINT
Q3 Q4
CTRL
Q5
Q6
Q7 Q8
ADRS
QINT bit
“0”
2
3
4
5
6
7
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Q2
R2
S2
T2
U2
V2 W2
Q3
R3
S3
T3
U3
V3 W3
:
:
:
:
:
:
:
Q97 R97 S97 T97 U97 V97 W97
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Q2
R2
S2
T2
U2
V2 W2
Q3
R3
S3
T3
U3
V3 W3
:
:
:
:
:
:
:
(*) number of “0” : min=0; max=8.
Q
Q2
“0” bit
Q9
Figure 26. U-
*
0…
0…
0…
0…
:
0…
0…
0…
0…
0…
:
(CD)
Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25
TRACK NUMBER
INDEX
Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Q48 Q49
MINUTE
SECOND
FRAME
Q50 Q51 Q52 Q53 Q54 Q55 Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Q72 Q73
ZERO
ABSOLUTE MINUTE
ABSOLUTE SECOND
Q74 Q75 Q76 Q77 Q78 Q79 Q80 Q81 Q82 Q83 Q84 Q85 Q86 Q87 Q88 Q89 Q90 Q91 Q92 Q93 Q94 Q95 Q96 Q97
ABSOLUTE FRAME
CRC
G(x)=x16+x12+x5+1
Figure 27.
Addr
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
D7
Q9
Q17
D6
Q8
Q16
Q
D5
D4
Q81
Q80
Figure 28. Q-subcode register
MS0287-J-03
D3
D2
D1
Q3
Q11
D0
Q2
Q10
Q75
Q74
2009/05
- 50 -
[AK4588]
■
INT1-0 pin
“H”
1. UNLOCK : PLL
2. PAR
8
“1”
:
“1”
“1”
3. AUTO
5. AUDION
: Non-Linear PCM
4096
: DTS-CD
DTS-CD
sync
: AUDIO
6. PEM
:
7. QINT
:Q-subcode bit Sync
Sync
4. DTSCD
8. CINT
:
U-
“1”
Sync
“1”
PLL OFF
1024/fs (EFH0/1 bit
INT pin
1
(Clock Operation Mode 1) INT0/1 pin
“L”
)
“H”
INT1 pin
INT0 pin
PAR, QINT, CINT bit
8
OR
INT pin
“L”
“1”
INT pin
(
06H
1024/fs (EFH0/1 bit
“1”
)
)
06H
“H”
INT0 pin
PAR, QINT, CINT bit
INT0 UNLOCK, PAR
bit
UNLOCK
1
0
0
0
0
0
0
0
INT1 AUTO, DTSCD, AUDION bit
PAR
x
1
0
0
0
0
0
0
AUTO
x
x
1
x
x
x
x
x
Event
DTSCD AUDION
x
x
x
x
x
x
1
x
x
1
x
x
x
x
x
x
PEM
x
x
x
x
x
1
x
x
QINT
x
x
x
x
x
x
1
x
CINT
x
x
x
x
x
x
x
1
SDTO2 pin
“L”
Previous Data
Output
Output
Output
Output
Output
Output
Pin
VOUT pin
“L”
Output
Output
Output
Output
Output
Output
Output
TX1-0 pin
Output
Output
Output
Output
Output
Output
Output
Output
Table 28.
MS0287-J-03
2009/05
- 51 -
[AK4588]
Error
(UNLOCK, PAR,..)
(Error)
INT0 pin
Hold Time (max: 4096/fs)
INT1 pin
Hold Time = 0
Register
(PAR,CINT,QINT)
Reset
Hold ”1”
Register
(others)
Command
MCKO,BICK2,LRCK2
(UNLOCK)
MCKO,BICK2,LRCK2
(except UNLOCK)
READ 06H
Free Run
(fs: around 20kHz)
SDTO2 (UNLOCK)
SDTO2
(PAR error)
Previous Data
SDTO2
(others)
VOUT pin
(UNLOCK)
VOUT pin
(except UNLOCK)
Normal Operation
Figure 29. INT1-0 pin
MS0287-J-03
2009/05
- 52 -
[AK4588]
PDN pin ="L" to "H"
Initialize
Read 06H
INT0/1 pin ="H"
No
Yes
Release
Muting
Mute DA C output
Read 06H
(Each Error Handling)
Read 06H
(Res ets registers)
No
INT0/1 pin ="H"
Yes
Figure 30.
1
MS0287-J-03
2009/05
- 53 -
[AK4588]
PDN pin ="L" to "H"
Initialize
Read 06H
No
INT1 pin ="H"
Yes
Read 06H
and
Detect QSUB= “1”
(Read Q-buffer)
QCRC = “0”
No
New data
is invalid
Yes
INT1 pin ="L"
No
Yes
New data
is valid
Figure 31.
2 (Q/CINT)
MS0287-J-03
2009/05
- 54 -
[AK4588]
■
8
(Table 29)
MSB
SDTO2 BICK2
DAUX2
BICK2 64fs
Mode 6-7 Mode 4-5
20
(Mode0-2)
4
Aux
Figure 32
Mode 3-7
(
)
BICK2
Parity Error
SDTO2
(PDN pin = “H”)
“L”
“0”
SDTO2
DAUX2 pin
, Left justified
SDTO2
I2S
LRCK2 BICK2
Clock Mode 2
Clock Mode 3
Mode 5, 7
24
Mode 5, 7
Mode4-5
Mode0-5
128fs
BICK2 fs=48kHz
LSB
(PDN pin = “L”)
LRCK2
Hi-Z
PLL
unlock
2’s compliment
DAUX2
Clock Mode 1 PLL
DAUX2
Mode 6-7
MCKO1/2
sub-frame of IEC60958
0
3 4
preamble
7 8
11 12
27 28 29 30 31
Aux.
V U C P
LSB
MSB
MSB
LSB
23
0
AK4588 Audio Data (MSB First)
Figure 32.
Mode
DIF2
DIF1
DIF0
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAUX2
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
SDTO2
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
LRCK2
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
H/L
I
L/H
I
BICK2
64fs
64fs
64fs
64fs
64fs
64fs
64-128fs
64-128fs
I/O
O
O
O
O
O
O
I
I
(default)
Table 29.
MS0287-J-03
2009/05
- 55 -
[AK4588]
LRCK2
0
1
2
15
16
17
31
0
1
2
15
16
17
31
0
1
0
1
0
1
BICK2
(0:64fs)
15
14
1
0
15
14
1
0
SDTO2
15:MSB, 0:LSB
Rch Data
Lch Data
Figure 33. Mode 0
LRCK2
0
1
2
9
10
12
11
31
0
1
2
9
10
11
12
31
BICK2
(0:64fs)
23
22
21
20
1
0
23
22
21
20
1
0
SDTO2
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 34. Mode 3
LRCK2
0
1
2
21
22
24
23
31
0
1
2
21
22
23
24
31
BICK2
(64fs)
23
22 21
2
1
0
23 22
3
2
1
0
23 22
SDTO2
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 35. Mode 4/6
Mode4 : LRCK2, BICK2 : Output
Mode6 : LRCK2, BICK2 : Input
LRCK2
0
1
2
22
24
23
25
31
0
1
2
21
22
23
24
25
31
0
1
BICK2
(64fs)
SDTO2
23
22 21
2
1
23 22
0
3
2
1
0
23
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 36. Mode 5/7
Mode5: LRCK2, BICK2 : Output
Mode7: LRCK2, BICK2 : Input
MS0287-J-03
2009/05
- 56 -
[AK4588]
■
Addr
Register Name
CLK & Power Down
00H
Control
01H Format & De-em Control
02H Input/ Output Control 0
03H Input/ Output Control 1
04H INT0 MASK
05H INT1 MASK
06H Receiver status 0
07H Receiver status 1
08H RX Channel Status Byte 0
09H RX Channel Status Byte 1
0AH RX Channel Status Byte 2
0BH RX Channel Status Byte 3
0CH RX Channel Status Byte 4
D7
D6
D5
D4
CS12
BCU
CM1
CM0
0
TX1E
EFH1
MQIT0
MQIT1
QINT
FS3
CR7
CR15
CR23
CR31
CR39
D3
D2
OCKS1 OCKS0
DIF2
DIF1
DIF0
DEAU DEM1
OPS12 OPS11 OPS10 TX0E OPS02
EFH0
UDIT
0
DIT
IPS2
MAUT0 MCIT0 MULK0 MDTS0 MPE0
MAUT1 MCIT1 MULK1 MDTS1 MPE1
AUTO CINT UNLCK DTSCD PEM
FS2
FS1
FS0
0
V
CR6
CR5
CR4
CR3
CR2
CR14
CR13
CR12
CR11
CR10
CR22
CR21
CR20
CR19
CR18
CR30
CR29
CR28
CR27
CR26
CR38
CR37
CR36
CR35
CR34
D1
D0
PWN
RSTN2
DEM0
OPS01
IPS1
MAUD0
MAUD1
AUDION
QCRC
CR1
CR9
CR17
CR25
CR33
DFS
OPS00
IPS0
MPAR0
MPAR1
PAR
CCRC
CR0
CR8
CR16
CR24
CR32
0DH
TX Channel Status Byte 0
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
0EH
TX Channel Status Byte 1
CT15
CT14
CT13
CT12
CT11
CT10
CT9
CT8
0FH
TX Channel Status Byte 2
CT23
CT22
CT21
CT20
CT19
CT18
CT17
CT16
10H
TX Channel Status Byte 3
CT31
CT30
CT29
CT28
CT27
CT26
CT25
CT24
11H
TX Channel Status Byte 4
CT39
CT39
CT39
CT39
CT39
CT39
CT39
CT32
Burst Preamble Pc Byte 0
PC7
Burst Preamble Pc Byte 1
PC15
Burst Preamble Pd Byte 0
PD7
Burst Preamble Pd Byte 1
PD15
Q-subcode
Address
/
16H
Q9
Control
17H Q-subcode Track
Q17
18H Q-subcode Index
Q25
19H Q-subcode Minute
Q33
1AH Q-subcode Second
Q41
1BH Q-subcode Frame
Q49
1CH Q-subcode Zero
Q57
1DH Q-subcode ABS Minute
Q65
1EH Q-subcode ABS Second
Q73
1FH Q-subcode ABS Frame
Q81
: PDN pin
“L”
RSTN2 bit “0”
PWN bit “0”
“0”
“0”
PC6
PC14
PD6
PD14
PC5
PC13
PD5
PD13
PC4
PC12
PD4
PD12
PC3
PC11
PD3
PD11
PC2
PC10
PD2
PD10
PC1
PC9
PD1
PD9
PC0
PC8
PD0
PD8
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
Q80
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
12H
13H
14H
15H
MS0287-J-03
2009/05
- 57 -
[AK4588]
■
Reset & Initialize
Addr
Register Name
00H CLK & Power Down Control
R/W
Default
D7
CS12
R/W
0
D6
BCU
R/W
1
D5
CM1
R/W
0
D4
CM0
R/W
0
D3
D2
OCKS1 OCKS0
R/W
R/W
0
0
D1
PWN
R/W
1
D0
RSTN2
R/W
1
RSTN2:
0:
1:
&
PWN:
0:
1:
OCKS1-0:
CM1-0:
BCU:
, C, U
BCU bit = 1
3
(BOUT, COUT, UOUT)
frame 31
frame 0
“H”
CS12:
0: Channel 1
1: Channel 2
C bit, AUDION, PEM, FS3-0, Pc, Pd
Format & De-emphasis Control
Addr
Register Name
01H Format & De-em Control
R/W
Default
D7
0
RD
0
D6
DIF2
R/W
1
DFS: 96kHz
DEM1-0: 32, 44.1, 48kHz
DEAU:
0: Disable
1: Enable
DIF2-0:
D5
DIF1
R/W
1
D4
DIF0
R/W
0
D3
DEAU
R/W
1
D2
DEM1
R/W
0
D1
DEM0
R/W
1
D0
DFS
R/W
0
(Table 24)
(Table 29)
MS0287-J-03
2009/05
- 58 -
[AK4588]
Input/Output Control
Addr
Register Name
02H Input/ Output Control 0
R/W
Default
OPS02-00:
OPS12-10:
TX0E: TX0
0:
1:
TX1E: TX1
0:
1:
D7
TX1E
R/W
1
D6
D5
D4
OPS12 OPS11 OPS10
R/W
R/W
R/W
0
0
0
D3
TX0E
R/W
1
D2
D1
D0
OPS02 OPS01 OPS00
R/W
R/W
R/W
0
0
0
(TX0)
(TX1)
TX0 pin
“L”
TX1 pin
“L”
Addr
Register Name
03H Input/ Output Control 1
R/W
Default
D7
EFH1
R/W
0
D6
EFH0
R/W
1
D5
UDIT
R/W
0
IPS2-0:
DIT: TX1 pin
0:
(RX
)
1:
(DAUX2
)
UDIT: DIT U bit
0: U bit “0”
1:
U bit
EFH1-0: INT0 pin
00: 512 LRCK2
01: 1024 LRCK2
10: 2048 LRCK2
11: 4096 LRCK2
MS0287-J-03
D4
0
RD
0
D3
DIT
R/W
1
(U bit
D2
IPS2
R/W
0
D1
IPS1
R/W
0
D0
IPS0
R/W
0
)
2009/05
- 59 -
[AK4588]
Mask Control for INT0
Addr
Register Name
04H INT0 MASK
R/W
Default
MPR0:
MAN0:
MPE0:
MDTS0:
MUL0:
MCI0:
MAT0:
MQI0:
D7
MQI0
R/W
1
D6
MAT0
R/W
1
D5
MCI0
R/W
1
D4
MUL0
R/W
0
D3
MDTS0
R/W
1
D2
MPE0
R/W
1
D1
MAN0
R/W
1
D0
MPR0
R/W
0
D7
MQI1
R/W
1
D6
MAT1
R/W
0
D5
MCI1
R/W
1
D4
MUL1
R/W
1
D3
MDTS1
R/W
0
D2
MPE1
R/W
1
D1
MAN1
R/W
0
D0
MPR1
R/W
1
PAR bit
AUDN bit
PEM bit
DTSCD bit
UNLOCK bit
CINT bit
AUTO bit
QINT bit
0:
1:
Mask Control for INT1
Addr
Register Name
05H INT1 MASK
R/W
Default
MPR1:
MAN1:
MPE1:
MDTS1:
MUL1:
MCI1:
MAT1:
MQI1:
PAR bit
AUDN bit
PEM bit
DTSCD bit
UNLOCK bit
CINT bit
AUTO bit
QINT bit
0:
1:
MS0287-J-03
2009/05
- 60 -
[AK4588]
Receiver Status 0
Addr
Register Name
06H Receiver status 0
R/W
Default
D7
QINT
RD
0
D6
AUTO
RD
0
D5
CINT
RD
0
D4
D3
UNLCK DTSCD
RD
RD
0
0
D2
PEM
RD
0
D1
AUDION
RD
0
D0
PAR
RD
0
PAR:
0:No Error
1:Error
PAR bit
“1”
AUDION: Audio bit
0: Audio
1: Non Audio
PEM:
0: OFF
1: ON
DTSCD: DTS-CD
0:
1:
UNLCK: PLL
0:
1:
CINT:
0:
1:
AUTO: Non-PCM
0:
1:
QINT: Q
0:
1:
QINT, CINT, PAR bit 06H
READ
Receiver Status 1
Addr
Register Name
07H Receiver status 1
R/W
Default
D7
FS3
RD
0
CCRC:
D6
FS2
RD
0
D5
FS1
RD
0
D4
FS0
RD
1
D3
0
RD
0
D2
V
RD
0
D1
QCRC
RD
0
D0
CCRC
RD
0
CRC
0:
1:
QCRC: Q
CRC
0:
1:
V:
0: Valid
1: Invalid
FS3-0:
(Table 20)
MS0287-J-03
2009/05
- 61 -
[AK4588]
Receiver Channel Status
Addr
08H
09H
0AH
0BH
0CH
Register Name
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
R/W
Default
D7
CR7
CR15
CR23
CR31
CR39
D6
CR6
CR14
CR22
CR30
CR38
D5
CR5
CR13
CR21
CR29
CR37
D4
CR4
CR12
CR20
CR28
CR36
D3
CR3
CR11
CR19
CR27
CR35
D2
CR2
CR10
CR18
CR26
CR34
D1
CR1
CR9
CR17
CR25
CR33
D0
CR0
CR8
CR16
CR24
CR32
D2
CT2
CT10
CT18
CT26
CT34
D1
CT1
CT9
CT17
CT25
CT335
D0
CT0
CT8
CT16
CT24
CT32
D2
PC2
PC10
PD2
PD10
D1
PC1
PC9
PD1
PD9
D0
PC0
PC8
PD0
PD8
RD
Not initialized
CR39-0:
Byte 4-0
Transmitter Channel Status
Addr
0DH
0EH
0FH
10H
11H
Register Name
TX Channel Status Byte 0
TX Channel Status Byte 1
TX Channel Status Byte 2
TX Channel Status Byte 3
TX Channel Status Byte 3
R/W
Default
D7
CT7
CT15
CT23
CT31
CT39
D6
CT6
CT14
CT22
CT30
CT38
CT39-0:
D5
CT5
CT13
CT21
CT29
CT37
D4
D3
CT4
CT3
CT12
CT11
CT20
CT19
CT28
CT27
CT36
CT35
R/W
0
Byte 4-0
Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams
Addr
12H
13H
14H
15H
Register Name
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
R/W
Default
D7
PC7
PC15
PD7
PD15
D6
PC6
PC14
PD6
PD14
PC15-0:
PD15-0:
Pc Byte 0, 1
Pd Byte 0, 1
D5
PC5
PC13
PD5
PD13
D4
PC4
PC12
PD4
PD12
D3
PC3
PC11
PD3
PD11
RD
Not initialized
MS0287-J-03
2009/05
- 62 -
[AK4588]
Q-subcode Buffer
Addr
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
R/W
Default
D7
Q9
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
Q81
D6
Q8
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
Q80
D5
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
D4
Q6
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
D3
Q5
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
D2
Q4
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
D1
Q3
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
D0
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
RD
Not initialized
MS0287-J-03
2009/05
- 63 -
[AK4588]
■ Non-PCM
sub-frame of IEC60958
0
3 4
preamble
7 8
11 12
Aux.
27 28 29 30 31
LSB
MSB V U C P
16 bits of bitstream
0
Pa Pb Pc Pd
15
Burst_payload
stuffing
repetition time of the burst
Figure 37. IEC60958
Preamble word
Pa
Pb
Pc
Pd
Length of field
16 bits
16 bits
16 bits
16 bits
Contents
sync word 1
sync word 2
Burst info
Length code
Value
0xF872
0x4E1F
see Table 31
Numbers of bits
Table 30.
MS0287-J-03
2009/05
- 64 -
[AK4588]
Bits of Pc Value
Contents
0-4
data type
NULL data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 without extension
MPEG-2 data with extension
MPEG-2 AAC ADTS
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
reserved, shall be set to “0”
error-flag indicating a valid burst_payload
error-flag indicating that the burst_payload may contain
errors
data type dependent info
bit stream number, shall be set to “0”
5, 6
7
8-12
13-15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
0
0
1
0
Repetition time of burst
in IEC60958 frames
Table 31.
≤4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
Pc
MS0287-J-03
2009/05
- 65 -
[AK4588]
■ Non-PCM
1) Non-PCM
4096
PDN pin
Bit stream
Pa Pb Pc1 Pd1
Pa Pb Pc2 Pd2
Repetition time
Pa Pb Pc3 Pd3
>4096 frames
AUTO bit
Pc Register
“0”
Pd Register
“0”
Pc1
Pc2
Pd1
Pd2
Figure 38.
2) Non-PCM
Pc3
Pd3
1
(MULK0= “0”
)
INT0 hold time
INT0 pin
<20mS (Lock time)
Bit stream
Pa Pb Pc1 Pd1
Stop
Pa Pb Pcn Pdn
2~3 Syncs (B,M or W)
<Repetition time
AUTO bit
Pc Register
Pd Register
Pc0
Pc1
Pd0
Pcn
Pd1
Figure 39.
Pdn
2
MS0287-J-03
2009/05
- 66 -
[AK4588]
(ADC/DAC
, DIR/DIT
)
■
AK4588
ADC/DAC
(AK4628
(1) 4
) DI/DIT
(AK4114
)
(I2C pin = “L”)
4
I/F (CSN, CCLK, CDTI, CDTO)
I/F
Chip address (2bits, AK4588
ADC/DAC
CAD1-0 pin
DIR/DIT
”00”
), Read/Write (1bit), Register address (MSB first, 5bits)
Control Data (MSB first, 8bits)
CCLK “↓”
“↑”
CSN “↑”
CSN “↑”
Hi-Z
CCLK
5MHz (max)
PDN pin= “L”
ADC/DAC
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13
14 15
CCLK
CDTI
WRITE
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
CDTI
READ
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
C1,C0:
R/W:
A4-A0:
D7-D0:
D7 D6 D5 D4 D3 D2 D1 D0
Chip Address: (ADC/DAC
CAD1,CAD0 pin
CAD1=CAD0 = “L”
(DIR/DIT
“00”
)
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
Figure 40. 4
Hi-Z
)
I/F
MS0287-J-03
2009/05
- 67 -
[AK4588]
(2) I2C
AK4588
(I2C pin = “H”)
I 2C
(max:100kHz)
(max:400kHz)
ADC/DAC
(2)-1
·
1
·
READ
WRITE
·
(2)-1-1.
SDA
SCL
“L”
“L”
“H”
“H”
“H”
SCL
“L”
SDA
SDA
SCL
·
·
SCL
SDA
CHANGE
OF DATA
ALLOWED
DATA LINE
STABLE :
DATA VALID
Figure 41.
(2)-1-2.
SCL
“H”
SDA
“H”
·
“L”
SCL
·
·
“H”
·
SDA
“L”
“H”
SCL
SDA
START CONDITION
Figure 42.
STOP CONDITION
·
·
MS0287-J-03
2009/05
- 68 -
[AK4588]
(2)-1-3.
IC
1
SDA
IC
SDA
(HIGH
)
“L”
AK4588
WRITE
AK4588
·
READ
SDA
·
SDA
AK4588
·
AK4588
(
)ADC, DAC
READ
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 43.
(2)-1-4.
1
1
·
·
5
pin
“1”
“00100”
2
7
IC
CAD1, CAD0
IC
) R/W bit
R/W bit=
·
1
R/W bit= “0”
READ
0
(ADC, DAC
(DIR
0
1
8
WRITE
0
0
CAD1, CAD0
“00”
)
(
CAD1
CAD1=CAD0= “0”
Figure 44.
CAD0
R/W
)
1
MS0287-J-03
2009/05
- 69 -
[AK4588]
(2)-2. WRITE
R/W bit
“0”
AK4588 WRITE
2
Don’t care
3
*
*
WRITE
2
MSB first
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 45.
2
3
8
D7
D6
D5
D4
Figure 46.
D3
MSB first
D2
D1
D0
3
AK4588
1
1FH
S
T
A
R
T
SDA
·
Register
Address(n)
Slave
Address
·
00H
S
T
Data(n+x) O
P
Data(n+1)
Data(n)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 47. WRITE
MS0287-J-03
2009/05
- 70 -
[AK4588]
(2)-3. READ
R/W bit
“1”
·
AK4588
READ
1FH
00H
ADC/DAC
AK4588
·
·
·
READ
(2)-3-1.
AK4588
·
·
·
AK4588 READ
·
·
·
(READ
WRITE
n+1
(R/W bit = “1”)
·
)
n
·
·
·
1
1
READ
·
S
T
A
R
T
SDA
Slave
Address
Data(n)
Data(n+1)
S
Data(n+x) T
O
P
Data(n+2)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 48. CURRENT ADDRESS READ
(2)-3-2.
·
·
·
(R/W bit = “1”)
·
·
WRITE
WRITE
·
READ
(R/W bit = “0”)
AK4588
·
READ
·
(R/W bit = “1”)
AK4588
·
1
·
READ
S
T
A
R
T
SDA
Slave
Address
S
T
A
R
T
Word
Address(n)
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 49. RANDOM READ
MS0287-J-03
2009/05
- 71 -
[AK4588]
Figure 50
(AKD4588)
:I2C
5
Micro
Controller
(S/PDIF
sources)
S/PDIF sources
S/PDIF out
+
C
NC 62
RX3 63
PVSS 64
R 65
RX4 67
PVDD 66
RX5 69
TEST2 68
RX6 71
CAD0 70
CAD1 72
I2C 74
2
BOUT
3
TVDD
NC 58
4
DVDD
RX0 57
5
DVSS
RX1 59
XTO
7
XTI
VREFH 54
8
TEST3
9
MCKO2
6
X’tal
VCOM 53
+
0.1u 10u
Analog 5V
0.1u 2.2u
+
RIN 52
AK4588
11 COUT
LIN 51
NC 50
12 UOUT
ROUT1 49
13 VOUT
NC 48
LOUT1 47
14 SDTO2
15 BICK2
NC 46
16 LRCK2
ROUT2 45
17 SDTO1
NC 44
LOUT2 43
18 BICK1
NC 42
Audio DSP
(MPEG/AC3)
MUTE
(Shield)
MUTE
(Shield)
MUTE
(Shield)
MUTE
(Shield)
MUTE
40 NC
ROUT3 41
(Shield)
(Shield)
39 LOUT3
38 NC
(Shield)
MUTE
36 NC
37 ROUT4
MUTE
Micro
Controller
(Shield)
34 DZF1
35 LOUT4
MUTE
33 DZF2
32 MASTER
31 PDN
29 XTL1
30 XTL0
27 SDTI2
28 SDTI1
26 SDTI3
24 DAUX1
23 CSN
22 SDA
20 CDTO
25 SDTI4
19 LRCK1
21 SCL
(Shield)
AVSS 56
AVDD 55
10 MCKO1
(Micro
Controller)
RX7 73
VIN 76
DAUX2 75
MCLK 77
INT1
C
Audio DSP
(MPEG/AC3)
TEST1 60
1
(S/PDIF
Source)
Digital 5V
TX1 79
12k
0.1u
+
TX0 78
INT0 80
10u
RX2 61
0.1u
Audio DSP
(MPEG/AC3)
3.3V to 5V
Digital
(Shield)
10u
+
Micro Controller
Digital Ground
Analog Ground
Figure 50
MS0287-J-03
2009/05
- 72 -
[AK4588]
1.
AVDD, DVDD, PVDD, TVDD
AVDD, DVDD, PVDD, TVDD
AVSS, DVSS, PVSS
PC
2.
VREFH pin
AVSS
0.1μF
VCOM
VREFH pin
AVDD/2
AVDD pin
2.2μF
0.1μF
AVSS
VCOM pin
VREFH,VCOM
3.
ADC
VREFH Vpp (typ)
AK4588
2’s compliment(2
AK4588
VCOM
AVSS
)
AVDD
DC
0.62 x
HPF
64fs
64fs
AK4588
(RC
64fs
)
4.
DAC
2’s compliment(2
800000H(@24bit)
(
VCOM
)
7FFFFFH(@24bit)
000000H(@24bit)
)
0.6xVREFH Vpp(typ)
VCOM
(SCF)
(CTF)
LSI
DC
VCOM
mV
MS0287-J-03
2009/05
- 73 -
[AK4588]
z
80-pin LQFP
( Unit : mm )
14.0±0.2
12.0±0.2
41
61
40
80
21
12.0±0.2
1
20
0.08
0.125+0.10
-0.05
0.50±0.1
0.10
M
+0.15
0.10 -0.10
0.50
1.25TYP
1.85MAX
0° ~ 10°
0.20±0.1
1.40±0.2
14.0±0.2
60
■
(
)
MS0287-J-03
2009/05
- 74 -
[AK4588]
AK4588VQ
XXXXXXX
1) Pin #1 indication
2) Asahi Kasei Logo
3) Marking Code: AK4588VQ
4) Date Code: XXXXXXX(7 digits)
Date (YY/MM/DD)
04/01/22
04/03/18
08/05/22
Revision
00
01
02
09/05/25
03
Reason
First Edition
Page
Contents
12
ADC Digital Filter, Group Delay: 19.1/fs → 16/fs
Ambient Temperature
“-10 ∼ +70°C” → “-40 ∼ +85°C”
■
TEST3 pin
(DVSS )
9
MS0287-J-03
2009/05
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[AK4588]
•
•
•
•
•
•
MS0287-J-03
2009/05
- 76 -