[AK4951] = Preliminary = AK4951 24bit Stereo CODEC with MIC/HP/SPK-AMP 1. General Description The AK4951 is a low power 24-bit stereo CODEC with a microphone, headphone and speaker amplifiers. The AK4951 supports sampling frequency from 8kHz to 48kHz. It is suitable for a wide range of application from speech signal processing for narrowband, wideband and super wideband to sound signal processing for audio band. The input circuits include a microphone amplifier, an automatic wind noise reduction filter of the proprietary algorithms and a high performance digital ALC (automatic level control) circuit, therefore the AK4951 can record with high-quality sound regardless of whether indoors or outdoors. In addition, the output circuits include a cap-less headphone amplifier with a negative voltage generated by charge pump circuit and a speaker amplifier with 1W output power. It is suitable for various products as well as portable applications with recording/playback function. The AK4951 are available in a small 32-pin QFN (4mm x 4mm, 0.4mm pitch: AK4951EN) and a 32-pin BGA (3.5mm x 3.5mm, 0.5mm pitch: AK4951EG) packages saving mounting area on the board. Application: IP Camera Digital Camera IC Recorder Tablet Wireless Headphone Headset 2. Features 1. Recording Functions Analog Input (AK4951EN) 3 Stereo Single-ended inputs with Selectors (AK4951EG) 2 Stereo and 1 Monaural Single-ended inputs with Selectors Microphone Amplifier: +30dB ~ 0dB, 3dB Step Microphone Power Supply: 2.0V or 2.4V, Noise Level= 108dBV Digital ALC (Automatic Level Control) - Setting Range: +36dB 52.5dB, 0.375dB Step & Mute ADC Performance: S/(N+D): 83dB, DR, S/N: 88dB (MIC-Amp=+18dB) S/(N+D): 85dB, DR, S/N: 96dB (MIC-Amp=0dB) Microphone Sensitivity Correction Automatic Wind Noise Reduction Filter 5-Band Notch Filter: Include Dynamic Gain Control Stereo Separation Emphasis Circuit Digital Microphone Interface 014004561-E-00-PB 2014/08 -1- [AK4951] 2. Playback Functions Digital ALC (Automatic Level Control) - Setting Range: +36dB ~ 52.5dB, 0.375dB Step & Mute Sidetone Mixer & Volume Control (0dB ~ 18dB, 6dB Step) Digital Volume Control - +12dB ~ 89.5dB, 0.5dB Step & Mute Capacitor-less Stereo Headphone Amplifier - HP-Amplifier Performance: S/(N+D): 75dB@20mW, S/N: 97dB - Output Power: 20mW@16 - Pop Noise Free at Power-ON/OFF Mono Speaker Amplifier (with Stereo Line Output Switch) - Speaker Amplifier Porformance: S/(N+D): 75dB@250mW, S/N: 99dB - BTL Output - Output Power: (AK4951EN) 400mW@8 (SVDD=3.3V), 1W@8 (SVDD=5V) (AK4951EG) 400mW@8 (AVDD=3.3V) Analog Mixing: BEEP Input 3. Power Management 4. Master Clock: (1) PLL Mode Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin), 32fs or 64fs (BICK pin) (2) External Clock Mode Frequencies: 256fs, 384fs, 512fs or 1024fs (MCKI pin) 5. Sampling Frequencies PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz PLL Slave Mode (BICK pin): 8kHz ~ 48kHz EXT Master/Slave Mode: 8kHz ~ 48kHz (256fs, 384fs, 512fs), 8kHz 24kHz (1024fs) 6. Master/Slave Mode 7. Audio Interface Format: MSB First, 2’s complement ADC: 16/24bit MSB justified, 16/24bit I2S DAC: 16/24bit MSB justified, 16bit LSB justified, 24bit LSB justified, 16/24bit I2S 8. P I/F: (AK4951EN) I2C Bus (Ver 1.0, 400kHz Fast-Mode) (AK4951EG) 3-wire Serial, I2C Bus (Ver 1.0, 400kHz Fast-Mode) 9. Operating Temperature: Ta = 40 85C 10. Power Supply (AK4951EN) Analog Power Supply (AVDD): 2.8 ~ 3.5V Speaker Power Supply (SVDD): 1.8 ~ 5.5V Digital & Headphone Power Supply (DVDD): 1.6 ~ 1.98V Digital I/O Power Supply (TVDD): 1.6 or (DVDD – 0.2) ~ 3.5V (AK4951EG) Analog & Speaker Power Supply (AVDD): 2.8 ~ 3.5V Digital & Headphone Power Supply (DVDD): 1.6 ~ 1.98V Digital I/O Power Supply (TVDD): 1.6 or (DVDD – 0.2) ~ 3.5V 11. Package: (AK4951EN) 32-pin QFN (4 x 4 mm, 0.4mm pitch) (AK4951EG) 32-pin BGA (3.5 x 3.5 mm, 0.5mm pitch) 014004561-E-00-PB 2014/08 -2- [AK4951] 3. Table of Contents 1. 2. 3. 4. 5. General Description.................................................................................................................................... 1 Features ...................................................................................................................................................... 1 Table of Contents ....................................................................................................................................... 3 Block Diagram ........................................................................................................................................... 4 Pin Configurations and Functions .............................................................................................................. 6 ■ Ordering Guide ......................................................................................................................................... 6 ■ Pin Layout ................................................................................................................................................. 6 ■ Comparison Table of the AK4954A.......................................................................................................... 8 ■ PIN/FUNCTION ..................................................................................................................................... 10 ■ Handling of Unused Pin .......................................................................................................................... 12 6. Absolute Maximum Ratings..................................................................................................................... 12 7. Recommended Operating Conditions ...................................................................................................... 13 8. Electrical Characteristics .......................................................................................................................... 14 ■ Analog Characteristics ............................................................................................................................ 14 ■ Power Consumption on Each Operation Mode....................................................................................... 17 ■ Filter Characteristics ............................................................................................................................... 18 ■ DC Characteristics .................................................................................................................................. 19 ■ Switching Characteristics........................................................................................................................ 20 ■ Timing Diagram ...................................................................................................................................... 23 9. Package .................................................................................................................................................... 28 ■ AK4951EN Outline Dimensions ............................................................................................................ 28 ■ AK4951EN Material & Lead finish ........................................................................................................ 28 ■ AK4951EN Marking............................................................................................................................... 28 ■ AK4951EG Outline Dimensions ............................................................................................................ 29 ■ AK4951EG Material & Lead finish ........................................................................................................ 29 ■ AK4951EG Marking............................................................................................................................... 29 IMPORTANT NOTICE .................................................................................................................................. 30 014004561-E-00-PB 2014/08 -3- [AK4951] 4. Block Diagram [AK4951EN] VCOM VSS1 DVDD TVDD VSS2 PMMP MPWR2 MIC Power Supply MPWR1 AVDD Analog Block LDO 2.3V PDN Digital Core, Headphone-Amp MIC-Power, Charge-pump PMADL Internal MIC AVDD REGFIL SDA Control Register SCL LIN1 PMADL or PMADR RIN1 External MIC MIC-Amp +30~0dB LIN2 ADC HPF PMADR PMPFIL RIN2 Line Input MIC Sensitivity Correction Auto HPF LIN3 BICK HPF2 LPF SVDD Stereo Emphasis VSS3 Audio I/F SDTO 4-band EQ PMBP ALC RIN3/ BEEP LRCK SDTI 1 Band EQ BEEP PFVOL PMSL PMDAC SPP/LOUT Mono Speaker SPN/ROUT DAC DVOL Mono/ SMUTE Stereo PMPLL PMHPL HPL PMOSC PLL MCKI Oscillator Cap-less Headphone PMHPR HPR PMHPL or PMHPR Charge Pump AVDD VEE CN CP Figure 1. Block Diagram (AK4951EN) 014004561-E-00-PB 2014/08 -4- [AK4951] [AK4951EG] VCOM VSS1 DVDD TVDD VSS2 PMMP MPWR2 MIC Power Supply MPWR1 AVDD Analog Block LDO 2.3V PDN Digital Core, Headphone-Amp MIC-Power, Charge-pump, Speaker-Amp PMADL Internal MIC AVDD REGFIL CSN/SDA Control Register LIN1 RIN1 MIC-Amp +30~0dB LIN2 ADC CDTIO/CAD0 I2C PMADL or PMADR External MIC CCLK/SCL HPF PMADR PMPFIL RIN2 MIC Sensitivity Correction Auto HPF BICK HPF2 LPF Stereo Emphasis VSS3 Audio I/F SDTO 4-band EQ PMBP ALC RIN3/BEEP LRCK SDTI 1 Band EQ BEEP PFVOL PMSL PMDAC SPP/LOUT Mono Speaker SPN/ROUT DAC DVOL Mono/ SMUTE Stereo PMPLL PMHPL HPL PMOSC PLL MCKI Oscillator Cap-less Headphone PMHPR HPR PMHPL or PMHPR Charge Pump AVDD VEE CN CP Figure 2. Block Diagram (AK4951EG) 014004561-E-00-PB 2014/08 -5- [AK4951] 5. Pin Configurations and Functions ■ Ordering Guide AK4951EN AKD4951EN 40 +85C 32-pin QFN (0.4mm pitch) Evaluation board for AK4951EN AK4951EG AKD4951EG 40 ~ +85°C 32-pin BGA (0.5mm pitch) Evaluation board for AK4951EG ■ Pin Layout VEE HPR HPL DVDD SPP/LOUT SPN/ROUT SVDD VSS3 24 23 22 21 20 19 18 17 [AK4951EN] LRCK VSS1 29 Top View 12 SDTO VCOM 30 11 SDTI REGFIL 31 10 SDA RIN3/BEEP 32 9 SCL 8 13 PDN AK4951EN 7 28 LIN1/DMDAT AVDD 6 BICK RIN1/DMCLK 14 5 27 MPWR1 CN 4 MCKI MPWR2 15 3 26 LIN2 CP 2 TVDD RIN2 16 1 25 LIN3 VSS2 Figure 3. Pin Layout (AK4951EN) 014004561-E-00-PB 2014/08 -6- [AK4951] [AK4951EG] 6 5 4 AK4951EG 3 Top View 2 1 A B C D E F 6 LIN2 RIN2 REGFIL VSS1 AVDD VSS2 5 MPWR2 MPWR1 RIN3 /BEEP VCOM CN VEE 4 RIN1 LIN1 /DMCLK /DMDAT CP HPR DVDD HPL 3 PDN CCLK /SCL 2 CSN /SDA SDTO BICK TVDD SPP SPN 1 SDTI LRCK MCKI I2C CDTIO /CAD0 VSS3 A B C D E F Top View Figure 4. Pin Layout (AK4951EG) 014004561-E-00-PB 2014/08 -7- [AK4951] ■ Comparison Table of the AK4954A 1. Function Function Resolution AVDD SVDD DVDD TVDD ADC DR, S/N DAC(Headphone) S/N Input Level Output Level (Headphone) MIC Power Output Voltage MIC Power Output Noise MIC-Amp Gain MIC Sensitivity Correction Automatic Wind Noise Reduction Output Volume 3-band DRC Serial μP I/F AK4954A 32bit 2.5V 3.5V 0.9V 5.5V 1.6V ~ 1.98V 1.6V or (DVDD-0.2)V 3.5V 97dB @MGAIN = +20dB 100dB @MGAIN = 0dB 100dB typ. 0.8 x AVDD @MGAIN=0dB typ. 0.485 x AVDD @DVOL=0dB AK4951 24bit 2.8V ~ 3.5V 1.8V 5.5V ← ← 88dB @MGAIN = +18dB 96dB @MGAIN = 0dB 97dB typ. 2.07Vpp @MGAIN=0dB typ. 1.62Vpp @DVOL=0dB typ. 2.3V (2 Line Outputs) typ. 2.0V or 2.4V (2 Line Outputs) -120dBV (A-weighted) +26dB/+20dB/+13dB/+6dB/0dB No -108dBV (A-weighted) +30dB ~ 0dB, 3dB Step Yes No Yes +36dB -52.5dB, 0.375dB Step (Note 1) & +6dB -65.5dB, 0.5dB Step Yes +36dB -52.5dB, 0.375dB Step (Note 1) & +12dB -89.5dB, 0.5dB Step No AK4951EN: I2C Bus AK4951EG: 3-wire Serial, I2C Bus I2C Bus Power Consumption (Stereo Recording) typ. 10.4mW (Low Power Mode) (Headphone Playback) typ. 6.2mW (Low Power Mode) Package typ. 9.3mW typ. 8.6mW AK4951EN: 32-pin QFN 32-pin QFN (4 x 4mm, 0.4mm pitch) (4 x 4mm, 0.4mm pitch) AK4951EG: 32-pin BGA (3.5 x 3.5mm, 0.5mm pitch) Note 1. ALC and Volume circuits are shared by input and output. Therefore, it is impossible to use ALC and Volume control function at the same time for both recording and playback mode. 2. Pin Pin# 15 31 32 AK4954A MCKI/OVF MRF RIN3 AK4951 MCKI REGFIL RIN3/BEEP 014004561-E-00-PB 2014/08 -8- [AK4951] 3. Register Map Addr Register Name 00H 01H 02H 03H 04H 05H 07H 09H 0AH 0BH 0FH 10H 11H 12H 15H 16H 17H 18H 19H 1AH 1BH 1DH 31H 50H ~7FH Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Signal Select 3 Mode Control 1 Mode Control 3 Timer Select ALC Timer Select ALC Mode Control 1 ALC Volume Lch MIC Gain Setting Rch MIC Gain Setting BEEP Control EQ Common Gain Select EQ2 Common Gain Setting EQ3 Common Gain Setting EQ4 Common Gain Setting EQ5 Common Gain Setting Auto HPF Control Digital Filter Select 1 Digital Filter Mode Device Information D7 D6 PMPFIL PMVCM PMOSC 0 SLPSN MGAIN3 SPKG1 SPKG0 LVCM1 LVCM0 PLL3 PLL2 TSDSEL THDET ADRST1 ADRST0 IVTM1 IVTM ALCEQN LMTH2 VOL7 VOL6 MGL7 MGL6 MGR7 MGR6 HPZ BPVCM BPCNT 0 EQ2G5 EQ2G4 EQ3G5 EQ3G4 EQ4G5 EQ4G4 EQ5G5 EQ5G4 0 0 0 0 PMDRC 0 REV3 REV2 D5 D4 D3 D2 D1 D0 PMBP PMHPR DACS 0 DACL PLL1 SMUTE FRATT EQFC1 ALC VOL5 MGL5 MGR5 BEEPS 0 EQ2G3 EQ3G3 EQ4G3 EQ5G3 AHPF 0 PFVOL1 REV1 0 PMHPL MPSEL MICL 1 PLL0 DVOLC FRN EQFC0 RGAIN2 VOL4 MGL4 MGR4 BEEPH EQC5 EQ2G2 EQ3G2 EQ4G2 EQ5G2 SENC2 0 PFVOL0 REV0 LSV M/S PMMP INL1 PTS1 BCKO 0 OVTM1 WTM1 RGAIN1 VOL3 MGL3 MGR3 BPLVL3 EQC4 EQ2G1 EQ3G1 EQ4G1 EQ5G1 SENC1 SDAD PFDAC1 DVN3 PMDAC PMPLL MGAIN2 INL0 PTS0 CKOFF IVOLC OVTM0 WTM0 RGAIN0 VOL2 MGL2 MGR2 BPLVL2 EQC3 EQ2G0 EQ3G0 EQ4G0 EQ5G0 SENC0 HPFC1 PFDAC0 DVN2 PMADR PMSL MGAIN1 INR1 MONO1 DIF1 LPMIC MOFF RFST1 LMTH1 VOL1 MGL1 MGR1 BPLVL1 EQC2 EQ2T1 EQ3T1 EQ4T1 EQ5T1 STG1 HPFC0 ADCPF DVN1 PMADL LOSEL MGAIN0 INR0 MONO0 DIF0 LPDA DVTM RFST0 LMTH0 VOL0 MGL0 MGR0 BPLVL0 BPLVL0 EQ2T0 EQ3T0 EQ4T0 EQ5T0 STG0 HPFAD PFSDO DVN0 DRC Function These bits are added to the AK4951. These bits are removed from the AK4951. These bits are changed from the AK4951. 014004561-E-00-PB 2014/08 -9- [AK4951] ■ PIN/FUNCTION [AK4951EN] No. Pin Name 1 LIN3 2 RIN2 3 LIN2 4 MPWR2 5 MPWR1 RIN1 6 DMCLK LIN1 7 DMDAT 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note I/O I I I O O I O I I Function Lch Analog Input 3 pin Rch Analog Input 2 Pin Lch Analog Input 2 pin MIC Power Supply 2 Pin MIC Power Supply 1 Pin Rch Analog Input 1 Pin (DMIC bit = “0”: default) Digital Microphone Clock pin (DMIC bit = “1”) Lch Analog Input 1 Pin (DMIC bit = “0”: default) Digital Microphone Data Input Pin (DMIC bit = “1”) Reset & Power-down Pin PDN I “L”: Reset & Power-down, “H”: Normal Operation SCL I Control Data Clock Pin SDA I/O Control Data Input/Output Pin SDTI I Audio Serial Data Input Pin SDTO O Audio Serial Data Output Pin LRCK I/O Input/Output Channel Clock Pin BICK I/O Audio Serial Data Clock Pin MCKI I External Master Clock Input Pin TVDD Digital I/O Power Supply Pin, 1.6 or (DVDD-0.2) ~ 3.5V VSS3 Ground 3 Pin SVDD Speaker-Amp Power Supply Pin, 1.8 ~ 5.5V SPN O Speaker-Amp Negative Output Pin (LOSEL bit = “0”: default) ROUT O Rch Stereo Line Output Pin (LOSEL bit = “1”) SPP O Speaker-Amp Positive Output Pin (LOSEL bit = “0”: default) LOUT O Lch Stereo Line Output Pin (LOSEL bit = “1”) DVDD Digital Power Supply Pin, 1.6 ~ 1.98V HPL O Lch Headphone-Amp Output Pin HPR O Rch Headphone-Amp Output Pin Charge-Pump Circuit Negative Voltage Output Pin VEE O This pin must be connected to VSS2 with 2.2μF±20% capacitor in series. VSS2 Ground 2 Pin Positive Charge-Pump Capacitor Terminal Pin CP O This pin must be connected to CN pin with 2.2μF±20% capacitor in series. Negative Charge-Pump Capacitor Terminal Pin CN I This pin must be connected to CP pin with 2.2μF±20% capacitor in series. AVDD Analog Power Supply Pin, 2.8 ~ 3.5V VSS1 Ground 1 Pin Common Voltage Output Pin VCOM O Bias voltage of ADC inputs and DAC outputs. This pin must be connected to VSS1 with 2.2F±20% capacitor in series. LDO Voltage Output pin for Analog Block (typ 2.3V) REGFIL O This pin must be connected to VSS1 with 2.2μF±20% capacitor in series. RIN3 I Rch Analog Input 3 Pin (PMBP bit = “0”: default) BEEP I Beep Signal Input Pin (PMBP bit = “1”) 2. All input pins except analog input pins (LIN1, RIN1, LIN2, RIN2, LIN3, RIN3/BEEP) must not be allowed to float. 014004561-E-00-PB 2014/08 - 10 - [AK4951] [AK4951EG] No. Pin Name B6 RIN2 A6 LIN2 B5 MPWR1 A5 MPWR2 RIN1 A4 DMCLK LIN1 B4 DMDAT I/O I I O O I O I I Function Rch Analog Input 2 Pin Lch Analog Input 2 pin MIC Power Supply 1 Pin MIC Power Supply 2 Pin Rch Analog Input 1 Pin (DMIC bit = “0”: default) Digital Microphone Clock pin (DMIC bit = “1”) Lch Analog Input 1 Pin (DMIC bit = “0”: default) Digital Microphone Data Input Pin (DMIC bit = “1”) Reset & Power-down Pin A3 PDN I “L”: Reset & Power-down, “H”: Normal Operation Control Mode Select Pin D1 I2C I “L”: 3-wire Serial, “H”: I2C Bus CCLK I Control Data Clock Pin (I2C pin = “L”) B3 SCL I Control Data Clock Pin (I2C pin = “H”) CDTIO I/O Control Data Input/Output Pin (I2C pin = “L”) E1 CAD0 I Chip Address Select Pin (I2C pin = “H”) CSN I Chip Select Pin (I2C pin = “L”) A2 SDA I/O Control Data Input/Output Pin (I2C pin = “H”) A1 SDTI I Audio Serial Data Input Pin B2 SDTO O Audio Serial Data Output Pin B1 LRCK I/O Input/Output Channel Clock Pin C2 BICK I/O Audio Serial Data Clock Pin C1 MCKI I External Master Clock Input Pin D2 TVDD Digital I/O Power Supply Pin, 1.6 or (DVDD-0.2) ~ 3.5V F1 VSS3 Ground 3 Pin SPN O Speaker-Amp Negative Output Pin (LOSEL bit = “0”: default) F2 ROUT O Rch Stereo Line Output Pin (LOSEL bit = “1”) SPP O Speaker-Amp Positive Output Pin (LOSEL bit = “0”: default) E2 LOUT O Lch Stereo Line Output Pin (LOSEL bit = “1”) E3 DVDD Digital Power Supply Pin, 1.6 ~ 1.98V F3 HPL O Lch Headphone-Amp Output Pin F4 HPR O Rch Headphone-Amp Output Pin Charge-Pump Circuit Negative Voltage Output Pin F5 VEE O This pin must be connected to VSS2 with 2.2μF±20% capacitor in series. F6 VSS2 Ground 2 Pin Positive Charge-Pump Capacitor Terminal Pin E4 CP O This pin must be connected to CN pin with 2.2μF±20% capacitor in series. Negative Charge-Pump Capacitor Terminal Pin E5 CN I This pin must be connected to CP pin with 2.2μF±20% capacitor in series. E6 AVDD Analog & Speaker-Amp Power Supply Pin, 2.8 ~ 3.5V D6 VSS1 Ground 1 Pin Common Voltage Output Pin D5 VCOM O Bias voltage of ADC inputs and DAC outputs. This pin must be connected to VSS1 with 2.2μF±20% capacitor in series. LDO Voltage Output pin for Analog Block (typ 2.3V) C6 REGFIL O This pin must be connected to VSS1 with 2.2μF±20% capacitor in series. RIN3 I Rch Analog Input 3 Pin (PMBP bit = “0”: default) C5 BEEP I Beep Signal Input Pin (PMBP bit = “1”) Note 3. All input pins except analog input pins (LIN1, RIN1, LIN2, RIN2, LIN3, RIN3/BEEP) must not be allowed to float. 014004561-E-00-PB 2014/08 - 11 - [AK4951] ■ Handling of Unused Pin Unused I/O pins must be processed appropriately as below. Classification Pin Name MPWR, SPN, SPP, HPL, HPR, CP, CN, VEE, Analog LIN1/DMDAT, RIN1/DMCLK, LIN2, RIN2, LIN3, RIN3/BEEP MCKI, SDTI Digital SDTO Setting Open Connect to VSS2 Open 6. Absolute Maximum Ratings (VSS1=VSS2=VSS3=0V; Note 4) Parameter Symbol min max Unit Power Supplies 0.3 Analog AVDD 6.0 V Digital DVDD 0.3 2.5 V Digital I/O TVDD 6.0 V 0.3 Speaker-Amp SVDD 6.0 V 0.3 Input Current, Any Pin Except Supplies IIN mA 10 Analog Input Voltage (Note 5) VINA AVDD+0.3 V 0.3 Digital Input Voltage (Note 6) VIND TVDD+0.3 V 0.3 Operating Temperature (powered applied) Ta 85 40 C Storage Temperature Tstg 150 65 C AK4951EN Pd 840 mW Maximum Power Dissipation (Note 7) AK4951EG Pd 340 mW Note 4. All voltages are with respect to ground. VSS1, VSS2 and VSS3 must be connected to the same analog ground plane. Note 5. LIN1, RIN1, LIN2, RIN2, LIN3 and RIN3/BEEP pins Note 6. PDN, CCLK/SCL, CSN/SDA, CDTIO/CAD0, SDTI, LRCK, BICK and MCKI pins Pull-up resistors at the SDA and SCL pins must be connected to a voltage in the range from TVDD or more to 6V or less. Note 7. This power is the AK4951 internal dissipation that does not include power dissipation of externally connected speakers. The maximum junction temperature is 125C and θja (Junction to Ambient) is 42C/W at JESD51-9 (2p2s) for the AK4951EN and 80C/W at JESD51-9 (2p2s) for the AK4951EG. When Pd =840mW and the θja is 42C/W for the AK4951EN, the junction temperature does not exceed 125C. When Pd =340mW and the θja is 80C/W for the AK4951EG, the junction temperature does not exceed 125C. In this case, the AK4951 will not be damaged by its internal power dissipation. Therefore, the AK4951EN should be used in the condition of θja ≤ 42C/W, and the AK4951EG should be used in the condition of θja ≤ 80C/W. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 014004561-E-00-PB 2014/08 - 12 - [AK4951] 7. Recommended Operating Conditions [AK4951EN] (VSS1=VSS2=VSS3 =0V; Note 4) Parameter Power Supplies Analog (Note 8) Digital Digital I/O (Note 9) Symbol AVDD DVDD TVDD min 2.8 1.6 1.6 or (DVDD-0.2) 1.8 typ 3.3 1.8 max 3.5 1.98 Unit V V 1.8 3.5 V Speaker-Amp SVDD 3.3 5.5 V Note 4. All voltages are with respect to ground. Note 8. The power-up sequence between AVDD, DVDD, TVDD and SVDD is not critical. The PDN pin must be “L” upon power up, and should be changed to “H” after all power supplies are supplied to avoid an internal circuit error. Note 9. The minimum value is higher voltage between DVDD-0.2 and 1.6V. * When SVDD is powered ON and the PDN pin is “L”, AVDD, DVDD and TVDD can be powered ON/OFF. When TVDD is powered ON and the PDN pin is “L”, AVDD, DVDD and SVDD can be powered ON/OFF. The PDN pin must be set to “H” after all power supplies are ON, when the AK4951EN is powered-up from power-down state. [AK4951EG] (VSS1=VSS2=VSS3 =0V; Note 4) Parameter Power Supplies Analog & Speaker (Note 10) Digital Digital I/O (Note 11) Symbol AVDD DVDD TVDD min 2.8 1.6 1.6 or (DVDD-0.2) typ 3.3 1.8 max 3.5 1.98 Unit V V 1.8 3.5 V Note 4. All voltages are with respect to ground. Note 10. The power-up sequence between AVDD, DVDD and TVDD is not critical. The PDN pin must be “L” upon power up, and should be changed to “H” after all power supplies are supplied to avoid an internal circuit error. Note 11. The minimum value is higher voltage between DVDD-0.2 and 1.6V. * When TVDD is powered ON and the PDN pin is “L”, AVDD and DVDD can be powered ON/OFF. The PDN pin must be set to “H” after all power supplies are ON, when the AK4951EG is powered-up from power-down state. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. 014004561-E-00-PB 2014/08 - 13 - [AK4951] 8. Electrical Characteristics ■ Analog Characteristics (Ta=25C; AVDD=SVDD=3.3V, TVDD=DVDD=1.8V; VSS1=VSS2=VSS3=0V; fs=48kHz, BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Bandwidth=20Hz 20kHz; unless otherwise specified) Parameter min typ max Unit MIC Amplifier: LIN1, RIN1, LIN2, RIN2, LIN3, RIN3 pins Input Resistance 20 30 40 k Gain Gain Setting 0 +30 dB Step Width 3 dB MIC Power Supply: MPWR1, MPWR2 pins MICL bit = “0” 2.2 2.4 2.6 V Output Voltage MICL bit = “1” 1.8 2.0 2.2 V Output Noise Level (A-weighted) -108 dBV Load Resistance 1.0 k Load Capacitance 30 pF PSRR (f = 1kHz) (Note 12) 100 dB ADC Analog Input Characteristics: LIN1, RIN1, LIN2, RIN2, LIN3, RIN3 pins → ADC (Programmable Filter = OFF) → SDTO Resolution 24 Bits (Note 14) 0.261 Vpp Input Voltage (Note 13) (Note 15) 1.86 2.07 2.28 Vpp (Note 14) 73 83 dBFS S/(N+D) (-1dBFS) (Note 15: AK4951EN) 85 dBFS (Note 15: AK4951EG) 84 dBFS (Note 14) 78 88 dB D-Range (60dBFS, A-weighted) (Note 15) 96 dB (Note 14) 78 88 dB S/N (A-weighted) (Note 15) 96 dB (Note 14) 75 100 dB Interchannel Isolation (Note 15) 110 dB (Note 14) 0 0.5 dB Interchannel Gain Mismatch (Note 15) 0 0.5 dB PSRR (f = 1kHz) (Note 12) 80 dB Note 12. PSRR applied to AVDD with 500mVpp sine wave. Note 13. Vin = 0.9 x 2.3Vpp (typ) @MGAIN3-0 bits = “0000” (0dB) Note 14. MGAIN3-0 bits = “0110” (+18dB) Note 15. MGAIN3-0 bits = “0000” (0dB) 014004561-E-00-PB 2014/08 - 14 - [AK4951] Parameter min typ max Unit DAC Characteristics: Resolution 24 Bits Headphone-Amp Characteristics: DAC → HPL, HPR pins, ALC=OFF, IVOL=DVOL= 0dB, RL=16 Output Voltage (0dBFS) 1.44 1.60 1.76 Vpp RL=16Ω 50 75 dB S/(N+D) RL=10kΩ 80 dB S/N (A-weighted) 87 97 dB Interchannel Isolation 65 80 dB Interchannel Gain Mismatch 0 0.8 dB Output Offset Voltage -1 0 +1 mV Load Resistance 16 Load Capacitance 300 pF AVDD 74 dB PSRR (f = 1kHz) (Note 16) DVDD 90 dB Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, IVOL=DVOL= 0dB, RL=8, BTL Output Voltage 3.18 Vpp SPKG1-0 bits = “00”, 0.5dBFS (Po=150mW) 3.20 4.00 4.80 Vpp SPKG1-0 bits = “01”, 0.5dBFS (Po=250mW) 1.79 Vrms SPKG1-0 bits = “10”, 0.5dBFS (Po=400mW) SPKG1-0 bits = “11”, 0.5dBFS (Po=1000mW) 2.83 Vrms (SVDD=5V) S/(N+D) 80 dB SPKG1-0 bits = “00”, 0.5dBFS (Po=150mW) 40 75 dB SPKG1-0 bits = “01”, 0.5dBFS (Po=250mW) 20 dB SPKG1-0 bits = “10”, 0.5dBFS (Po=400mW) SPKG1-0 bits = “11”, 0.5dBFS (Po=1000mW) 20 dB (AK4951EN: SVDD=5V) S/N (A-weighted) SPKG1-0 bits = “01” 80 99 dB Output Offset Voltage SPKG1-0 bits = “01” -30 0 +30 mV Load Resistance 8 Load Capacitance 100 pF AVDD 80 dB PSRR (f = 1kHz) (Note 17) DVDD 60 dB Stereo Line Output Characteristics: DAC → LOUT, ROUT pins, ALC=OFF, IVOL=DVOL = 0dB, RL=10k, LVCM1-0 bits = “01” LVCM0 bit = “0”, SVDD=2.8V 2.26 Vpp (0dBFS) LVCM0 bit = “1” 1.0 Vrms Output Voltage LVCM0 bit = “0”, SVDD=2.8V 1.44 1.6 1.76 Vpp (-3dBFS) LVCM0 bit = “1” 1.82 2.0 2.22 Vpp LVCM0 bit = “0”, SVDD=2.8V 80 dB (0dBFS) S/(N+D) LVCM0 bit = “1” 80 dB (-3dBFS) 75 85 dB S/N (A-weighted) 82 94 dB Interchannel Isolation 100 dB Interchannel Gain Mismatch 0 0.8 dB Load Resistance 10 k Load Capacitance 30 pF Note 16. PSRR applied with 500mVpp sine wave. Note 17. PSRR applied to AVDD or SVDD with 500mVpp sine wave. 014004561-E-00-PB 2014/08 - 15 - [AK4951] Parameter min typ max Unit Mono Input: BEEP pin (PMBP bit =“1”, BPVCM bit = “0”, BPLVL3-0 bits = “0000”) Input Resistance 46 66 86 k Maximum Input Voltage (Note 18) 1.54 Vpp Gain BEEP pin → HPL, HPR pins 0 +1 dB 1 BEEP pin → SPP/SPN pins (Note 19) SPKG1-0 bits = “00” +4.4 +6.4 +8.4 dB SPKG1-0 bits = “01” +8.4 dB SPKG1-0 bits = “10” +11.1 dB SPKG1-0 bits = “11” +14.9 dB BEEP pin → LOUT, ROUT pins LVCM1-0 bits = “00” -1 0 +1 dB LVCM 1-0 bits = “01” +2 dB LVCM 1-0 bits = “10” +2 dB LVCM 1-0 bits = “11” +4 dB Power Supplies: Power Up (PDN pin = “H”) MIC + ADC + DAC + Headphone out AVDD+DVDD+TVDD (Note 20) 6.5 9.8 mA AVDD+DVDD+TVDD (Note 21) 5.7 mA SVDD (No Load) 36 54 A MIC + ADC + DAC + Speaker out AK4951EN 5.6 8.4 mA AVDD+DVDD+TVDD (Note 22) AK4951EG 7.4 11.3 mA AK4951EN 4.7 mA AVDD+DVDD+TVDD (Note 23) AK4951EG 6.5 mA SVDD (No Load) AK4951EN 1.8 2.7 mA Power Down (PDN pin = “L”) (Note 24) AVDD+DVDD+TVDD+SVDD 0 10 A SVDD (Note 25) 0 10 A Note 18. The maximum value is AVDD Vpp when BPVCM bit = “1”. However, a click noise may occur when the amplitude after BEEP-Amp is 0.5Vpp or more. (set by BPLVL3-0 bits) Note 19. The gain is in inverse proportion to external input resistance. Note 20. When PLL Master Mode (MCKI=12MHz), and PMADL=PMADR=PMDAC=PMPFIL=PMHPL= PMHPR= PMVCM=PMPLL =PMBP=PMMP=M/S bits = “1”. In this case, the MPWR1 (MPWR2) pin outputs 0mA. AVDD= 4.4mA (typ), DVDD= 2.0mA (typ), TVDD= 0.08mA (typ). Note 21. When EXT Slave Mode (PMPLL=M/S bits =“0”), PMADL=PMADR=PMDAC=PMHPL=PMHPR= PMVCM=PMBP=PMMP bits = “1”, and PMPFIL bit = “0”. In this case, the MPWR1 (MPWR2) pin outputs 0mA. AVDD= 4.2mA (typ), DVDD= 1.5mA (typ), TVDD= 0.02mA (typ). Note 22. When PLL Master Mode (MCKI=12MHz), and PMADL=PMADR=PMDAC=PMPFIL=PMSL= PMVCM= PMPLL =PMBP=PMMP=SLPSN=DACS=M/S bits = “1”. In this case, the MPWR1 (MPWR2) pin outputs 0mA. AVDD= 3.8mA (AK4951EN: typ), 5.6mA (AK4951EG: typ), DVDD= 1.7mA (typ), TVDD= 0.08mA (typ). Note 23. When EXT Slave Mode (PMPLL=M/S bits =“0”), PMADL=PMADR=PMDAC=PMSL=PMVCM= PMBP=PMMP=SLPSN=DACS bits = “1”, and PMPFIL bit = “0”. In this case, the MPWR1 (MPWR2) pin outputs 0mA. AVDD= 3.5mA (AK4951EN: typ), 5.3mA (AK4951EG: typ), DVDD= 1.2mA (typ), TVDD= 0.02mA (typ). Note 24. All digital input pins are fixed to TVDD or VSS2. Note 25. When AVDD, DVDD and TVDD are powered OFF. 014004561-E-00-PB 2014/08 - 16 - [AK4951] ■ Power Consumption on Each Operation Mode PMVCM PMSL PMDAC PMADL PMADR PMHPL PMHPR PMPFIL LOSEL Conditions: Ta=25C; AVDD=SVDD=3.3V, TVDD=DVDD=1.8V; VSS1=VSS2=VSS3=0V; fs=48kHz, Programmable Filter=OFF, External Slave Mode, BICK=64fs; LIN1/RIN1 input = No signal; SDTI input = No data; Headphone & Speaker outputs = No load. Power Management Bit Total AVDD DVDD TVDD SVDD Mode Power [mA] [mA] [mA] [mA] [mW] All Power-down LIN1/RIN1 → ADC LIN1 (Mono) → ADC DAC → HP DAC → SPK DAC → Line out LIN1/RIN1 → ADC & DAC → HP LIN1/RIN1 → ADC & DAC → SPK LIN1/RIN1 → ADC & DAC → Line out 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2.40 1.62 2.15 1.50 1.68 0 0.75 0.75 0.80 0.50 0.50 0 0.02 0.02 0.02 0.02 0.02 0 0 0 0 1.80 0.34 0 9.3 6.7 8.6 11.8 7.6 1 0 1 1 1 1 1 0 0 3.75 1.55 0.02 0 15.2 1 1 1 1 1 0 0 0 0 3.10 1.25 0.02 1.80 18.5 1 1 1 1 1 0 0 0 1 3.30 1.25 0.02 0.34 14.3 Table 1. Power Consumption on Each Operation Mode (typ) 014004561-E-00-PB 2014/08 - 17 - [AK4951] ■ Filter Characteristics (Ta =25C; fs=48kHz; AVDD=2.8 3.5V, SVDD=1.8 ~ 5.5V, DVDD = 1.6 ~ 1.98V, TVDD = 1.6 or (DVDD-0.2) 3.5V) Parameter Symbol min typ max Unit ADC Digital Filter (Decimation LPF): Passband (Note 26) PB 0 18.8 kHz 0.16dB 21.1 kHz 0.66dB 21.7 kHz 1.1dB 24.1 kHz 6.9dB Stopband (Note 26) SB 28.4 kHz Passband Ripple PR dB 0.16 Stopband Attenuation SA 73 dB Group Delay (Note 27) GD 17 1/fs Group Delay Distortion 0 GD s ADC Digital Filter (HPF): HPFC1-0 bits = “00” Frequency Response FR 3.7 Hz 3.0dB (Note 26) 10.9 Hz 0.5dB 23.9 Hz 0.1dB DAC Digital Filter (LPF): Passband (Note 26) PB 0 21.8 kHz 0.05dB 24 kHz 6.0dB Stopband (Note 26) SB 27.0 kHz Passband Ripple PR dB 0.05 Stopband Attenuation SA 70 dB Group Delay (Note 27) GD 29 1/fs DAC Digital Filter (LPF) + SCF: FR dB Frequency Response: 0 20.0kHz 1.0 Note 26. The passband and stopband frequencies scale with fs (sampling frequency). Note 27. A calculating delay time which is induced by digital filtering. This time is from the input of an analog signal to the setting of 24-bit data of both channels to the ADC output register. For the DAC, this time is from setting the 24-bit data of a channel from the input register to the output of analog signal. For the signal through the programmable filters (Microphone Sensitivity Correction + Automatic Wind Noise Reduction Filter + 1st order HPF + 1st order LPF + Stereo Separation Emphasis + 4-band Equalizer + ALC + 1-band Equalizer), the group delay is increased by 4/fs from the value above in both recording and playback modes if there is no phase change by the IIR filter. 014004561-E-00-PB 2014/08 - 18 - [AK4951] ■ DC Characteristics (Ta =25C; fs=48kHz; AVDD=2.8 ~ 3.5V, SVDD= 1.8 ~ 5.5V, DVDD = 1.6 ~ 1.98V, TVDD = 1.6 or (DVDD-0.2) 3.5V) Parameter Symbol min typ max Unit Audio Interface & Serial µP Interface (CDTIO/CAD0, CSN/SDA, CCLK/SCL, I2C, PDN, BICK, LRCK, SDTI, MCKI pins) High-Level Input Voltage (TVDD ≥ 2.2V) VIH 70%TVDD V (TVDD < 2.2V) VIH 80%TVDD V Low-Level Input Voltage (TVDD ≥ 2.2V) VIL 30%TVDD V (TVDD < 2.2V) VIL 20%TVDD V Input Leakage Current Iin1 10 A Audio Interface & Serial µP Interface (CDTIO, SDA, BICK, LRCK, SDTO pins Output) High-Level Output Voltage (Iout = 80A) VOH TVDD0.2 V Low-Level Output Voltage (Except SDA pin : Iout = 80A) VOL1 0.2 V (SDA pin, 2.0V TVDD 3.5V: Iout = 3mA) VOL2 0.4 V (SDA pin, 1.6V TVDD < 2.0V: Iout = 3mA) VOL2 20%TVDD V Digital Microphone Interface (DMDAT pin Input; DMIC bit = “1”) High-Level Input Voltage VIH2 65%AVDD V Low-Level Input Voltage VIL2 35%AVDD V Input Leakage Current Iin2 10 A Digital Microphone Interface (DMCLK pin Output; DMIC bit = “1”) High-Level Output Voltage (Iout=80A) VOH3 AVDD-0.4 V Low-Level Output Voltage (Iout= 80A) VOL3 0.4 V 014004561-E-00-PB 2014/08 - 19 - [AK4951] ■ Switching Characteristics (Ta=25C; fs=48kHz; CL=20pF; AVDD=2.83.5V, SVDD=1.8~5.5V, DVDD=1.6~1.98V, TVDD=1.6 or (DVDD-0.2)3.5V) Parameter Symbol min typ max Unit PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency PLL3-0 bits = “0100” fCLK 11.2896 MHz PLL3-0 bits = “0101” fCLK 12.288 MHz PLL3-0 bits = “0110” fCLK 12 MHz PLL3-0 bits = “0111” fCLK 24 MHz PLL3-0 bits = “1100” fCLK 13.5 MHz PLL3-0 bits = “1101” fCLK 27 MHz Pulse Width Low tCLKL 0.4/fCLK s Pulse Width High tCLKH 0.4/fCLK s LRCK Output Timing Frequency fs Table 7 Hz Duty Cycle Duty 50 % BICK Output Timing Frequency BCKO bit = “0” fBCK 32fs Hz BCKO bit = “1” fBCK 64fs Hz Duty Cycle dBCK 50 % PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency PLL3-0 bits = “0010” fs fBCK/32 Hz PLL3-0 bits = “0011” fs fBCK/64 Hz Duty Duty 45 55 % BICK Input Timing Frequency PLL3-0 bits = “0010” fBCK 0.256 1.536 MHz PLL3-0 bits = “0011” fBCK 0.512 3.072 MHz Pulse Width Low tBCKL 0.4/fBCK s Pulse Width High tBCKH 0.4/fBCK s External Slave Mode MCKI Input Timing Frequency CM1-0 bits = “00” fCLK 256fs Hz CM1-0 bits = “01” fCLK 384fs Hz CM1-0 bits = “10” fCLK 512fs Hz CM1-0 bits = “11” fCLK 1024fs Hz Pulse Width Low tCLKL 0.4/fCLK s Pulse Width High tCLKH 0.4/fCLK s LRCK Input Timing Frequency CM1-0 bits = “00” fs 8 48 kHz CM1-0 bits = “01” fs 8 48 kHz CM1-0 bits = “10” fs 8 48 kHz CM1-0 bits = “11” fs 8 24 kHz Duty Duty 45 55 % BICK Input Timing Frequency fBCK 32fs 64fs Hz Pulse Width Low tBCKL 130 ns Pulse Width High tBCKH 130 ns 014004561-E-00-PB 2014/08 - 20 - [AK4951] Parameter Symbol min typ External Master Mode MCKI Input Timing Frequency 256fs fCLK 2.048 384fs fCLK 3.072 512fs fCLK 4.096 1024fs fCLK 8.192 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK Output Timing Frequency fs fCLK/256 CM1-0 bits = “00” fs fCLK/384 CM1-0 bits = “01” fs fCLK/512 CM1-0 bits = “10” fs fCLK/1024 CM1-0 bits = “11” Duty Cycle Duty 50 BICK Output Timing Frequency BCKO bit = “0” fBCK 32fs BCKO bit = “1” fBCK 64fs Duty Cycle dBCK 50 Audio Interface Timing Master Mode tBLR BICK “” to LRCK Edge (Note 28) 40 LRCK Edge to SDTO (MSB) tLRD 70 2 (Except I S mode) tBSD BICK “” to SDTO 70 SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Slave Mode tLRB 50 LRCK Edge to BICK “” (Note 28) tBLR 50 BICK “” to LRCK Edge (Note 28) LRCK Edge to SDTO (MSB) tLRD (Except I2S mode) tBSD BICK “” to SDTO SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Digital Audio Interface Timing; CL=100pF DMCLK Output Timing Period tSCK 1/(64fs) Rising Time tSRise Falling Time tSFall Duty Cycle dSCK 40 50 Audio Interface Timing DMDAT Setup Time tDSDS 50 DMDAT Hold Time tDSDH 0 Note 28. BICK rising edge must not occur at the same time as LRCK edge. 014004561-E-00-PB max Unit 12.288 18.432 24.576 24.576 - MHz MHz MHz MHz s s - Hz Hz Hz Hz % - Hz Hz % 40 70 ns ns 70 - ns ns ns 80 ns ns ns 80 - ns ns ns 10 10 60 s ns ns % - ns ns 2014/08 - 21 - [AK4951] Parameter Symbol min typ max Unit 2 Control Interface Timing (I C Bus) SCL Clock Frequency fSCL 400 kHz Bus Free Time Between Transmissions tBUF 1.3 s Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 s Clock Low Time tLOW 1.3 s Clock High Time tHIGH 0.6 s Setup Time for Repeated Start Condition tSU:STA 0.6 s SDA Hold Time from SCL Falling (Note 30) tHD:DAT 0 s SDA Setup Time from SCL Rising tSU:DAT 0.1 s Rise Time of Both SDA and SCL Lines tR 0.3 s Fall Time of Both SDA and SCL Lines tF 0.3 s Setup Time for Stop Condition tSU:STO 0.6 s Capacitive Load on Bus Cb 400 pF Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 50 ns Control Interface Timing (3-wire Serial: AK4951EG) CCLK Period tCCK 200 ns CCLK Pulse Width Low tCCKL 80 ns Pulse Width High tCCKH 80 ns CDTIO Setup Time tCDS 40 ns CDTIO Hold Time tCDH 40 ns CSN “H” Time tCSW 150 ns tCSS 50 ns CSN Edge to CCLK “” (Note 31) tCSH 50 ns CCLK “” to CSN Edge (Note 31) tDCD ns CCLK “” to CDTIO (at Read Command) 70 tCCZ ns CSN “” to CDTIO (Hi-Z) (at Read Command) (Note 32) 70 Power-down & Reset Timing PDN Accept Pulse Width (Note 33) tAPD 200 ns PDN Reject Pulse Width (Note 33) tRPD 50 ns PMADL or PMADR “” to SDTO valid (Note 34) ADRST1-0 bits =“00” tPDV 1059 1/fs ADRST1-0 bits =“01” tPDV 267 1/fs ADRST1-0 bits =“10” tPDV 531 1/fs ADRST1-0 bits =“11” tPDV 135 1/fs VCOM Voltage Rising Time (Note 35) tRVCM 0.6 2.0 ms 2 Note 29. I C Bus is a trademark of NXP B.V. Note 30. Data must be held for sufficient time to bridge the 300ns transition time of SCL. Note 31. CCLK rising edge must not occur at the same time as CSN edge. Note 32. It is the time of 10% potential change of the CDTIO pin when RL = 1kΩ (pull-up or TVDD). Note 33. The AK4951 can be reset by the PDN pin = “L”. The PDN pin must be held “L” for more than 200ns for a certain reset. The AK4951 is not reset by the “L” pulse less than 50ns. Note 34. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”. Note 35. All analog blocks including PLL block are powered up after the VCOM voltage (VCOM pin) rises up. An external capacitor of the VCOM pin is 2.2F and the REGFIL pin is 2.2F. The capacitance variation should be ±50%. 014004561-E-00-PB 2014/08 - 22 - [AK4951] ■ Timing Diagram 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs 50%TVDD LRCK tLRCKH tLRCKL 1/fBCK Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 BICK 50%TVDD tBCKH tBCKL Duty = tBCKH x fBCK x 100 tBCKL x fBCK x 100 Figure 5. Clock Timing (PLL/EXT Master mode) 50%TVDD LRCK tBLR tBCKL BICK 50%TVDD tLRD tBSD SDTO 50%TVDD tSDS tSDH VIH SDTI VIL Figure 6. Audio Interface Timing (PLL/EXT Master mode) 014004561-E-00-PB 2014/08 - 23 - [AK4951] VIL MCKI 1/fs VIH LRCK VIL tLRCKH Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tLRCKL 1/fBCK VIH BICK VIL tBCKH tBCKL Figure 7. Clock Timing (PLL Slave mode) 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRCKH Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tLRCKL 1/fBCK VIH BICK VIL tBCKH tBCKL Figure 8. Clock Timing (EXT Slave mode) VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRD tBSD SDTO MSB tSDS 50%TVDD tSDH VIH SDTI VIL Figure 9. Audio Interface Timing (PLL/EXT Slave mode) 014004561-E-00-PB 2014/08 - 24 - [AK4951] tSCK 65%AVDD DMCLK 50%AVDD 35%AVDD tSCKL tSRise tSFall dSCK = 100 x tSCKL / tSCK Figure 10. DMCLK Clock Timing 65%AVDD DMCLK 35%AVDD tDSDS tDSDH VIH2 DMDAT VIL2 Figure 11. Audio Interface Timing (DCLKP bit = “1”) 65%AVDD DMCLK 35%AVDD tSDS tSDH VIH2 DMDAT VIL2 Figure 12. Audio Interface Timing (DCLKP bit = “0”) VIH SDA VIL tBUF tLOW tHIGH tR tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA Start tSU:STO Stop 2 Figure 13. I C Bus Mode Timing 014004561-E-00-PB 2014/08 - 25 - [AK4951] VIH CSN VIL tCSH tCSS tCCKL tCCKH VIH CCLK VIL tCCK tCDH tCDS VIH CDTIO R/W A6 A5 VIL Figure 14. WRITE Command Input Timing (3-wire Serial: AK4951EG) tCSW VIH CSN VIL tCSH tCSS VIH CCLK VIL VIH CDTIO D2 D1 D0 VIL Figure 15. WRITE Data Input Timing (3-wire Serial: AK4951EG) VIH CSN VIL VIH CCLK Clock, H or L tCCZ tDCD CDTIO D3 VIL D2 D1 D0 Hi-Z 50% TVDD Figure 16. Read Data Output Timing (3-wire Serial: AK4951EG) 014004561-E-00-PB 2014/08 - 26 - [AK4951] tAPD tRPD PDN VIL Figure 17. Power Down & Reset Timing 1 PMADL/R bit or PMDML/R bit tPDV SDTO 50%TVDD Figure 18. Power Down & Reset Timing 2 PMVCM bit tRVCM 1.15V VCOM pin Figure 19. VCOM Rising Timing 014004561-E-00-PB 2014/08 - 27 - [AK4951] 9. Package ■ AK4951EN Outline Dimensions 32-pin QFN (Unit: mm) 0.75 ± 0.05 B 17 24 25 16 Exposed Pad 32 9 8 A 1 0~0.05 4.0 ± 0.1 C0.35 0.40 (0.20) 0.35 ± 0.1 (0.25) 2.8 ± 0.1 4.0 ± 0.1 2.8 ± 0.1 0.20 ± 0.05 0.10 M C A B 0.08 C C Note. The exposed pad on the bottom surface of the package must be connected to the ground. ■ AK4951EN Material & Lead finish Package molding compound: Epoxy Resin, Halogen (Br and Cl) free Lead frame material: Cu Alloy Lead frame surface treatment: Solder (Pb free) plate ■ AK4951EN Marking 4951 XXXX 1 XXXX: Date code (4 digit) Pin #1 indication 014004561-E-00-PB 2014/08 - 28 - [AK4951] ■ AK4951EG Outline Dimensions 32-pin BGA (Unit: mm) Top View Bottom View A 3.50.1 0.5 B 6 0.5 5 3.50.1 4 3 2 1 1 F C 0.08 0. 870.13 0.210.05 A E D C B 32 x (0.27~0.37) A 0.15 M C A B C ■ AK4951EG Material & Lead finish Package material: Epoxy Resin, Halogen (Br and Cl) free Solder ball material: SnAgCuNi (LF35) ■ AK4951EG Marking 4951 XXXX A1 XXXX: Date code (4 digit) Pin #A1 indication 014004561-E-00-PB 2014/08 - 29 - [AK4951] Thank you for your access to AKM product information. More detail product information is available, please contact our sales office or authorized distributors. IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. 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Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. 014004561-E-00-PB 2014/08 - 30 -