[AK4954A] AK4954A 32-bit Stereo CODEC with MIC/HP/SPK-AMP GENERAL DESCRIPTION The AK4954A is a low power consumption 32-bit stereo CODEC with a microphone, a headphone and a speaker amplifiers. The input circuits include a microphone amplifier and an ALC (Automatic Level Control) circuit, and the output circuits include a cap-less headphone amplifier and a speaker amplifier. It is suitable for portable application with recording/playback function. The integrated charge pump circuit generates a negative voltage and removes the output AC coupling capacitors. The speaker amplifier has a wide operating voltage range, which is from 0.9V to 5.5V, enabling a direct drive to batteries. The AK4954A is available in a small 32-pin QFN (4x4mm 0.4mm pitch), utilizing less board space than competitive offerings. FEATURES 1. Recording Function • Two Low Noise Microphone Power Supplies • Stereo Single-ended input with three Selectors • Low Noise Microphone Amplifier (+26dB/+20dB/+13dB/+6dB/0dB) • Digital ALC (Automatic Level Control) (Setting Range: +36dB ∼ −52.5dB, 0.375dB Step) • ADC Performance: S/(N+D): 88dB, DR, S/N: 97dB (Microphone Amplifier =+20dB) S/(N+D): 88dB, DR, S/N: 100dB (Microphone Amplifier =0dB) • Two Types of Decimation Filters • Overflow Detection • Wind-noise Reduction Filter • Stereo Separation Emphasis Circuit • 5-band Notch Filter • Digital Microphone Interface 2. Playback Function • Digital ALC (Automatic Level Control) (Setting Range: +36dB ~ −52.5dB, 0.375dB Step) • 3-band Dynamic Range Control Circuit • Digital Volume Control (+6dB ~ −65.5dB, 0.5dB Step, Mute) • Capacitor-less Stereo Headphone Amplifier - HP-Amplifier Performance: S/(N+D): 65dB@20mW, S/N: 100dB - Output Power: 20mW@16Ω - Pop Noise Free at Power-ON/OFF • Mono Speaker-Amplifier (with Stereo Line Output Switch) - SPK-Amplifier Performance: S/(N+D): 70dB@250mW Output Noise Level: -97dBV - BTL Output - Output Power: 400mW@8Ω (SVDD=3.3V) 100mW@8Ω (SVDD=1.5V) • Beep Generator 3. Power Management MS1542-E-00-PB 2013/06 -1- [AK4954A] 4. Master Clock: (1) PLL Mode • Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin) 32fs or 64fs (BICK pin) (2) External Clock Mode • Frequencies: 256fs, 384fs, 512fs or 1024fs (MCKI pin) 5. Sampling Frequencies • PLL Slave Mode (BICK pin): 8kHz ∼ 96kHz • PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz • EXT Master/Slave Mode: 8kHz ~ 96kHz (256fs), 8kHz ~ 48kHz (384fs), 8kHz ~ 48kHz (512fs), 8kHz ~ 12kHz (1024fs) 6. Master/Slave mode 7. Audio Interface Format: MSB First, 2’s complement • ADC: 16/24/32-bit MSB justified, 16/24/32-bit I2S • DAC: 16/24/32-bit MSB justified, 16/24-bit LSB justified, 16/24/32-bit I2S 8. Serial μP I/F: I2C Bus (Ver 1.0, 400kHz Fast-Mode) 9. Ta = −30 ∼ 85°C 10. Power Supply: • Analog Power Supply (AVDD): 2.5 ~ 3.5V • Digital Power Supply (DVDD): 1.6 ~ 1.98V • Digital I/O Power Supply (TVDD): 1.6 or (DVDD-0.2) ~ 3.5V • Speaker Power Supply (SVDD): 0.9 ~ 5.5V 11. Package: 32-pin QFN (4 x 4mm, 0.4mm pitch) MS1542-E-00-PB 2013/06 -2- [AK4954A] ■ Block Diagram AVDD MRF VSS1 VCOM DVDD TVDD VSS2 PMMP MPWR2 PDN MPWR1 PMVCM MIC Power Supply Control Logic VCOM SCL SDA PMADL Internal MIC LIN1/DDAT RIN1 /DMCLK PMADL or PMADR PMADR External MIC LIN2 ADC SDTI HPF1 RIN2 PMPFIL LIN3 Line In HPF2 BICK LPF RIN3 Stereo Separation 4-band EQ * OVF SDTI SDTO 1-band EQ Beep Gen VSS3 LRCK ALC PMBP SVDD Audio I/F SDTO PMSL Mono Speaker or Stereo Line-out SPP/LOUT PMPLL SPN/ROUT PLL PMHPL * MCKI PMDAC HPL Cap-less Headphone DVL/R DAC SMUTE HPR DRC PMHPR PMDRC PMHPL or PMHPR Charge Pump VEE CN CP (The OVF and MCKI pins share the No. 15 pin terminal.) Figure 1. Block Diagram MS1542-E-00-PB 2013/06 -3- [AK4954A] ■ Ordering Guide AK4954AEN AKD4954 −30 ∼ +85°C 32-pin QFN (0.4mm pitch) Evaluation board for AK4954A VEE HPR HPL DVDD SPP/LOUT SPN/ROUT SVDD VSS3 24 23 22 21 20 19 18 17 ■ Pin Layout LRCK VSS1 29 Top View 12 SDTO VCOM 30 11 SDTI MRF 31 10 SDA RIN3 32 9 SCL 8 13 PDN AK4954A 7 28 LIN1/DMDAT AVDD 6 BICK RIN1/DMCLK 14 5 27 MPWR1 CN 4 MCKI/OVF MPWR2 15 3 26 LIN2 CP 2 TVDD RIN2 16 1 25 LIN3 VSS2 MS1542-E-00-PB 2013/06 -4- [AK4954A] ■ Comparison with AK4953A Function Resolution AVDD DVDD SVDD TVDD ADC DR, S/N DAC S/N Input level Output level (Headphone) MIC Power Output Voltage MIC Power Output Noise MIC-Amp ADC Overflow Output Stereo Emphasis Output Volume AK4953A 24-bit 2.85V ∼ 3.5V 1.6V ~ 2.0V 0.9V ∼ 5.5V DVDD ∼ 3.5V 88dB @ MGAIN = +20dB 96dB @ MGAIN = 0dB 96dB typ. 2.4Vpp @ MIC Gain=0dB typ. 1.75Vpp @ DVOL=0dB typ 2.3V (2 Line Outputs) -108dBV (A-weighted) 0dB/+12dB/+16dB/+20dB/+23dB/ +26dB/+29dB No No +36dB ∼ -54dB, 0.375dB Step (Note 1) & +12dB ∼ -115dB, 0.5dB Step No No AK4954A 32-bit 2.5V ∼ 3.5V 1.6V ~ 1.98V ← 1.6V or (DVDD-0.2)V ∼ 3.5V 97dB @ MGAIN = +20dB 100dB @ MGAIN = 0dB 100dB typ. 0.8 x AVDD @ MGAIN=0dB typ. 0.485 x AVDD @ DVOL=0dB 0.8 x AVDD (2 Line Outputs) -120dBV (A-weighted) 0dB/+6dB/+13dB/+20dB/+26dB Yes (pin selectable OVF/MCKI) Yes +36dB ∼ -52.5dB, 0.375dB Step (Note 1) & +6dB ∼ -65.5dB, 0.5dB Step Yes (for Playback) Yes Dynamic Range Control Line Output Switch for Speaker-Amp 11.2896MHz, 12MHz, 12.288MHz, Master Clock Reference for 11.2896MHz, 12MHz, 13.5MHz, 24MHz, 27MHz 13.5MHz, 24MHz, 27MHz PLL Mode 3-wire Serial or I2C Bus I2C Bus Serial μP Interface Power Consumption typ. 10.4mW (Low-power operation mode) (Stereo Recording) typ. 9.4mW typ. 6.2mW (Low-power operation mode) (Headphone Playback) typ. 10.2mW 36-pin QFN (5 x 5mm, 0.4mm pitch) 32-pin QFN (4 x 4mm, 0.4mm pitch) Package Note 1. ALC and Volume circuits are shared by input and output. Therefore, it is impossible to use ALC and Volume control function at the same time for both recording and playback mode. MS1542-E-00-PB 2013/06 -5- [AK4954A] PIN/FUNCTION No. 1 2 3 4 5 Pin Name LIN3 RIN2 LIN2 MPWR2 MPWR1 RIN1 DMCLK LIN1 DMDAT I/O I I I O O I O I I Function Lch Analog Input 3 Pin Rch Analog Input 2 Pin Lch Analog Input 2 pin Microphone Power Supply Pin for Microphone 2 Microphone Power Supply Pin for Microphone 1 Rch Analog Input 1 Pin (DMIC bit = “0”: default) 6 Digital Microphone Clock pin (DMIC bit = “1”) Lch Analog Input 1 Pin (DMIC bit = “0”: default) 7 Digital Microphone Data Input Pin (DMIC bit = “1”) Power-down & Reset 8 PDN I When “L”, the AK4954A is in power-down mode and is held in reset. The AK4954A must be always reset upon power-up. 9 SCL I Control Data Clock Pin 10 SDA I/O Control Data Input/Output Pin 11 SDTI I Audio Serial Data Input Pin 12 SDTO O Audio Serial Data Output Pin 13 LRCK I/O Input/Output Channel Clock Pin 14 BICK I/O Audio Serial Data Clock Pin MCKI I External Master Clock Input Pin (OVFL bit = “0”: default) 15 OVF O Over Flow Flag Output Pin (OVFL bit = “1”) 16 TVDD Digital I/O Power Supply Pin, 1.6 ~ 3.5V 17 VSS3 Ground 3 Pin 18 SVDD Speaker Amplifier Power Supply Pin, 0.9 ~ 5.5V SPN O Speaker Amplifier Negative Output Pin (LOSEL bit = “0”: default) 19 ROUT O Rch Stereo Line Output Pin (LOSEL bit = “1”) SPP O Speaker Amplifier Positive Output Pin (LOSEL bit = “0”: default) 20 LOUT O Lch Stereo Line Output Pin (LOSEL bit = “1”) 21 DVDD Digital Power Supply Pin, 1.6 ~1.98V 22 HPL O Lch Headphone Amplifier Output Pin 23 HPR O Rch Headphone Amplifier Output Pin Charge-Pump Circuit Negative Voltage Output Pin 24 VEE O This pin must be connected to VSS2 with 2.2μF±50% capacitor in series. 25 VSS2 Ground 2 Pin Positive Charge-Pump Capacitor Terminal Pin 26 CP O This pin must be connected to CN pin with 2.2μF±50% capacitor in series. Negative Charge-Pump Capacitor Terminal Pin 27 CN I This pin must be connected to CP pin with 2.2μF±50% capacitor in series. 27 AVDD Analog Power Supply Pin, 2.5 ~ 3.5V 29 VSS1 Ground 1 Pin Common Voltage Output Pin 30 VCOM O Bias voltage of ADC inputs and DAC outputs. This pin must be connected to VSS1 with 2.2μF±50% capacitor in series. Microphone Power Supply Ripple Filter Pin 31 MRF O This pin must be connected to VSS1 with 2.2μF±50% capacitor in series. 32 RIN3 I Rch Analog Input 3 Pin Note 2. All input pins except analog input pins (LIN1, RIN1, LIN2, RIN2, LIN3, RIN3) must not be allowed to float. MS1542-E-00-PB 2013/06 -6- [AK4954A] ■ Handling of Unused Pin The unused I/O pins must be connected appropriately. Classification Pin Name MPWR1, MPWR2, MRF, SPN, SPP, HPL, HPR, Analog CP, CN, VEE, LIN1/DMDAT, RIN1/DMCLK, LIN2, RIN2, LIN3, RIN3 MCKI/OVF Digital SDTI SDTO Setting Open. Connect to VSS2 and set OVFL bit = “0”. Connect to VSS2 Open ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=0V; Note 3) Parameter Symbol min max Unit Power Supplies: Analog AVDD 6.0 V −0.3 Digital DVDD 2.5 V −0.3 Digital I/O TVDD 6.0 V −0.3 Speaker Amplifier SVDD 6.0 V −0.3 Input Current, Any Pin Except Supplies IIN mA ±10 Analog Input Voltage (Note 5) VINA AVDD+0.3 V −0.3 Digital Input Voltage (Note 6) VIND TVDD+0.3 V −0.3 Ambient Temperature (powered applied) Ta 85 −30 °C Storage Temperature Tstg 150 −65 °C Maximum Power Dissipation (Note 7) Pd 900 mW Note 3. All voltages are with respect to ground. Note 4. VSS1, VSS2 and VSS3 must be connected to the same analog ground plane. Note 5. LIN1, RIN1, LIN2, RIN2, LIN3, RIN3 pins Note 6. PDN, SCL, SDA, SDTI, LRCK, BICK and MCKI pins Pull-up resistors at SDA and SCL pins should be connected to (TVDD+0.3)V or less voltage. Note 7. This power is the AK4954A internal dissipation that does not include power dissipation of externally connected speakers. The maximum junction temperature is 125°C and θja (Junction to Ambient) is 42°C/W at JESD51-9 (2p2s). When Pd =900mW and the θja is 42°C/W, the junction temperature does not exceed 125°C. In this case, there is no case that the AK4954A is damaged by its internal power dissipation. Therefore, the AK4954A should be used in the condition of θja ≤ 42°C/W. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. MS1542-E-00-PB 2013/06 -7- [AK4954A] RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3= 0V; Note 3) Parameter Symbol min typ max Unit Power Supplies Analog AVDD 2.5 3.3 3.5 V (Note 8) Digital DVDD 1.6 1.8 1.98 V 1.6 or Digital I/O (Note 9) TVDD 1.8 3.5 V (DVDD-0.2) SPK Amplifier SVDD 0.9 3.3 5.5 V Note 3. All voltages are with respect to ground. Note 8. The power-up sequence between AVDD, DVDD, TVDD and SVDD is not critical. The PDN pin must be “L” upon power-up, and should be changed to “H” after all power supplies are supplied to avoid an internal circuit error. Note 9. The minimum value is higher voltage between DVDD-0.2V and 1.6V. * When SVDD is powered ON and the PDN pin is “L”, AVDD, DVDD or TVDD can be powered ON/OFF. When TVDD is powered ON and the PDN pin is “L”, AVDD, DVDD or SVDD can be powered ON/OFF. The PDN pin must be set to “H” after all power supplies are ON when the AK4954A is powered-up from power-down state. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1542-E-00-PB 2013/06 -8- [AK4954A] ANALOG CHARACTERISTICS (Ta=25°C; AVDD=SVDD=3.3V, TVDD=DVDD=1.8V; VSS1=VSS2=VSS3=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 24-bit Data; Measurement Bandwidth=20Hz ∼ 20kHz; unless otherwise specified) Parameter min typ max Unit Microphone Amplifier: LIN1, RIN1, LIN2, RIN2, LIN3, RIN3 pins Input Resistance 70 100 140 kΩ Gain MGAIN2-0 bits = “000” +5 +6 +7 dB +12 MGAIN2-0 bits = “001” +13 +14 dB +19 MGAIN2-0 bits = “010” +20 +21 dB +25 MGAIN2-0 bits = “011” +26 +27 dB MGAIN2-0 bits = “1xx” 0 dB Microphone Power Supply: MPWR1, MPWR2 pins Output Voltage (Note 10) 2.51 2.64 2.77 V Output Noise Level (A-weighted) -120 dBV PSRR (fin = 1kHz) (Note 11) 70 dB Load Resistance 1.0 kΩ Load Capacitance 15 pF ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 pins → ADC → Programmable Filter (IVOL=0dB, EQ=ALC=OFF) → SDTO; Cext1 = 1μF, Cext2 = 1nF (Note 12) Resolution 32 Bits (Note 14) 0.237 0.264 0.29 Vpp Input Voltage (Note 13) 2.37 2.64 2.90 Vpp (Note 15) fs=44.1kHz (Note 14) 78 88 dBFS BW=20kHz (Note 15) 88 dBFS S/(N+D) (−1dBFS) (Note 14) 85 dBFS fs=96kHz BW=40kHz (Note 15) 82 dBFS (Note 14) 87 97 dB D-Range (−60dBFS, A-weighted) 100 dB (Note 15) (Note 14) 87 97 dB S/N (A-weighted) 100 dB (Note 15) (Note 14) 80 100 dB Interchannel Isolation 100 dB (Note 15) (Note 14) 0 0.8 dB Interchannel Gain Mismatch 0 0.5 dB (Note 15) PSRR (fin = 1kHz) (Note 11, Note 14) 40 dB Note 10. The output voltage is proportional to AVDD. (typ. 0.8 x AVDD V) Note 11. PSRR is applied to AVDD with 100mpVpp sine wave. Note 12. Measured by the circuit shown below (Figure 2). (Cext2 can also be placed between the input pin and VSS1.) Cext1 Signal Input ADC Input Cext2 Figure 2. ADC Analog Characteristics Measurement Circuit Note 13. The input voltage is proportional to AVDD. typ. 0.8 x AVDD Vpp (0dB), typ. 0.08 x AVDD Vpp (+20dB) Note 14. MGAIN2-0 bits = “010” (+20dB) Note 15. MGAIN2-0 bits = “1xx” (0dB). MS1542-E-00-PB 2013/06 -9- [AK4954A] Parameter min typ max DAC Characteristics: Resolution 32 Headphone Amplifier Characteristics: DAC → HPL, HPR pins, ALC=OFF, IVOL=DVOL= 0dB, RL=16Ω Output Voltage (Note 16) 1.44 1.60 1.76 fs=44.1kHz, 55 65 (RL=16Ω) BW=20kHz S/(N+D) fs=96kHz, BW=40kHz 65 fs=44.1kHz, (RL=10kΩ) 80 BW=20kHz S/N (A-weighted) 90 100 Interchannel Isolation 65 80 Interchannel Gain Mismatch 0 0.8 Output Offset Voltage -1 0 +1 PSRR (fin = 1kHz) (Note 17) 40 Load Resistance 16 Load Capacitance 300 Speaker Amplifier Characteristics: DAC → SPP/SPN pins, ALC=OFF, IVOL=DVOL= 0dB, RL=8Ω, BTL Output Voltage 3.18 SLG1-0 bits = “00”, −0.5dBFS (Po=150mW) 3.20 4.00 4.80 SLG1-0 bits = “01”, −0.5dBFS (Po=250mW) 1.79 SLG1-0 bits = “10”, −0.5dBFS (Po=400mW) SLG1-0 bits = “00”, −1.5dBFS (Po=100mW) 0.9 (Note 18) S/(N+D) 70 SLG1-0 bits = “00”, −0.5dBFS (Po=150mW) 40 70 SLG1-0 bits = “01”, −0.5dBFS (Po=250mW) 20 SLG1-0 bits = “10”, −0.5dBFS (Po=400mW) SLG1-0 bits = “00”, −1.5dBFS (Po=100mW) 20 (Note 18) Output Noise Level -97 -87 (A-weighted, SLG1-0 bits = “01”) Output Offset Voltage -30 0 +30 PSRR (fin = 1kHz) (Note 19) 50 Load Resistance 6.8 8 Load Capacitance 30 Stereo Line Output Characteristics: DAC → LOUT, ROUT pins, ALC=OFF, IVOL=DVOL=SLG= 0dB, RL=10kΩ Output Voltage (Note 20) 2.24 S/(N+D) 74 84 S/N (A-weighted) 84 94 Interchannel Isolation 90 Interchannel Gain Mismatch 0 0.8 Load Resistance 10 Load Capacitance 30 Note 16. The full-scale output voltage is proportional to AVDD. (typ. 0.485 x AVDD Vpp) Note 17. PSRR is applied to AVDD or DVDD with 100mpVpp sine wave. Note 18. When SVDD = 1.5V. Note 19. PSRR is applied to AVDD or SVDD with 100mpVpp sine wave. Note 20. The full-scale output voltage is proportional to AVDD. (typ. 0.68 x AVDD Vpp) MS1542-E-00-PB Unit Bits Vpp dB dB dB dB dB dB mV dB Ω pF Vpp Vpp Vrms Vrms dB dB dB dB dBV mV dB Ω pF Vpp dB dB dB dB kΩ pF 2013/06 - 10 - [AK4954A] Parameter min typ max Unit Beep Output Characteristics: BEEP Generator → HPL, HPR pins, SPP/SPN pins, LOUT, ROUT pins Output Voltage (BPLVL = 0dB) 1.5 Vpp HPL, HPR pins (RL=16Ω) 2.8 Vpp SPP/SPN pins (RL=8Ω, BTL, SLG = +4.26dB) 1.4 Vpp LOUT, ROUT pins (RL=10kΩ, SLG = 0dB) Gain Gain Setting -60 0 dB Step Width 3 dB Power Supplies: Power-up (PDN pin = “H”) MIC + ADC + DAC + Headphone out AVDD+DVDD+TVDD (Note 21) 9.2 13.8 mA AVDD+DVDD+TVDD (Note 22) 8.2 mA SVDD (No Load) 8 12 μA MIC + ADC + DAC + Speaker out AVDD+DVDD+TVDD (Note 23) 8.2 12.3 mA AVDD+DVDD+TVDD (Note 24) 7.2 mA SVDD (No Load) 0.8 1.2 mA Power-down (PDN pin = “L”) (Note 25) AVDD+DVDD+TVDD+SVDD 0 10 μA SVDD (Note 26) 0 10 μA Note 21. When PLL Master Mode (MCKI=12MHz), and PMADL=PMADR=PMDAC=PMPFIL=PMHPL=PMHPR= PMVCM=PMPLL=PMBP=PMMP=M/S bits = “1”, and LPMIC = LPDA bits = “0”. In this case, the MPWR1 (MPWR2) pin outputs 0mA. AVDD= 7.3mA (typ), DVDD= 1.6mA (typ), TVDD= 0.3mA (typ). Note 22. When EXT Slave Mode (PMPLL=M/S bits =“0”), PMADL=PMADR=PMDAC=PMHPL=PMHPR= PMVCM=PMBP=PMMP bits = “1”, and PMPFIL = LPMIC = LPDA bits = “0”. In this case, the MPWR1 (MPWR2) pin outputs 0mA. AVDD= 6.5mA (typ), DVDD= 1.6mA (typ), TVDD= 0.1mA (typ). Note 23. When PLL Master Mode (MCKI=12MHz), and PMADL=PMADR=PMDAC=PMPFIL=PMSL=PMVCM= PMPLL=PMBP=PMMP=M/S bits = “1”, and LPMIC = LPDA bits = “0”. In this case, the MPWR1 (MPWR2) pin outputs 0mA. AVDD= 6.5mA (typ), DVDD= 1.4mA (typ), TVDD= 0.3mA (typ). Note 24. When EXT Slave Mode (PMPLL=M/S bits =“0”), PMADL=PMADR=PMDAC=PMSL=PMVCM= PMBP=PMMP bits = “1”, and PMPFIL = LPMIC = LPDA bits = “0”. In this case, the MPWR1 (MPWR2) pin outputs 0mA. AVDD= 5.7mA (typ), DVDD= 1.4mA (typ), TVDD= 0.1mA (typ). Note 25. All digital input pins are fixed to TVDD or VSS2. Note 26. When AVDD, DVDD, and TVDD are powered OFF. MS1542-E-00-PB 2013/06 - 11 - [AK4954A] ■ Power Consumption on Each Operation Mode PMHPR PMHPL PMADR PMADL PMDAC PMSL Mode PMVCM Conditions: Ta=25°C; AVDD= SVDD=3.3V, TVDD=DVDD=1.8V; VSS1=VSS2=VSS3= 0V; fs=44.1kHz, LPF, HPF, Stereo Separation, 5-band Equalizer, ALC, DRC=OFF (PMPFIL = PMDRC bits = “0”), External Slave Mode, BICK=64fs; LIN1/RIN1 input = No input; SDTI input = No input; Headphone & Speaker & Line output = No load. Power Management Bit AVDD [mA] DVDD [mA] TVDD [mA] All Power-down 0 0 0 0 0 0 0 0 0 0 0.76 0.03 LIN1/RIN1 → ADC (Note 27) 1 0 0 1 1 0 0 2.70 1.54 0.63 0.03 LIN1(Mono)→ADC (Note 27) 1 0 0 1 0 0 0 1.49 0.69 DAC → HP (Note 28) 1 0 1 0 0 1 1 0.01 DAC → SPK 1.44 0.67 1 1 1 0 0 0 0 0.01 (LOSEL bit = “0”) LIN1/RIN1 → ADC (Note 27) 4.07 1.60 0.03 1 0 1 1 1 1 1 & DAC → HP (Note 28) LIN1/RIN1 → ADC (Note 27) 4.03 1.54 0.03 & DAC → SPK 1 1 1 1 1 0 0 (LOSEL bit = “0”) Note 27. Low-power consumption mode (LPMIC bit = “1”). Note 28. Low-power consumption mode (LPDA bit = “1”). Table 1. Power Consumption for Each Operation Mode (typ) MS1542-E-00-PB SVDD [mA] Total Power [mW] 0 0.01 0.01 0.01 0 10.4 6.3 6.2 0.76 8.5 0.01 16.4 0.76 18.6 2013/06 - 12 - [AK4954A] ADC SHARP ROLL-OFF FILTER CHARACTERISTICS (fs=44.1kHz) (Ta = -30 ~ 85°C; AVDD=2.5 ~ 3.5V, DVDD =1.6 ∼ 1.98V, TVDD=(DVDD-0.2) ~ 3.5V, SVDD=0.9 ∼ 5.5V; SDAD bit = “0”) Parameter Symbol min typ max Unit ADC Digital Filter (Decimation LPF): Passband (Note 29) PB 0 18.8 kHz +0.08dB ~ −0.23dB 19.4 kHz −0.74dB 19.9 kHz −1.41dB 22.1 kHz −8.0dB Stopband (Note 29) SB 26.1 kHz Passband Ripple PR dB ±0.16 Stopband Attenuation SA 62 dB Group Delay (Note 30) GD 10.7 1/fs Group Delay Distortion 0 μs ΔGD ADC Digital Filter (HPF): HPFC1-0 bits = “00” Frequency Response FR 3.4 Hz −3.0dB (Note 29) 10 Hz −0.5dB 22 Hz −0.1dB ADC SHARP ROLL-OFF FILTER CHARACTERISTICS (fs=96kHz) (Ta = -30 ~ 85°C; AVDD=2.5 ~ 3.5V, DVDD =1.6 ∼ 1.98V, TVDD=(DVDD-0.2) ~ 3.5V, SVDD=0.9 ∼ 5.5V; SDAD bit = “0”) Parameter Symbol min typ max Unit ADC Digital Filter (Decimation LPF): Passband (Note 29) PB 0 40.9 kHz +0.08dB ~ −0.23dB 42.2 kHz −0.74dB 43.3 kHz −1.41dB 48.0 kHz −8.0dB Stopband (Note 29) SB 56.8 kHz Passband Ripple PR dB ±0.16 Stopband Attenuation SA 62 dB Group Delay (Note 30) GD 10.7 1/fs Group Delay Distortion 0 μs ΔGD ADC Digital Filter (HPF): HPFC1-0 bits = “00” Frequency Response FR 7.4 Hz −3.0dB (Note 29) 21.8 Hz −0.5dB 47.9 Hz −0.1dB Note 29. The passband and stopband frequencies scale with fs (system sampling rate). Each response refers to that of 1kHz. Note 30. A calculating delay time which induced by digital filtering. This time is from the input of an analog signal to the setting of 32-bit data of both channels to the ADC output register. For the signal through the programmable filters (First HPF + 4-band Equalizer + ALC + Equalizer), the group delay is increased 4/fs from the value above if there is no phase change by the IIR filter. MS1542-E-00-PB 2013/06 - 13 - [AK4954A] ADC SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (fs=44.1kHz) (Ta = -30 ~ 85°C; AVDD=2.5 ~ 3.5V, DVDD =1.6 ∼ 1.98V, TVDD=(DVDD-0.2) ~ 3.5V, SVDD=0.9 ∼ 5.5V; SDAD bit = “1”) Parameter Symbol min typ max Unit ADC Digital Filter (Decimation LPF): Passband (Note 33) PB 0 18.8 kHz +0.08dB ~ −0.23dB 19.4 kHz −0.74dB 19.9 kHz −1.41dB 22.1 kHz −8.0dB Stopband (Note 33) SB 26.1 kHz Passband Ripple PR ±0.16 dB Stopband Attenuation SA 61 dB Group Delay (Note 34) GD 4.3 1/fs Group Delay Distortion ±1.8 1/fs ΔGD ADC Digital Filter (HPF): HPFC1-0 bits = “00” Frequency Response FR 3.4 Hz −3.0dB (Note 31) 10 Hz −0.5dB 22 Hz −0.1dB ADC SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (fs=96kHz) (Ta = -30 ~ 85°C; AVDD=2.5 ~ 3.5V, DVDD =1.6 ∼ 1.98V, TVDD=(DVDD-0.2) ~ 3.5V, SVDD=0.9 ∼ 5.5V; SDAD bit = “1”) Parameter Symbol min typ max Unit ADC Digital Filter (Decimation LPF): Passband (Note 33) PB 0 40.9 kHz +0.08dB ~ −0.23dB 42.2 kHz −0.74dB 43.3 kHz −1.41dB 48.0 kHz −8.0dB Stopband (Note 31) SB 56.8 kHz Passband Ripple PR ±0.16 dB Stopband Attenuation SA 61 dB Group Delay (Note 32) GD 4.3 1/fs Group Delay Distortion ±1.3 1/fs ΔGD ADC Digital Filter (HPF): HPFC1-0 bits = “00” Frequency Response FR 7.4 Hz −3.0dB (Note 31) 21.8 Hz −0.5dB 47.9 Hz −0.1dB Note 31. The passband and stopband frequencies scale with fs (system sampling rate). Each response refers to that of 1kHz. Note 32. A calculating delay time which induced by digital filtering. This time is from the input of an analog signal to the setting of 32-bit data of both channels to the ADC output register. For the signal through the programmable filters (First HPF + 4-band Equalizer + ALC + Equalizer), the group delay is increased 4/fs from the value above if there is no phase change by the IIR filter. MS1542-E-00-PB 2013/06 - 14 - [AK4954A] DAC FILTER CHARACTERISTICS (fs=44.1kHz) (Ta = -30 ~ 85°C; AVDD=2.5 ~ 3.5V, DVDD =1.6 ∼ 1.98V, TVDD=(DVDD-0.2) ~ 3.5V, SVDD=0.9 ∼ 5.5V) Parameter Symbol min typ max Unit DAC Digital Filter (LPF): Passband (Note 33) PB 0 20.0 kHz ±0.05dB 22.05 kHz −6.0dB Stopband (Note 33) SB 24.1 kHz Passband Ripple PR ±0.05 dB Stopband Attenuation SA 54 dB Group Delay (Note 34) GD 22 1/fs DAC Digital Filter (LPF) + SCF: FR ±1.0 dB Frequency Response: 0 ∼ 20.0kHz (Note 33) DAC FILTER CHARACTERISTICS (fs=96kHz) (Ta = -30 ~ 85°C; AVDD=2.5 ~ 3.5V, DVDD =1.6 ∼ 1.98V, TVDD=(DVDD-0.2) ~ 3.5V, SVDD=0.9 ∼ 5.5V) Parameter Symbol min typ max Unit DAC Digital Filter (LPF): Passband (Note 33) PB 0 43.5 kHz ±0.05dB 48.0 kHz −6.0dB Stopband (Note 33) SB 52.5 kHz Passband Ripple PR ±0.05 dB Stopband Attenuation SA 54 dB Group Delay (Note 34) GD 22 1/fs DAC Digital Filter (LPF) + SCF: FR ±1.0 dB Frequency Response: 0 ∼ 40.0kHz (Note 33) Note 33. The passband and stopband frequencies scale with fs (system sampling rate). Each response refers to that of 1kHz. Note 34. A calculating delay time which induced by digital filtering. This time is from setting the 32-bit data of both channels to input register to the output of analog signal. For the signal through the programmable filters (First HPF + 4-band Equalizer + ALC + Equalizer), the group delay is increased 7/fs from the value above if there is no phase change by the IIR filter. MS1542-E-00-PB 2013/06 - 15 - [AK4954A] DC CHARACTERISTICS (Ta = -30 ~ 85°C; AVDD=2.5 ~ 3.5V, DVDD =1.6 ∼ 1.98V, TVDD=(DVDD-0.2) ~ 3.5V, SVDD=0.9 ∼ 5.5V) Parameter Symbol min typ max Audio Interface & Serial µP Interface (SDA, SCL, PDN, BICK, LRCK, SDTI, MCKI pins ) High-Level Input Voltage (TVDD ≥ 2.2V) VIH 70%TVDD (TVDD < 2.2V) 80%TVDD Low-Level Input Voltage (TVDD ≥ 2.2V) VIL 30%TVDD (TVDD < 2.2V) 20%TVDD Audio Interface & Serial µP Interface (SDA, BICK, LRCK, SDTO, OVF pins Output) VOH High-Level Output Voltage (Iout = −80μA) TVDD−0.2 Low-Level Output Voltage 0.2 (Except SDA pin : Iout = 80μA) VOL1 0.4 (SDA pin, 2.0V ≤ TVDD ≤ 3.5V: Iout = 3mA) VOL2 20%TVDD (SDA pin, 1.6V ≤ TVDD < 2.0V: Iout = 3mA) VOL2 Input Leakage Current Iin ±10 Digital Microphone Interface (DMDAT pin Input ; DMIC bit = “1”) High-Level Input Voltage VIH3 65%AVDD Low-Level Input Voltage VIL3 35%AVDD Sink Current (Vin = AVDD) Isink 150 Source Current (Vin = 0V) Isource -20 Digital Microphone Interface (DMCLK pin Output ; DMIC bit = “1”) VOH3 AVDD-0.4 High-Level Output Voltage (Iout=−80μA) VOL3 0.4 Low-Level Output Voltage (Iout= 80μA) Input Leakage Current Iin ±10 MS1542-E-00-PB Unit V V V V V V V V μA V V μA μA V V μA 2013/06 - 16 - [AK4954A] SWITCHING CHARACTERISTICS (Ta = -30 ~ 85°C; AVDD=2.5 ~ 3.5V, DVDD =1.6 ∼ 1.98V, TVDD=(DVDD-0.2) ~ 3.5V, SVDD=0.9 ∼ 5.5V; CL=20pF) Parameter Symbol min typ max Unit PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 27 MHz Pulse Width Low tCLKL 0.4/fCLK ns Pulse Width High tCLKH 0.4/fCLK ns LRCK Output Timing Frequency fs 8 96 kHz Duty Cycle Duty 50 % BICK Output Timing Period BCKO bit = “0” tBCK 1/(32fs) ns BCKO bit = “1” tBCK 1/(64fs) ns Duty Cycle dBCK 50 % PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs 8 96 kHz Duty Duty 45 55 % BICK Input Timing Period PLL2-0 bits = “000” tBCK 1/(32fs) ns PLL2-0 bits = “001” tBCK 1/(64fs) ns Pulse Width Low tBCKL 0.4 x tBCK ns Pulse Width High tBCKH 0.4 x tBCK ns MS1542-E-00-PB 2013/06 - 17 - [AK4954A] Parameter External Slave Mode MCKI Input Timing Frequency 256fs 384fs 512fs 1024fs Pulse Width Low Pulse Width High LRCK Input Timing Frequency 256fs 384fs 512fs 1024fs Duty BICK Input Timing Period Pulse Width Low Pulse Width High External Master Mode MCKI Input Timing Frequency 256fs 384fs 512fs 1024fs Pulse Width Low Pulse Width High LRCK Output Timing Frequency Duty Cycle BICK Output Timing Period BCKO bit = “0” BCKO bit = “1” Duty Cycle MS1542-E-00-PB Symbol min typ max Unit fCLK fCLK fCLK fCLK tCLKL tCLKH 2.048 3.072 4.096 8.192 0.4/fCLK 0.4/fCLK - 24.576 18.432 24.576 12.288 - MHz MHz MHz MHz ns ns fs fs fs fs Duty 8 8 8 8 45 - 96 48 48 12 55 kHz kHz kHz kHz % tBCK tBCKL tBCKH 156.25 65 65 - - ns ns ns fCLK fCLK fCLK fCLK tCLKL tCLKH 2.048 3.072 4.096 8.192 0.4/fCLK 0.4/fCLK - 24.576 18.432 24.576 12.288 - MHz MHz MHz MHz ns ns fs Duty 8 - 50 96 - kHz % tBCK tBCK dBCK - 1/(32fs) 1/(64fs) 50 - ns ns % 2013/06 - 18 - [AK4954A] Parameter Symbol min typ Audio Interface Timing Master Mode tMBLR −20 BICK “↓” to LRCK Edge (Note 35) tLRD LRCK Edge to SDTO (MSB) −35 (Except I2S mode) tBSD BICK “↓” to SDTO −35 SDTI Hold Time tSDH 25 SDTI Setup Time tSDS 20 Slave Mode tLRB 25 LRCK Edge to BICK “↑” (Note 35) tBLR 25 BICK “↑” to LRCK Edge (Note 35) tLRD LRCK Edge to SDTO (MSB) (Except I2S mode) tBSD BICK “↓” to SDTO SDTI Hold Time tSDH 25 SDTI Setup Time tSDS 20 Control Interface Timing (I2C Bus Mode): (Note 36) SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 37) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Capacitive Load on Bus Cb Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 Note 35. BICK rising edge must not occur at the same time as LRCK edge. Note 36. I2C-bus is a trademark of NXP B.V. Note 37. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. MS1542-E-00-PB max Units 20 35 ns ns 35 - ns ns ns 45 ns ns ns 45 - ns ns ns 400 0.3 0.3 400 50 kHz μs μs μs μs μs μs μs μs μs μs pF ns 2013/06 - 19 - [AK4954A] Parameter Symbol min typ max Unit Digital Audio Interface Timing; fs = 8kHz ~ 48kHz, CL=100pF DMCLK Output Timing Period tSCK 1/(64fs) ns Rising Time tSRise 10 ns Falling Time tSFall 10 ns Duty Cycle dSCK 40 50 60 % Audio Interface Timing DMDAT Setup Time tSDS 50 ns DMDAT Hold Time tSDH 0 ns Power-down & Reset Timing PDN Accept Pulse Width (Note 38) tAPD 1 μs PDN Reject Pulse Width (Note 38) tRPD 50 ns (Note 39) PMADL or PMADR “↑” to SDTO valid ADRST1-0 bits = “00” tPDV 2115 1/fs ADRST1-0 bits = “01” tPDV 4227 1/fs ADRST1-0 bits = “10” tPDV 267 1/fs ADRST1-0 bits = “11” tPDV 1059 1/fs (Note 40) PMDML or PMDMR “↑” to SDTO valid ADRST1-0 bits = “00” tPDV 2115 1/fs ADRST1-0 bits = “01” tPDV 4227 1/fs ADRST1-0 bits = “10” tPDV 267 1/fs ADRST1-0 bits = “11” tPDV 1059 1/fs Note 38. The AK4954A can be reset by bringing the PDN pin “L” upon power-up. The PDN pin must held “L” for more than 1µs for a certain reset. The AK4954A is not reset by the “L” pulse less than 50ns. Note 39. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”. Note 40. This is the count of LRCK “↑” from the PMDML or PMDMR bit = “1”. ■ Timing Diagram 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs 50%TVDD LRCK tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 Figure 3. Clock Timing (PLL/EXT Master mode) MS1542-E-00-PB 2013/06 - 20 - [AK4954A] 50%TVDD LRCK tMBLR tBCKL BICK 50%TVDD tLRD tBSD SDTO 50%TVDD tSDS tSDH VIH SDTI VIL Figure 4. Audio Interface Timing (PLL/EXT Master mode) 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tBCK VIH BICK VIL tBCKH tBCKL Figure 5. Clock Timing (EXT Slave mode) MS1542-E-00-PB 2013/06 - 21 - [AK4954A] VIH LRCK VIL tLRB tBLR VIH BICK VIL tBSD tLRD SDTO 50%TVDD MSB tSDH tSDS VIH SDTI VIL Figure 6. Audio Interface Timing (PLL/EXT Slave mode) VIH SDA VIL tBUF tLOW tHIGH tR tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA tSU:STO Start Stop Figure 7. I2C Bus Mode Timing tSCK 65%AVDD DMCLK 50%AVDD 35%AVDD tSCKL tSRise tSFall dSCK = 100 x tSCKL / tSCK Figure 8. DMCLK Clock Timing MS1542-E-00-PB 2013/06 - 22 - [AK4954A] 65%AVDD DMCLK 35%AVDD tSDS tSDH VIH3 DMDAT VIL3 Figure 9. Audio Interface Timing (DCLKP bit = “1”) 65%AVDD DMCLK 35%AVDD tSDS tSDH VIH3 DMDAT VIL3 Figure 10. Audio Interface Timing (DCLKP bit = “0”) PMADL bit, PMADR bit, PMDML bit or PMDMR bit tPDV SDTO 50%TVDD Figure 11. Power-down & Reset Timing 1 tAPD tRPD PDN VIL Figure 12. Power-down & Reset Timing 2 MS1542-E-00-PB 2013/06 - 23 - [AK4954A] PACKAGE 32pin QFN 4.0 ± 0.1 B 2.8 ± 0.1 A 17 24 16 4.0 ± 0.1 2.8 ± 0.1 25 Exposed Pad 32 9 8 0.40 0.55 0.20 0.10 C 0.20 ± 0.05 0.10 M C A B 0.75 ± 0.05 0.35 ± 0.1 C C0.35 1 (Unit: mm) Note: The exposed pad on the bottom surface of the package must be connected to the ground. ■ Material & Lead finish Package molding compound: Epoxy Resin, Halogen (Br and Cl) free Lead frame material: Cu Alloy Lead frame surface treatment: Solder (Pb free) plate MS1542-E-00-PB 2013/06 - 24 - [AK4954A] MARKING 4954A XXXX 1 XXXX: Date code (4 digit) Pin #1 indication REVISION HISTORY Date (Y/M/D) 13/06/07 Revision 00 Reason First Edition Page/Line Contents MS1542-E-00-PB 2013/06 - 25 - [AK4954A] Thank you for your access to AKM product information. More detail product information is available, please contact our sales office or authorized distributors. IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. MS1542-E-00-PB 2013/06 - 26 -