[AK7754] AK7754 Audio DSP with Stereo CODEC + MIC/HP-AMP GENERAL DESCRIPTION The AK7754 is a highly integrated audio digital signal processor (DSP) with two Audio I/F’s, Microphone and Headphone Amplifier. The audio DSP has 1536step/fs (at 48KHz sampling) parallel processing power, and AKM’s original Hands-free technology provides high performance noise and echo cancelling. The 96k-bit delay memory allows surround processing, acoustic effect and parametric equalizers. As the AK7754 is a RAM based DSP, it is programmable for user requirements. The internal SRC has various sampling rate converting modes, corresponds many sampling rates without changing the DSP operating sampling frequency. The AK7754 is available in a space saving small 48pin QFN package. FEATURES □ DSP Block - Word length: 24bit (Coefficient RAM & Data RAM: F24 floating point) - Processing Speed: 13.6 ns (1536step/fs fs=48kHz; 9216step/fs fs=8kHz) - Multiplication: 20 x 16 → 36-bit Double precision arithmetic available - Divider 20 / 20 → 20bit - ALU: 40bit arithmetic operation (overflow margin 4bit) 24bit floating point arithmetic and logic operation - Program RAM: 2048 x 36bit - Coefficient RAM: 2048 x 16bit (F24 floating point) - Data RAM: 512 x 24-bit (F24 floating point) - Offset Register: 32 x 12bit - Delay RAM1: 3072 x 24bit - Delay RAM2: 2048 x 12bit - Sampling rate: fs= 8.0k ~ 48kHz - Master/Slave Operation - Master Clock: 1536fs (generated from 32fs, 48fs, 64fs, 128fs, 256fs, 384fs by internal PLL) □ Two Digital Interfaces (I/F 1, I/F 2) - Digital Signal Input Port (4ch) MSB justified 24bit/LSB justified 24/20/16bit and I2S - Digital Signal Input Port (6ch) MSB justified 24bit/ LSB justified 20/16bit and I2S - Short / Long Frame -24 bit linear, 8 bit A-law, 8 bit µ-law □ Stereo 24bit ADC Block - Sampling rate: 8 ~ 48kHz - ADC Characteristics S/(N+D): 82dB ,DR, S/N: 89dB - Three Analog Input Selectors (Differential, Single-ended Inputs) - Channel Independent MIC, Analog Line Gain Amp (0dB, 9dB~27dB, 3dBstep) - Channel Independent Digital Volume (24dB ~ -103dB, 0.5dB Step, Mute) - Integrated DC offset canceling High Pass Filter □ Digital Microphone I/F MS1138-E-02-PB - 1 - 2012/05 [AK7754] □ Stereo 24bit DAC - Sampling rate: 8 ~ 48kHz - Digital Volume (12dB~-115dB, 0.5dB Step, Mute) - Digital De-emphasis Filter (tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz) □ Line Outputs - Single-ended or Differential Outputs - S/(N+D): 91dB ,DR, S/N: 96dB - Stereo Analog Volume (+0 ~ -28dB, 2.0dB Step, Mute) □ Stereo Headphone Amplifier with a Volume Control - Rated Output Power: 27mW/ch @16Ω - S/(N+D): 70dB , S/N: 89dB - Stereo Analog Volume (+0 ~ -50dB,1.0/2.0/4.0dB Step, Mute) - Click Noise Free at Power ON/OFF □ SRC Block - 2ch x 1 system - Input Sampling Frequency: 8kHz ~ 96kHz - Output Sampling Frequency: 8kHz ~ 48kHz □ Analog Bypass Mode - Bypass Amplifier (0dB~-21dB, 3dB step) □ Output Mixer □ μP Interface: I2C Bus (400KHz Fast-Mode) □ Power Supply Analog Digital1 Digital2 HP-Amp AVDD: 3.0V ~ 3.6V (typ.3.3V) DVDD: 3.0V ~ 3.6V (typ.3.3V) DVDD18: 1.7V ~ 1.9V (typ.1.8V) HVDD: 3.0V ~ 3.6V (typ.3.3V) □ Operating temperature range: -20°C ~ 85°C □ Package: 48pin QFN (0.5mm pitch) MS1138-E-02-PB - 2 - 2012/05 [AK7754] ■ Block Diagram VCOM MPRF MPWR IN1L/IN1P IN2L/IN1N MIC POWER PMMP VREF BPSL 0 1 BPSR 0 1 AINL 1 0 AINR PMMICL IN1L/IN1P IN2L MICL pull down PMPSL 1 0 PMPSR PMLOL IN1N IN3L IN3L/DMCLK IN3R IN3R/DMDAT IN1R/IN2P IN2R/IN2N PMLINL LINL Line PMADL/R PMDAL/R ADC DAC Line OUTR/OUTN PMLOR DAL PMHPL DAR PMMICR DIGMIC IF MICR HPL HP DMCLK DMDAT LRCKO BICKO CLKO HVCOM PMHPR LRCKOE SDOUTAD BICKOE HPR HP CLKOE MLRCLK0 MBITCLK0 MCLK0 MDSPCLK0 XTO XTI 2 3 AVDD DVDD DVDD18 VSS OUTL/OUTP PMLINR LINR IN1R/IN2P IN2R IN2N HVDD Open Drain CLKGEN & CONT LFLT INITRSTN TEST1 BICK1/JX1 LRCK1/JX0 DIN3 DOUT3 3 2 1 0 SELDAI[1:0] SELJX2 1 0 1 0 SELJX 1 0 JX2E JX2 JX1E GP0 JX1 JX0E SELDOM[1:0] 3 2 1 0 MICIF OUTME SELSON 1 0 RDY/SDOUTM SO/RDY TEST2 CAD1 SCL CAD0 SDA SRCBICKO SRCLRCKO LRCK2/JX0 DSP SRCLFLT SDIN2/JX2 0 1 RDY SO JX0 SRC BICK2/JX1 SELMN SRCI UNLOCK SRCO PMSRC 0 1 WDT WDTEN LOCKE DIN2 GP1 SELDI2 DOUT2 SELDO2[1:0] 3 OUT2E 2 1 0 STO SDOUT2 SELDO1[1:0] IRPT SDIN1/JX2 DIN1 DOUT1 3 2 1 0 OUT1E SDOUT1 PMDSP Figure 1. Block Diagram MS1138-E-02-PB - 3 - 2012/05 [AK7754] ■ DSP Block Diagram CP0,CP1 DLP0,DLP1 DP0,DP1 DLRAM DRAM 512w x 24-Bit 512w x 24-Bit CRAM 2048w x 16-Bit OFREG 32w x 12-Bit 3072w x 24-Bit 2048w x 12-Bit CBUS(16-Bit) DBUS(24-Bit) MPX16 Micon I/F MPX20 X Control PRAM DEC Y Serial I/F 2048w x 36-Bit Multiply 16 x 20 → 36-Bit PC Stack: 5level(max) TMP 12 x 24-Bit 24-Bit 36-Bit PTMP(LIFO) 6 x 24-Bit MUL DBUS SHIFT 40-Bit 40-Bit A B 2 x 24,16-Bit ALU DIN3 (ADC) 2 x 24,20,16-Bit DIN2 (SRC) 40-Bit Overflow Margin: 4-Bit 2 x 24,20,16-Bit DIN1 40-Bit DR0 ∼ 3 40-Bit Over Flow Data Generator Division 20÷20→20 MS1138-E-02-PB 2 x 24,20,16-Bit DOUT3 (DAC) 2 x 24,20,16-Bit DOUT2 2 x 24,20,16-Bit DOUT1 Peak Detector - 4 - 2012/05 [AK7754] ■ Ordering Guide AK7754EN AKD7754 -20 ∼ +85°C 48pin QFN (0.5mm pitch) Evaluation Board for AK7754 42 43 44 45 46 47 48 5 24 23 22 21 RDY/SDOUTM RDY SDA SCL 20 19 18 17 CAD0 CAD1 LRCK2/JX0 BICK2/JX1 16 15 SDIN2/JX2 SDOUT2 14 13 SDOUT1 CLKO TEST2 INIT RSTN STO 28 27 26 25 LRCKO XTO XTI DVDD LFLT TEST1 MS1138-E-02-PB VSS2 DVDD Top View 1 2 3 4 IN2R/IN2N IN2L/IN1N IN3R/DMDAT IN3L/DMCLK AK7754EN 11 12 41 BICKO MPRF MPWR IN1R/IN2P IN1L/IN1P 9 10 39 40 BICK1/JX1 LRCK1/JX0 VSS4 VCOM VSS1 DVDD18 SD IN1/JX2 37 38 5 6 7 8 OUTL/OUTP AVDD 29 VSS3 SRCLFLT HPR HVDD HVCOM 36 35 34 33 32 31 30 OUTR/OUTN HPL ■ Pin Layout (TBD) 2012/05 [AK7754] PIN FUNCTION No. Name I/O 1 LFLT O 2 TEST1 I 3 XTO O 4 XTI I DVDD VSS1 DVDD18 JX2 8 SDIN1 JX1 9 BICK1 JX0 10 LRCK1 I I I I 11 BICKO O 12 LRCKO O 13 CLKO O 14 SDOUT1 O 15 SDOUT2 O JX2 SDIN2 JX1 17 BICK2 I I I I 5 6 7 16 MS1138-E-02-PB I Function PLL RC component connect pin Connect a capacitor and resistor between this pin and VSS4. This pin outputs “L” during initial reset. Test1 Pin (Internal pull-down) This pin must be connected to VSS1. Crystal oscillator output pin When a crystal oscillator is used, connect it between XTI and XTO. When an external clock is used, leave this pin open. During initial reset, the output of this pin is Hi-Z. Crystal oscillator input pin/ Master Clock input Connect a crystal oscillator between this pin and the XTO pin, or input an external clock to the XTI pin. When CKM[2:0] bits= 0h, 1h, 2h, input “L” to this pin. Power Supply for Digital Section 3.0V ~ 3.6V Ground Pin 0V Digital Power Supply Pin 1.7V~1.9V Conditional Jump Pin2 (JX2E bit = “1”) Serial Data Input Pin1 Conditional Jump Pin1 (JX2E bit = “1”) Serial Bit Clock Input Pin1 Conditional Jump Pin0 (JX2E bit = “1”) LR Channel Select Clock Pin1 Serial Bit Clock Output Pin (BICKOE bit = “1”) Outputs “L” during initial reset in master mode. LR Channel Select Clock Pin (LRCKOE bit = “1”) Outputs “L” during initial reset in master mode. Clock Output Pin (CLKOE bit = “1”) Outputs “L” during initial reset in master mode. Serial Data Output Pin1 Outputs “L” during initial reset in master mode. Serial Data Output Pin2 Outputs “L” during initial reset in master mode. Conditional Jump Pin2 (JX2E bit = “1”) Serial Data Input Pin2 Conditional Jump Pin1 (JX2E bit = “1”) Serial Bit Clock Input Pin2 (for SRC) 6 Classification Analog Output Test System Clcok Digital Power Supply Conditional Input Data I/F Conditional Input Data I/F Conditional Input Data I/F System Clock Output System Clock Output System Data I/F Data I/F Conditional Input Data I/F Conditional Input Data I/F 2012/05 [AK7754] No. Name I/O JX0 I LRCK2 19 CAD1 20 CAD0 21 SCL I I I I 18 22 SDA I/O 23 RDY O RDY O SDOUTM O 24 25 STO O 26 INITRSTN I 27 TEST2 I 28 DVDD - 29 VSS2 - 30 SRCLFLT O 31 VSS3 - 32 HVCOM O 33 HVDD - 34 HPR 35 HPL O O OUTR O OUTN O OUTL O OUTP O 38 AVDD - 36 37 MS1138-E-02-PB Function Classification Conditional Jump Pin0 (JX0E bit = “1”) A conditional jump pin (JX0) is available by setting control register (JX0E) Conditional Input to “1” when SCKSEK bit = “1”. LR Channel Select Clock Pin2 (for SRC) Data I/F 2 I C Bus Address Pin1 I2C Bus Address Pin0 I2C I2C Bus Interface I2C Bus Clock Outputs “Hi-z” during initial reset. Data Write Ready Output Pin for Microprocessor Interface Microprocessor I/F Data Write Ready Output Pin for Microprocessor Interface (SELM bit= “0”) Microprocessor I/F Serial Data Monitering Selector Output Pin (SELM bit= “0”) Outputs “L” during initial reset. Status Output Pin Status Outputs “H” during initial reset. Initial Reset Pin Use to initialize the AK7754. This pin must be “L” when power up the Reset AK7754. Test2 Pin Test This pin must be connected to DVDD. Digital Power Supply for Digital Section 3.0V ~ 3.6V Power Supply Digital Ground Pin 0V Power Supply SRC, PLL RC component connect pin Connect a 1μF capacitor between this pin and VSS2. This pin outputs “L” Analog Output during initial reset. Analog Ground Pin 0V Power Supply Headphone Common Voltage Output Pin Connect a of 1μF cap to VSS3. Do not use for an outside circuits. Outputs Headphone “L” during initial reset. Analog Headphone Power Supply Pin 3.0V~3.6V Power Supply Headphone Rch Output Pin Analog Output Outputs “L” during initial reset Headphone Lch Output Pin Analog Output Outputs “L” during initial reset DAC Rch Output Pin (LODIF bit= “0”) Outputs “L” during initial reset Analog Output Inverted Line Output Pin (LODIF bit= “1”) Outputs “L” during initial reset DAC Lch Output Pin (LODIF bit= “0”) Outputs “L” during initial reset Analog Output DAC Non-inverted differential Analog Output Pin (LODIF bit= “1”) Outputs “L” during initial reset Analog Analog Power Supply Pin 3.0V~3.6V Power Supply 7 2012/05 [AK7754] No. Name 39 VSS4 I/O Function Classification Analog Power Supply - Ground Pin 0V Analog common voltage Connect 0.1μF and 2.2μF capacitors in parallel to VSS4. Never to use for an external circuit. Outputs “L” during initial reset Ripple Filter Pin for Microphone Power Supply 41 MPRF O Connect a 1uF capacitor between this pin and VSS4. Power Supply Pin for Microphone 42 MPWR O Outputs “Hi-Z” during initial reset (MDIFR bit = “0”) IN1R I Rch Single-end Input Pin1 43 (MDIFR bit = “1”) IN2P I MIC Differential Non-Inverted Input Pin2 IN1L I Lch Single-end Input Pin1 (MDIFL bit = “0”) 44 IN1P I MIC Differential Non-inverted Input Pin1 (MDIFL bit = “1”) IN2R I Rch Single-end Input Pin2 (MDIFR bit = “0”) 45 IN2N I MIC Differential Inverted Input Pin2 (MDIFR bit = “1”) (MDIFL bit = “0”) IN2L I Lch Single-end Input Pin2 46 (MDIFL bit = “1”) IN1N I MIC Differential Inverted Input Pin1 (DMIC bit = “0”) IN3R I Rch Single-end Input Pin3 47 (DMIC bit = “1”) DMDAT I Digital Microphone Data Input Pin (DMIC bit = “0”) IN3L I Lch Single-end Input Pin3 48 (DMIC bit = “1”) DMCLK O Digital Microphone Clock pin Note: Do not leave digital input pins open. 40 VCOM O Analog Output Analog Output Analog Output Analog Input Analog Input Analog Input Analog Input Analog Input Digital Microphone Analog Input Digital Microphone ■ Handling of Unused Pin The following table illustrates recommended states for open pins: Classification Analog Digital MS1138-E-02-PB Pin Name IN1L/IN1P,IN1R/IN2P,IN2L/IN1N,IN2R/IN2N,IN3L,IN3R CLKO, BICKO, LRCKO, SDOUT1-2, SDOUTM, STO, SOUTM/RDY,XTO SDIN1, SDIN2, BICK1, BICK2, LRCK1, LRCK2, XTI 8 Setting Leave Open Leave Open Connect to VSS1 2012/05 [AK7754] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=VSS4= 0V: Note 1) Parameter Symbol min max Power Supply Voltage (AVDD=DVDD) Analog AVDD -0.3 4.3 Analog HVDD -0.3 4.3 Digital DVDD -0.3 4.3 Digital DVDD18 -0.3 2.5 Difference(VSS1~4) ΔGND -0.3 0.3 Input Current (except for power supply pin) IIN – ±10 Analog Input Voltage (Note 2) VINA -0.3 (AVDD+0.3) or 4.3 Digital Input Voltage (Note 3) VIND1 -0.3 (DVDD+0.3) or 4.3 Operating Ambient Temperature Ta -20 85 Storage Temperature Tstg -65 150 Note 1. All indicated voltages are with respect to ground. Note 2. VSS1-5 must be connected to the same ground plane. Note 3. The maximum digital input voltage is smaller value between (DVDD+0.3)V and 4.3V. Unit V V V V V mA V V ºC ºC WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3=VSS4=0V: Note 1) Parameter Symbol min typ max Unit Power Supply Voltage Analog AVDD 3.0 3.3 3.6 V Analog HVDD 3.0 3.3 3.6 V Digital DVDD 3.0 3.3 3.6 V Digital DVDD18 1.7 1.8 1.9 V HVDD-AVDD ΔVDD1 -0.3 0 +0.3 V HVDD-DVDD ΔVDD2 -0.3 0 +0.3 V AVDD-DVDD ΔVDD3 -0.3 0 +0.3 V Note 4. The power supply sequence for AVDD, HVDD, DVDD and DVDD18 is not critical but all power supplies must be On before start operating the AK7754. Note 5. Do not turn off the power supply of the AK7754 with the power supply of the surrounding device turned on. DVDD must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for DVDD in the SDA and SCL pins.) WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet. MS1138-E-02-PB 9 2012/05 [AK7754] ANALOG CHARACTERISTICS (CODEC) ■ ADC Characteristics (Ta=25ºC; AVDD=DVDD=HVDD=3.3V, DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V; BICK1=64fs; Signal Frequency 1kHz; Measurement frequency =20Hz~20kHz, fs=48kHz, PMSRC=PMHPL=PMHPR bits=“0”, CKM mode 6 (CKM[2:0]=6h) Unless otherwise specified.) Parameter min typ max Units MIC/LINEIN Amplifier: IN1L,IN1R,IN2L,IN2R,IN3L,IN3R pins Input Resistance 22.5 30 37.5 kΩ Gain Max (MGNL/R2-0, LINL/R2-0 bits = “0H”) 0 dB Min (MGNL/R2-0, LINL/R2-0 bits = “7H”) +27 dB Bypass Amplifier: IN1L,IN1R,IN2L,IN2R,IN3L,IN3R pins (MGNL/R2-0 = 0h, LINL/R2-0 = 0h) Gain Max (BPGL/R2-0 bit = “0H”) 0 dB Min (BPGL/R2-0 bit = “7H”) -21 dB MIC Power Supply: MPWR pin Output Voltage (Note 6) 2.18 2.3 2.4 V Output Current 4 mA Stereo Resolution 24 Bits ADC Dynamic Characteristics IN1L/IN1R, IN2L/IN2R, IN3L/IN3R pins→ stereo ADC→ SDOUT1/2/M (VOLADL/R=30h(0dB) (Note 12) 70 77 dB S/(N+D) (-1dBFS) 74 82 dB (Note 13) (Note 12) 74 82 dB Dynamic Range (A-weight) 81 89 dB (Note 13) (Note 12) 74 82 dB S/N (A-weight) 81 89 dB (Note 13) Inter-Channel Isolation (Note 13) 90 105 dB (fin=1kHz) (Note 7) DC accuracy Channel Gain Mismatch 0.0 0.3 dB Analog Input Differential (Note 12) ±0.098 Vpp Input Voltage (Note 8, Note 10) ±1.0 ±1.1 ±1.2 (Note 13) (Note 12) 0.196 Vpp Single-ended Input Voltage (Note 9, Note 11) 2.0 2.2 2.4 (Note 13) Note 6. The output voltage is proportional to AVDD. Vout=0.76 x AVDD (typ.) Note 7. Inter-channel isolation between IN1-3L and IN1-3R pins when –1dB FS signal is input. Note 8. The input voltage is proportional to AVDD. Vin=±0.030 x AVDD (typ.)@MGNL2-0=MGNR2-0 bits = “5h”(+21dB), Vin=±0.33 x AVDD (typ.) @MGNL2-0=MGNR2-0 bits = “0h”(+0dB) Note 9. The input voltage is proportional to AVDD. Vin=0.059 x AVDD (typ.)@MGNL2-0=MGNR2-0 bits = “5h”(+21dB), Vin=0.67 x AVDD (typ.) @MGNL2-0=MGNR2-0 bits = “0h”(+0dB) Note 10. IN1P, IN1N, IN2P and IN2N pins Note 11. IN1L, IN1R, IN2L, IN2R, IN3L and IN3R pins Note 12. MGNL2-0=MGNR2-0 bits = “5h” (+21dB) Note 13. MGNL2-0=MGNR2-0 bits = “0h” (+0dB) MS1138-E-02-PB 10 2012/05 [AK7754] ■ DAC Characteristics (Ta=25ºC; AVDD=DVDD=HVDD=3.3V, DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V; BICK1=64fs; Signal frequency 1kHz; Measurement frequency=20Hz~20kHz, fs=48kHz, PMSRC=PMHPL=PMHPR bits = “0”, CKM mode 6 (CKM[2:0]=6h, Unless otherwise specified.) Parameter min typ max Unit Resolution 24 Bits Stereo DAC Dynamic Characteristics; Stereo DAC→OUTL/R pins VOLDAL/R=18h(0dB) LODIF=“0” S/(N+D) (0dBFS) 80 91 dB Dynamic Range (A-weight) 88 96 dB S/N (A-weight) 88 96 dB Inter-Channel Isolation (fin=1kHz) (Note 14) 90 110 dB DC accuracy Channel Gain Mismatch 0.0 0.5 dB Analog Volume Characteristics Min 0.0 dB Gain Amount Max 28.0 dB Step width 2.0 dB Analog Output Output Voltage Single-End 2.06 2.17 2.28 Vpp (Note 15) Differential ±2.06 ±2.17 ±2.28 Vpp Load Resistance 10 kΩ Load Capacitance 30 pF Note 14. Inter-channel isolation between Lch and Rch of the DAC. Note 15. Full scale output voltage. The output voltage is proportional to AVDD. Vout=0.67 x AVDD (typ.) MS1138-E-02-PB 11 2012/05 [AK7754] ANALOG CHARACTERISTICS (HP-Amp) (Ta=25ºC; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V; Signal frequency 1kHz; Measurement frequency=20Hz~20kHz@48kHz; PMSRC bit=“0”), RL =16Ω; Circuit External Capacitance: C1=C2=OPEN. CKM mode6, Unless otherwise specified.) Parameter min typ max Units Analog Volume Characteristics Gain Max (HPGL,HPGR[4:0] bits= “1FH”) +0 dB Min (HPGL,HPGR[4:0] bits= “01H”) -50 dB Step width 0.1 1 dB +0dB ∼ -16dB -16dB ∼ -38dB 0.1 2 dB -38dB ∼ -50dB 4 dB Headphone-Amp Characteristics: DAC → HPL/HPR pins, RL=16Ω (Note 16) Output Voltage 1.68 1.87 2.06 Vpp S/(N+D) (-3dBFS) 60 70 dB S/N (A-weighted) 83 89 dB Inter channel Isolation 60 75 dB Inter channel Gain Mismatch 0.0 1.0 dB Load Resistance (RL, Figure 2) 16 Ω Load Capacitance (C1, Figure 2) 30 pF Load Capacitance (C2, Figure 2) 300 pF Note 16. Because of an asynchronous circuit operation, the characteristic may deteriorate when SRC is in operation. Measurement Point HP-Amp HPL pin HPR pin 47μF – + + C1 0.22μF C2 RL 10Ω Figure 2. Headphone Amp Output Circuit MS1138-E-02-PB 12 2012/05 [AK7754] SRC CHARACTERISTICS (Ta=25°C; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V; Signal frequency 1kHz; Measurement frequency= 20Hz~FSO/2) Parameter Symbol min typ max Units Resolution 24 Bits Input Sample Rate FSI 8 96 kHz Output Sample Rate FSO 8 48 kHz THD+N (Input= 1kHz, 0dBFS) FSO/FSI=44.1kHz/48kHz -111 dB FSO/FSI=44.1kHz/96kHz -104 dB FSO/FSI=48kHz/44.1kHz -111 dB FSO/FSI=48kHz/96kHz -111 dB FSO/FSI=48kHz/8kHz -111 -103 dB FSO/FSI=16kHz/48kHz -111 dB FSO/FSI=16kHz/44.1kHz -104 dB FSO/FSI=8kHz/48kHz -111 dB FSO/FSI=8kHz/44.1kHz -78 dB Dynamic Range (Input= 1kHz, -60dBFS) FSO/FSI=44.1kHz/48kHz 112 dB FSO/FSI=44.1kHz/96kHz 112 dB FSO/FSI=48kHz/44.1kHz 112 dB FSO/FSI=48kHz/96kHz 112 dB FSO/FSI=48kHz/8kHz 108 112 dB FSO/FSI=16kHz/48kHz 112 dB FSO/FSI=16kHz/44.1kHz 112 dB FSO/FSI=8kHz/48kHz 112 dB FSO/FSI=8kHz/44.1kHz 112 dB Dynamic Range (Input= 1kHz, -60dBFS, A-weighted) FSO/FSI=44.1kHz/48kHz 115 dB Ratio between Input and Output Sample Rate FSO/FSI 0.167 6 - MS1138-E-02-PB 13 2012/05 [AK7754] DC CHARACTERISTICS (Ta=-20ºC~85ºC; AVDD= HVDD= 3.0V~3.6V; DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V) Parameter Symbol min typ max High level input voltage (Note 17) VIH 80%DVDD Low level input voltage (Note 17) VIL 20%DVDD SCL, SDA High level input voltage VIH 70%DVDD SCL, SDA Low level input voltage VIL 30%DVDD DMDAT High level input voltage VIH 65%DVDD DMDAT Low level input voltage VIL 35%DVDD VOH DVDD-0.4 High level output voltage: Iout=-100μA (Note 18) VOL 0.4 Low level output voltage: Iout=100μA (Note 18) SDA Low level output voltage Iout=3mA VOL 0.4 Input leak current (Note 19) Iin ±10 Input leak current TEST1/2 pin (Note 20) Iid 22 Input leak current XTI pin Iix 26 Note 17. Except for the SCL, SDA pin. Note 18. Except for the SDA pin. The DMCLK pin is included. Note 19. Except for the TEST2 pin, TEST1 pin and XTI pin. Note 20. The TEST1 pin has an internal pull-down device, nominally 150kΩ. Unit V V V V V V V V V μA μA μA POWER CONSUMPTION (Ta=-20ºC ~ 85ºC; AVDD=HVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=VSS3=VSS4=0V, fin=1 KHz, 24 bit, fs=48kHz, BICK1=64fs (CKM mode=4, BITFS mode=0), CODEC (Full-duplex mode, no output loads) and DSP running with programmed that connects DSP DIN3 with DOUT1 and DIN1 with DOUT3. Parameter min typ max Units Power Supplies: (Note 21) Power-Up (IRSTN pin = “H”) CODEC + DSP + LineOut + HP All Circuit Power-up AVDD+DVDD 21 mA AVDD=DVDD=HVDD=3.3V, HVDD 4.8 mA DVDD18=1.8V DVDD18 29 mA Power Consumption 137 mW AVDD+DVDD 22 38 mA AVDD=DVDD=HVDD=3.6V, HVDD 5.0 7.5 mA DVDD18=1.9V DVDD18 31 70 mA Reset (IRSTN pin = “L”), Reset condition (Note 22) AVDD+DVDD+HVDD 1 10 μA DVDD18 3 200 μA Note 21. The actual power consumption of DVDD18 depends on the master clock frequency and the step size of the DSP program. (BITFS bit = “2h” and DSPS bit = “0”) Note 22. All digital input pins must be fixed to Logic High /Low. MS1138-E-02-PB 14 2012/05 [AK7754] DIGITAL FILTER CHARACTERISTICS ■ ADC Block 1. fs=8kHz (Ta=-20ºC~85ºC, AVDD= HVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, VSS1=VSS2=VSS3=VSS4=0V; fs=8 kHz; Note 23) Units Parameter Symbol min typ max Passband (±0.1dB) (Note 24) PB 0 3.15 kHz (-1.0dB) 3.63 kHz (-3.0dB) 3.83 kHz Stopband SB 4.66 kHz Passband Ripple (Note 24) PR ±0.1 dB Stopband Attenuation (Note 25, Note 26) SA 68 dB Group Delay Distortion ΔGD 0 μs Group Deley (Ts=1/fs) GD 16 Ts Note 23. Frequencies of each amplitude characteristics are in proportion to fs (sampling rate). The characteristic of the high pass filter is not included. Note 24. The passband is from DC to 3.15kHz when fs=8kHz. Note 25. The stopband is 4.66kHz to 507.34kHz when fs=8kHz. Note 26. When fs = 8kHz, the analog modulator samples the input signal at 512kHz. 2. fs=48kHz (Ta=-20ºC~85ºC, AVDD=HVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, VSS1=VSS2=VSS3=VSS4=0V; fs=48 kHz; Note 27) Parameter Symbol min typ max Units Passband (±0.1dB) (Note 28) PB 0 18.9 kHz (-0.2dB) 20.0 kHz (-3.0dB) 23.0 kHz Stopband SB 28.0 kHz Passband Ripple (Note 28) PR ±0.04 dB Stopband Attenuation (Note 29,Note 30) SA 68 dB Group Delay Distortion ΔGD 0 μs Group Delay (Ts=1/fs) GD 16 Ts Note 27. Frequencies of each amplitude characteristics are in proportion to fs (sampling rate). Note 28. The passband is from DC to 18.9kHz when fs=48kHz. Note 29. The stopband is 28kHz to 3.044MHz when fs=48kHz. Note 30. When fs = 48kHz, the analog modulator samples the input signal at 3.07MHz. MS1138-E-02-PB 15 2012/05 [AK7754] ■ DAC Block 1. fs=8kHz (Ta=-20ºC ~ 85ºC, AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V; VSS1=VSS2 = VSS3=VSS4=0V; fs=48kHz; DEM1-0 bits= “0”, fs=8kHz; Note 27) Units Parameter Symbol min typ max Passband (±0.05dB) (Note 31) PB 0 3.62 kHz (-6.0dB) 4 kHz Stopband (Note 31) SB 4.37 kHz Passband Ripple PR ±0.01 dB Stopband Attenuation (Ts=1/fs) (Note 32) SA 64 dB Group Delay GD 24 Ts Digital Filter + Analog Filter Amplitude characteristic 20Hz~3.5kHz ±0.5 dB 2. fs=48kHz (Ta=-20ºC ~ 85ºC, AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V; VSS1=VSS2=VSS3=VSS4=0V; fs=48kHz; DEM1-0 bits= “0”, fs=48kHz; Note 27) Parameter Symbol min typ max Unit Digital Filter Passband (±0.05dB) (Note 31) PB 0 21.7 kHz (-6.0dB) 24.0 kHz Stopband (Note 31) SB 26.2 kHz Passband Ripple PR ±0.01 dB Stopband Attenuation SA 64 dB Group Delay (Ts=1/fs) (Note 32) GD 24 Ts Digital Filter + Analog Filter Amplitude characteristic 0~20.0kHz ±0.5 dB Note 31. Pass band and Stop band parameter is related to sampling frequency(fs). PB=0.4535fs (at-0.05dB), SB=0.5465fs. Note 32. The digital filter’s delay is calculated as the time from setting 24-bit data into the input register until an analog signal is output. MS1138-E-02-PB 16 2012/05 [AK7754] SWITCHING CHARACTERISTICS ■ System Clock (Ta= -20ºC ~ 85ºC, AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, VSS1=VSS2=VSS3=VSS4=0V, CL=20pF) Parameter Symbol min typ max Unit XTI CKM[2:0]bits=4h-7h a) with a Crystal Oscillator: CKM[2:0]bits=6h fXTI 11.2896 MHz 12.288 CKM[2:0]bits=7h fXTI 16.9344 MHz 18.432 b) with an External Clock Duty Cycle 40 50 60 % CKM[2:0]bits=4h,6h fXTI 11.0 11.2896 MHz 12.288 12.4 CKM[2:0]bits=5h,7h fXTI 16.5 16.9344 MHz 18.432 18.6 LRCK1 Frequency @SCKSEL bit=0 (Note 33) fs 8 BICK1 Frequency @SCKSEL bit=0 (Note 34) High Level Width tBCLKH 64 Low Level Width tBCLKL 64 Frequency 0.23 3.072 fBCLK LRCK2 Frequency @SCKSEL bit=1 (Note 35) fs 8 BICK2 Frequency @SCKSEL bit=1 (Note 36) High Level Width tBCLKH 64 Low Level Width tBCLKL 64 Frequency fBCLK 0.23 3.072 Note 33. Input LRCK1 frequency is the same as sampling rate (fs). Note 34. When BICLK1 is used as a master clock reference clock, it should be synchronized with LRCK1. Note 35. Input LRCK2 frequency is the same as sampling rate (fs). Note 36. When BICLK2 is used as a master clock reference clock, it should be synchronized with LRCK2. 48 kHz 3.1 48 ns ns MHz KHz 3.1 ns ns MHz ■ SRC Input Clock (Ta= -20ºC ~ 85ºC, AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, VSS1=VSS2=VSS3=VSS4=0V, @SCKSEL bit =“0”) Parameter Symbol min typ max Units fs kHz LRCLKI2 Frequency 8 96 BITCLKI2 Frequency Frequency High Level Width Low Level Width MS1138-E-02-PB fBCLK tBCLKH tBCLKL 0.23 32 32 17 3.072 6.2 MHz ns ns 2012/05 [AK7754] ■ Reset (Ta= -20 ºC ~ 85 ºC, AVDD=HVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1=VSS2=VSS3=VSS4=0V) Parameter Symbol min typ max Units INITRSTN (Note 37) tRST 600 ns Note 37. The INITRSTN pin should be “L” when power up the AK7754. ■ Audio Interface 1) SDIN1/2, SDOUT1/2/M (Ta= -20ºC ~ 85ºC, AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, VSS1=VSS2=VSS3=VSS4=0V, CL=20pF) Parameter Symbol min typ max Unit DSP Section Input SDIN1/2 tBLRD 20 ns Delay Time from BICLK1 “↑” to LRCLK1 SCKSEL bit= “0” (Note 38) tLRBD 20 ns Delay Time from LRCLK1 to BITCLK1 “↑” SCKSEL bit= “0” (Note 39) tBLRD 20 ns Delay Time from BICLK2 “↑” to LRCLK2 SCKSEL bit= “1” (Note 38) tLRBD 20 ns Delay Time from LRCLK2 to BITCLK2 “↑” SCKSEL bit= “1” (Note 39) Serial Data Input Latch Setup Time tBSIDS 80 ns Serial Data Input Latch Hold Time tBSIDH 80 ns SRC Section Input SDIN2 (SCKSEL bit= “1”) Delay Time from BICLK2 “↑” to LRCLK2 (Note 39) tBLRD 20 ns Delay Time from LRCLK2 to BITCLK2 “↑” (Note 39) tLRBD 20 ns Serial Data Input Latch Setup Time tBSIDS 40 ns Serial Data Input Latch Hold Time tBSIDH 40 ns Output SDOUT1, SDOUT2, SDOUTM Delay Time from LRCLK1 to Serial Data Output (Note 40) tLRD 80 ns Delay Time from BICK1 “↓” to Serial Data Output (Note 41) tBSOD 80 ns Delay Time from LRCKO to Serial Data Output (Note 40) tLRD 80 ns Delay Time from BICKO to Serial Data Output (Note 42) tBSOD 80 ns SDIN1/2 →SDOUT1/2 (Note 43) Delay Time from SDIN1/2 to SDOUT1/2 Output tIOD 60 ns Note 38. BITCLKI1 edge must not occur at the same time as LRCLKI1 edge. Note 39. BITCLKI2 edge must not occur at the same time as LRCLKI2 edge. Note 40. Except I2S. Note 41. When BICK1 polarity is reversed, delay time is from BICK1 “↑”. Note 42. When BICK2 polarity is reversed, delay time is from BICK2 “↑”. Note 43. SDIN1 → SDOUT1: SELDO1[1:0] bits= “1h”, OUT1E bit= “1” SDIN2 → SDOUT2: SELDO2[1:0] bits= “1h”, OUT2E bit= “1” MS1138-E-02-PB 18 2012/05 [AK7754] ■ Digital Microphone (DMIC) Switching Characteristics (Ta= -20˚C ~85˚C; AVDD=HVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, VSS1= VSS2= VSS3= VSS4= 0V, CL=100pF) Parameter Symbol min typ max Units DMDAT DMDAT Setup Time tDMDS 50 ns DMDAT Hold Time tDMDH 0 ns DMCLK Frequency fDMCK 0.5 64fs 3.1 MHz Duty Cycle dDMCK 40 50 60 % Rise Time tDMCKR 10 ns Fall Time tDMCKF 10 ns Note 44. Clock frequency is depend on the sampling rate (fs) which is set by CKM[1:0] or DFS[1:0] bits. ■ I2C BUS Interface (Ta= -20ºC ~ 85ºC; AVDD=HVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, VSS1=VSS2=VSS3=VSS4=0V; CL=20pF) Parameter Symbol min typ max Unit I2C Timing SCL clock frequency fSCL 400 KHz Bus Free Time Between Transmissions tBUF 1.3 μs Start Condition Hold Time (prior to first Clock tHD:STA 0.6 μs pulse) Clock Low Time tLOW 1.3 μs Clock High Time tHIGH 0.6 μs Setup Time for Repeated Start Condition tSU:STA 0.6 μs SDA Hold Time from SCL Falling tHD:DAT 0 0.9 μs SDA Setup Time from SCL Rising tSU:DAT 0.1 μs Rise Time of Both SDA and SCL Lines tR 0.3 μs Fall Time of Both SDA and SCL Lines tF 0.3 μs Setup Time for Stop Condition tSU:STO 0.6 μs Pulse Width of Spike Noise Suppressed tSP 0 50 ns by Input Filter Capacitive load on bus Cb 400 pF 2 Note 45. I C-bus is a trademark of NXP B.V. MS1138-E-02-PB 19 2012/05 [AK7754] ■ Timing Diagram 1/fXTI 1/fXTI tXTI=1/fXTI XTI VIH1 VIL1 1/fs ts=1/fs 1/fs LRCK1 VIH1 LRCK2 VIL1 1/fBCLK 1/fBCLK tBCLK=1/fBCLK VIH1 BICK1 BICK2 VIL1 tBCLKH tBCLKL Figure 3. System Clock INITRSTN tRST VIL1 Figure 4. Reset Note 46. The INITRSTN pin must be “L” when power-up/power-down the AK7754. MS1138-E-02-PB 20 2012/05 [AK7754] ■ Audio Interface VIH1 VIL1 LRCK1/2 tBLRD tLRBD VIH1 VIL1 BICK1/2 tBSIDS tBSIDH VIH1 VIL1 SDIN1/2 Figure 5. Audio Interface (DSP Section Slave Mode Input) VIH1 VIL1 LRCK2 tBLRD tLRBD VIH1 VIL1 BICK2 tBSIDS tBSIDH VIH1 VIL1 SDIN2 Figure 6. Audio Interface (SRC Section Input) VIH1 VIL1 LRCK1/2 tLRD VIH1 VIL1 BICK1/2 tLRD tBSOD SDOUT1/2/M tBSOD 50%DVDD Figure 7. Audio Interface (Slave Mode Output) MS1138-E-02-PB 21 2012/05 [AK7754] LRCKO 50%DVDD tMBL tMBL BICKO 50%DVDD tBSIDS tBSIDH VIH1 VIL1 Figure 8. Audio Interface (Master Mode Input) LRCKO 50%DVDD tLRD BICKO 50%DVDD tLRD tBSOD SDOUT1/2/M tBSOD 50%DVDD Figure 9. Audio Interface (Master Mode Output) MS1138-E-02-PB 22 2012/05 [AK7754] ■ Digital Microphone Interface Input Interface tDMCK 65%DVDD 50%DVDD 35%DVDD DMCLK tDMCKL tDMCKR tSFall fDMCK = 1/tDMCK dDMCK = 100 x tDMKL / tDMCK Figure 10. DMCLK Clock Timing DMCLK 50%DVDD tDMDS tDMDH VIH3 DMDAT VIL3 Figure 11. Audio Interface Timing, DCLKP bit = “1”) DMCLK 50%DVDD tDMDS tDMDH VIH3 DMDAT VIL3 Figure 12. Audio Interface Timing, DCLKP bit = “0”) I2C Bus Interface VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA Start Start tSU:STO Stop 2 Figure 13. I C Bus Interface MS1138-E-02-PB - 23 - 2012/05 [AK7754] PACKAGE 48pin QFN (Unit: mm) 7.00±0.10 0.40±0.10 B 5.1 6.75±0.10 7.00±0.10 6.75±0.10 0.23+0.07 -0.05 0.10 A M 0.50 AB C0.60MAX 5.1 C 0.85+0.15 -0.05 0.08 0.02+0.03 -0.02 0.20 C Note: The exposed pad on the bottom surface of the package must be open or connected to the ground. A support lead on each corner is for mounting the exposed pad. They are tied to the exposed pad electrically. ■ Materials and Lead Specification Package: Lead frame: Lead-finish: MS1138-E-02-PB Epoxy, Halogen (bromine and chlorine) free Copper Soldering (Pb free) plate - 24 - 2012/05 [AK7754] MARKING AKM AK7754EN XXXXXXX 48 1 XXXXXXX: Date code identifier (7 digits) REVISION HISTORY Date (Y/M/D) 10/06/01 Revision 00 12/03/23 01 12/05/18 02 MS1138-E-02-PB Reason First Edition Error Correction Page Contents 8 PIN FUNCTION IN2P (No. 43): MIC Differential Inverted Input Pin2 →MIC Differential Non-Inverted Input Pin2 IN2N (No. 45): MIC Differential Non-Inverted Input Pin2 →MIC Differential Inverted Input Pin2 PACKAGE The package drawing was changed. A description was added. Description 24 Addition - 25 - 2012/05 [AK7754] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. 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As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to r esult, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system conta ining it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to fun ction or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Thank you for your access to AKM products information. More detail product information is available, please contact our sales office or authorized distributors. MS1138-E-02-PB - 26 - 2012/05