[AK4220] AK4220 7:3 Audio Switch and 6:3 Video Switch AK4220 7:3 6:3 AV CMOS ON/OFF AK4220 64 LQFP 1. •7 3 • • THD+N: –92dB (@1Vrms) • : 96dB • • ON/OFF • L/R 2. •6 3 • • • • Sync-tip • : 6MHz • S/N: 74dB • 6 (+6dB) Hi-Z 3. • •5 µP I/F (I2C, 4 ) 4. • • • 4.5V ∼ 5.5V 3.0V ∼ 3.6V 186mW 5. Ta = -40 ∼ 85 °C 6. Package : 64pin LQFP MS0627-J-01 2010/09 -1- [AK4220] AV D D 40kΩ (typ) LIN + 1 AV S S 40kΩ (typ) LO U T 1 VCO M 40kΩ (typ) GND1 MU T E T 40kΩ (typ) 40kΩ (typ) R IN + 1 40kΩ (typ) ROUT1 In put #1 LIN + 2 GND2 R IN + 2 MU T E T O utput #1 (s am e circ uit) In put #2 LO U T 2 (s am e circ uit) LIN + 3 GND3 R IN + 3 (s am e circ uit) LIN + 4 GND4 R IN + 4 (s am e circ uit) ROUT2 In put #3 O utput #2 In put #4 LO U T 3 (s am e circ uit) LIN + 5 GND5 R IN + 5 (s am e circ uit) LIN + 6 GND6 R IN + 6 (s am e circ uit) LIN + 7 GND7 R IN + 7 (s am e circ uit) ROUT3 In put #5 O utput #3 In put #6 In put #7 AD ET L R VCO M MU T E T O s cillator B ias ADET R Figure 1. MS0627-J-01 2010/09 -2- [AK4220] VVDD1 VVDD2 VVSS1 Video Drivers VIN1 VVSS2 VVSS3 VIN2 VIN3 VOUT1 +6dB VIN4 VIN5 VIN6 VFB1 VOUT2 +6dB VFB2 VOUT3 +6dB VFB3 Sync DET Sync-tip TEST Clamp DVDD (A/V control) PDN DVSS IICN (open drain) SDA/CDTI Control SCL/CCLK Registers INT Q0 Q1 Q2 PDN Q3 CAD1/CSN Q4 CAD0/CDTO Figure 2. MS0627-J-01 2010/09 -3- [AK4220] ■ −40 ∼ +85°C AK4220 AK4220VQ AKD4220 64pin LQFP (0.5mm pitch) VIN6 33 AVDD 34 R 35 MUTET 36 VCOM 37 AVSS 38 LOUT1 39 ROUT1 40 LOUT2 41 ROUT2 42 LOUT3 43 ROUT3 44 GND1 45 LIN+1 46 RIN+1 47 GND2 48 ■ 49 LIN+2 VIN5 32 50 RIN+2 IICN 31 51 GND3 VIN4 30 52 LIN+3 VVSS1 29 53 RIN+3 VIN3 28 54 GND4 VVDD1 27 56 RIN+4 AK4220 57 GND5 Top View 55 LIN+4 VIN2 26 VVSS3 25 VIN1 24 MS0627-J-01 16 VFB1 15 VOUT1 14 DVSS 13 DVDD 12 Q4 11 Q3 10 Q2 Q1 Q0 8 9 INT TEST 17 7 64 LIN+7 CAD0 VOUT2 18 6 63 GND7 SDA VFB2 19 5 62 RIN+6 SCL VVDD2 20 4 61 LIN+6 CAD1 VOUT3 21 3 60 GND6 PDN VFB3 22 2 59 RIN+5 RIN+7 VVSS2 23 1 58 LIN+5 2010/09 -4- [AK4220] No. 1 2 Pin Name RIN+7 PDN I/O I I Function Rch 7 “L” “H” 7 8 9 10 11 12 CAD1 CSN SCL CCLK SDA CDTI CAD0 CDTO INT Q0 Q1 Q2 Q3 Q4 I I I I I/O I I O O O O O O O 13 DVDD - 14 15 16 17 18 19 DVSS VOUT1 VFB1 TEST VOUT2 VFB2 O I I O I 20 VVDD2 - 10uF 21 22 23 24 25 26 VOUT3 VFB3 VVSS2 VIN1 VVSS3 VIN2 O I I I 3 27 VVDD1 - 10uF 28 29 30 VIN3 VVSS1 VIN4 I I 3 31 IICN I 32 VIN5 I 3 4 5 6 1 (IICN pin = “L”) (IICN pin =“H”) (IICN pin = “L”) (IICN pin = “H”) (IICN pin = “L”) (IICN pin = “H”) 0 (IICN pin = “L”) (IICN pin = “H”) 0( 1( 2( 3( 4( ) ) ) ) ) 10uF 0.1uF DVSS 0.1uF VVSS 0.1uF VVSS 1 1 VVSS 2 2 5V 3 2 0V 1 3 0V 2 5V 1 0V 4 “L”(VVSS “H” (VVDD 5 ): IIC ): 4 MS0627-J-01 2010/09 -5- [AK4220] No. 33 Pin Name VIN6 I/O I 34 AVDD - 35 R O 36 MUTET O Function 6 5V 10uF 12k 1% VCOM O 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Note: AVSS LOUT1 ROUT1 LOUT2 ROUT2 LOUT3 ROUT3 GND1 LIN+1 RIN+1 GND2 LIN+2 RIN+2 GND3 LIN+3 RIN+3 GND4 LIN+4 RIN+4 GND5 LIN+5 RIN+5 GND6 LIN+6 RIN+6 GND7 LIN+7 O O O O O O I I I I I I I I I I I I I I I I I I I I AVSS AVSS ) 0.1uF AVSS AVSS 2 1uF 1 (Figure 3 37 0.1uF 2.2uF Lch Rch Lch Rch Lch Rch 0V 1 1 2 2 3 3 1 Lch Rch 1 1 2 Lch Rch 2 2 3 Lch Rch 3 3 4 Lch Rch 4 4 5 Lch Rch 5 5 6 Lch Rch 6 6 7 Lch 7 (PDN,CAD1-0,SCL,SDA pins) AVDD 35kΩ(typ) VCOM 35kΩ(typ) 2.2uF 0.1uF AVSS Figure 3. MS0627-J-01 2010/09 -6- [AK4220] ■ Classification Analog Digital Pin Name LIN+1-LIN+7, RIN+1-RIN+7, LOUT1-LOUT3, ROUT1-ROUT3,VIN1-VIN6, VOU1-VOUT3, VFB1-VFB3, Q0-Q4, INT TEST (AVSS = VVSS1-3 = DVSS = 0V; Note: 1) Parameter Power Supplies Audio Video Video Digital |AVSS-DVSS| (Note: 2) |AVSS-VVSS1| (Note: 2) |AVSS-VVSS2| (Note: 2) |AVSS-VVSS3| (Note: 2) Input Current (any pins except for supplies) Audio Input Voltage (LIN+1-7, RIN+1-7, GND1-7 pins) Video Input Voltage1 (VIN1-6, IICN pins) Video Input Voltage2 (VFB1-3, TEST pins) Digital Input Voltage (PDN, CAD1-0, SCL, SDA pins) Ambient Temperature (power applied) Storage Temperature Note: 1. Note: 2. AVSS, VVSS1-3 , DVSS DVSS Symbol AVDD VVDD1 VVDD2 DVDD ΔGND1 ΔGND2 ΔGND3 ΔGND4 IIN VINA min -0.3 -0.3 -0.3 -0.3 - max 6.0 6.0 6.0 6.0 0.3 0.3 0.3 0.3 Units V V V V V V V V -0.3 ±10 AVDD+0.3 mA V VINV1 -0.3 VVDD1+0.3 V VINV2 -0.3 VVDD2+0.3 V VIND -0.3 DVDD+0.3 V Ta Tstg -40 -65 85 150 °C °C : (AVSS = VVSS1-3 = DVSS = 0V; Note: 1) Parameter Audio Power Supplies Video(Note: 4) (Note: 3) Video(Note: 4) Digital VVDD1 – AVDD VVDD2 – AVDD Symbol AVDD VVDD1 VVDD2 DVDD ΔVDD1 ΔVDD2 min 4.5 4.5 4.5 3.0 -0.3 -0.3 typ 5.0 5.0 5.0 3.3 0 0 max 5.5 5.5 5.5 3.6 +0.3 +0.3 Units V V V V V V Note: 3. AVDD, VVDD1,VVDD2, DVDD Note: 4. VVDD1 VVDD2 : MS0627-J-01 2010/09 -7- [AK4220] ( ) (Ta=25°C; AVDD = VVDD1-2 = 5V, DVDD =3.3V; AVSS = VVSS1-3 = DVSS = 0V; Signal Frequency=1kHz, Measurement Frequency=20Hz∼20kHz, unless otherwise specified) Parameter min typ max Units S/(N+D) Input=0dBV 82 92 dB Input=-60dBV, A-weighted 88 96 dB DR (0dBV ) Input=0ff, A-weighted 88 96 dB S/N (0dBV ) Input Impedance (Note: 5) 20 kΩ Maximum Input Voltage (Note: 6) 1 Vrms Gain -0.5 0 0.5 dB Interchannel Isolation (Note: 7) 100 dB Interchannel Gain Mismatch 0.2 dB Gain Drift 20 ppm/°C Load Resistance (Note: 8) R1+R2 (Figure 4) 5 kΩ 400 pF Load Capacitance C1 (Figure 4) 30 pF C2 (Figure 4) Power Supply Rejection (Note: 9) 50 dB 1kHz (Note: 10) (Note: 11) Note: 5. GND1-7 C Note: 6. S/(N+D)>82dB Note: 7. LIN1-7 RIN1-7 Note: 8. (LOUT1-3, ROUT1-3) Note: 9. AVDD, VVDD1-2, DVDD 1kHz, 50mVpp Note: 10. -31dBV= +40mV0p AVDD 0.008 AVDD V0p(typ) Note: 11. +6dB -6dB -43 - -31 3 -26 - dBV dB (typ) R1 300Ω C3 10uF LOUT1-3 ROUT1-3 R2 4.7kΩ C21 C22 C2=C21+C22= 30pF(max) C1 C1= 400pF(max) Figure 4. Load Resistance R1, R2 and Load Capacitance C1, C2 MS0627-J-01 2010/09 -8- [AK4220] ( ) (Ta=25°C; AVDD = VVDD1-2 = 5V, DVDD =3.3V; AVSS = VVSS1-3 = DVSS = 0V; unless otherwise specified) Parameter Conditions min typ max Units At output pin. 0.6 V Sync Tip Clamp Voltage (Note: 12) Gain (Note: 13) Input=0.3Vp-p, 100kHz 5.5 6 6.5 dB Frequency Response (Note: 13) Input=0.3Vp-p, 100kHz to 6MHz. -1.0 1.0 dB Maximum Input Signal f=100kHz, maximum with distortion < 1.0%, 1.5 Vpp gain=6dB(typ). Load Resistance R1+R2(Note: 14) 150 Ω 400 pF Load Capacitance C1 (Note: 14) 15 pF C2 (Note: 14) Interchannel Isolation (Note: 15) f=4.43MHz, 1Vpp input. 50 dB S/N Reference Level = 0.7Vpp, CCIR 567 74 dB weighting. BW= 15kHz to 5MHz. Differential Gain 0.7Vpp 5steps modulated staircase. % 0.4 chrominance &burst are 280mVpp, 4.43MHz. Differential Phase 0.7Vpp 5steps modulated staircase. Degree 0.9 chrominance &burst are 280mVpp, 4.43MHz. (Note: 16) Note: 12. SAGN bit= “1”, 0.17 AVDD (typ) Note: 13. SAGN bit= “0”, 0.04 0.07 SAGN bit= “0”, 0.1 Vpp AVDD Figure 5 C3 R1 SAGN bit= “1”, DC Note: 14. Figure 5 Figure 6 Note: 15. VIN1-6 Note: 16. AVDD Vpp(typ) AVDD R1 75Ω C3 100uF +6dB VOUT C4 2.2uF R2 75Ω VFB C21 C22 0.014 C23 C1 C2=C21+C22+C23= 15pF(max) C1= 400pF(max) Figure 5. Load Resistance R1, R2 and Load Capacitance C1, C2 (SAGN bit= “0”, ) R1 75Ω +6dB VOUT R2 75Ω VFB C2 C2=15pF(max) C1 C1=400pF(max) Figure 6. Load Resistance R1, R2 and Load Capacitance C1, C2 (SAGN bit= “1”, MS0627-J-01 ) 2010/09 -9- [AK4220] DC (Ta=-40 85°C; AVDD = VVDD1-2 = 4.5∼5.5V, DVDD =3.0∼3.6V) Parameter Symbol min 70%DVDD VIH High-Level Input Voltage (PDN,SCL,SDA,CAD0-1,TEST,IICN pins) VIL Low-Level Input Voltage (PDN,SCL,SDA,CAD0-1,TEST,IICN pins) DVDD-0.4 VOH High-Level Output Voltage (Iout=-400μA) Low-Level Output Voltage VOL (CDTO pin: Iout=400μA) VOL (Q0-4, INT pins: Iout=1mA) VOL (SDA pin: Iout=3mA) Input Leakage Current Iin Parameter Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) AVDD VVDD1+VVDD2 DVDD Power-down mode (PDN pin = “L”) AVDD VVDD1+VVDD2 DVDD Total Note: 17. Note: 18. Note: 19. DC min typ - max - Units V - 30%DVDD V - - V - 0.4 0.4 0.4 ±10 V V V μA typ max Units 18 18 1 27 27 2 mA mA mA 50 μA μA μA μA (Note: 17) (Note: 18) (Note: 19) 10 10 10 30 (SAGN bit= “1”) 18mA(typ) DVSS MS0627-J-01 2010/09 - 10 - [AK4220] (Ta= -40 85°C; AVDD = VVDD1-2 = 4.5∼5.5V, DVDD= 3.0∼3.6V, CL= 20pF) Control Interface Timing (I2C Bus. Note: 20) SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note: 21) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 Capacitive load on bus Cb Control Interface Timing (4-wire serial mode) tCCK 200 CCLK Period tCCKL 80 CCLK Pulse Width Low tCCKH 80 Pulse Width High tCDS 50 CDTI Setup Time tCDH 50 CDTI Hold Time tCSW 150 CSN “H” Time tCSS 50 CSN “↓” to CCLK “↑” tCSH 50 CCLK “↑” to CSN “↑” tDCD CDTO Delay tCCZ CSN “↑” to CDTO Hi-Z Power-down & Reset Timing tPD 150 PDN Pulse Width (Note: 22) Note: 20. I2C-bus NXP B.V. Note: 21. 300ns (SCL ) Note: 22. PDN pin “L” MS0627-J-01 400 0.3 0.3 50 400 kHz μs μs μs μs μs μs μs μs μs μs ns pF 45 70 ns ns ns ns ns ns ns ns ns ns ns 2010/09 - 11 - [AK4220] ■ VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT Start tSU:DAT tSU:STA tSU:STO Start Stop Figure 7. I2C VIH CSN VIL tCSS tCCK tCCKL tCCKH VIH CCLK VIL tCDH tCDS C1 CDTI C0 A4 R/W VIH VIL Hi-Z CDTO Figure 8. WRITE/READ (4-wire serial mode) tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 D0 VIH VIL Hi-Z CDTO Figure 9. WRITE (4-wire serial mode) MS0627-J-01 2010/09 - 12 - [AK4220] VIH CSN VIL VIH CCLK CDTI VIL A1 VIH A0 VIL tDCD Hi-Z CDTO D7 Figure 10, READ D6 D5 50%DVDD 1 (4-wire serial mode) tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI VIL tCCZ CDTO 50%DVDD D2 D1 Figure 11. READ D0 Hi-Z 2 (4-wire serial mode) tPD PDN VIL Figure 12. MS0627-J-01 2010/09 - 13 - [AK4220] ■ / AK4220 PDN pin “L” ■ AK4220 AVSS (MUTET pin) BIAS bit “0” 150ms (typ, Note: 23) AVSS Note: 23. AVDD=5.0V, MUTET pin MUTET pin AVDD/2(typ) BIAS bit “1” 150ms(typ, Note: 23) AVDD/2(typ) C=1uF AVDD PDN pin BIAS bit “0” (default) “1” “0” 150ms (typ) 150ms (typ) Audio bias level Figure 13. BIAS bit ■ L/R LIN/RIN C AK4220 LIN+1-7, RIN+1-7, GND1-7 pin Sync Tip 0.47uF VIN1-6 pin 0.1uF C MS0627-J-01 2010/09 - 14 - [AK4220] ■ AK4220 7:3 Lch/Rch 6:3 ASEL12-10, ASEL22-20, ASEL32-30 bit VSEL12-10, VSEL22-20, VSEL32-30 bit ASEL12 bit 0 0 0 0 1 1 1 1 ASEL11 bit 0 0 1 1 0 0 1 1 ASEL10 bit 0 1 0 1 0 1 0 1 Table 1. ASEL22 bit 0 0 0 0 1 1 1 1 1 (LOUT1/ROUT1 ASEL21 bit 0 0 1 1 0 0 1 1 ASEL20 bit 0 1 0 1 0 1 0 1 Table 2. ASEL32 bit 0 0 0 0 1 1 1 1 ASEL31 bit 0 0 1 1 0 0 1 1 ASEL30 bit 0 1 0 1 0 1 0 1 Off BIAS bit = “0” (default) ) Off (Note: 24) LIN+1 / RIN+1 LIN+2 / RIN+2 LIN+3 / RIN+3 LIN+4 / RIN+4 LIN+5 / RIN+5 LIN+6 / RIN+6 LIN+7 / RIN+7 2 (LOUT2/ROUT2 Table 3. Note: 24. Off (Note: 24) LIN+1 / RIN+1 LIN+2 / RIN+2 LIN+3 / RIN+3 LIN+4 / RIN+4 LIN+5 / RIN+5 LIN+6 / RIN+6 LIN+7 / RIN+7 (default) ) Off (Note: 24) LIN+1 / RIN+1 LIN+2 / RIN+2 LIN+3 / RIN+3 LIN+4 / RIN+4 LIN+5 / RIN+5 LIN+6 / RIN+6 LIN+7 / RIN+7 3 (LOUT3/ROUT3 (default) ) VCOM 0V MS0627-J-01 2010/09 - 15 - [AK4220] VSEL12 bit 0 0 0 0 1 1 1 1 VSEL11 bit 0 0 1 1 0 0 1 1 VSEL10 bit 0 1 0 1 0 1 0 1 Table 4. VSEL22 bit 0 0 0 0 1 1 1 1 1 (VOUT1 VSEL21 bit 0 0 1 1 0 0 1 1 VSEL20 bit 0 1 0 1 0 1 0 1 Table 5. VSEL32 bit 0 0 0 0 1 1 1 1 VSEL31 bit 0 0 1 1 0 0 1 1 VSEL30 bit 0 1 0 1 0 1 0 1 Off (default) ) Off (Note: 25) VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 N/A 3 (VOUT3 (default) ) Off (Note: 25) VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 N/A 2 (VOUT2 Table 6. Note: 25. Off (Note: 25) VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 N/A (default) ) Hi-Z MS0627-J-01 2010/09 - 16 - [AK4220] ■ INT pin AK4220 L/R Table 7, Table 8 ADSEL2 bit 0 0 0 0 1 1 1 1 ADSEL1 bit 0 0 1 1 0 0 1 1 ADSEL0 bit 0 1 0 1 0 1 0 1 Off LIN+1 / RIN+1 LIN+2 / RIN+2 LIN+3 / RIN+3 LIN+4 / RIN+4 LIN+5 / RIN+5 LIN+6 / RIN+6 LIN+7 / RIN+7 (default) VDSEL0 bit 0 1 0 1 0 1 0 1 Off VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 N/A (default) Table 7. VDSEL2 bit 0 0 0 0 1 1 1 1 VDSEL1 bit 0 0 1 1 0 0 1 1 Table 8. 1. ADETL bit (Lch ), ADETR bit (Rch 100kHz 30% ACT1-0 bit ACT1-0 bit ADETL-R bit “0” ADETL-R bit 6dB L/R ) ADETL-R bit “1” RTM1-0 bit LV2-0 bit -31dBV(= +40mV0p)(typ) (05H) WRITE ADETL/R bit “0” ADETL/R bit MADETL/R bit ADSEL2-0, ACT1-0, RTM1-0 bit / MS0627-J-01 2010/09 - 17 - [AK4220] LV2 bit 0 0 0 0 1 1 1 1 LV1 bit 0 0 1 1 0 0 1 1 LV0 bit 0 1 0 1 0 1 0 1 -6dB -3dB 0dB +3dB +6dB N/A N/A N/A 0dB = +40mV0p(typ) (default) Table 9. ACT1 bit 0 0 1 1 ACT0 bit 0 1 0 1 1 2 4 8 (default) Table 10. RTM1 bit RTM0 bit 0 0 1 1 0 1 0 1 (typ) 40ms 80ms 160ms 320ms (default) Table 11. -31dBV(default) Input pin (ex. LIN+1) x ADETL bit INT pin x “0” Hi-Z (pulled-up) “1” “L” “0” Hi-Z (pulled-up) Figure 14. Audio MS0627-J-01 2010/09 - 18 - [AK4220] 2. VDET bit( ) VDMD bit VDMD bit =“0”(Default) 0.07Vpp(typ) Read 1 VDET bit “1” VDSEL2-0 bit (04H) Write( ) VDET bit “0” “0” VDET bit (08H) VDMD bit =“1” 40ms ( 1 30%) 1 384 2 0.07Vpp (typ) VDET bit “1” 2 0.5 VDET bit “0” 0.5 1 384 VDET bit “1” 1 (40ms x 70% = 28ms) 384 384 (min) = (1/fH) x 384 + 28ms x 1.5 1 2 H: (40ms x 130% = 52ms) 383 384 (max) = (1/fH) x 383 + 52ms x 2.5 VDSEL2-0 bit ) VDET bit 66.6ms @ fH=15.625kHz (04H) 154.5ms @ fH=15.625kHz Write( VDET bit “0” MVDET bit 1st period 2nd period 3rd period 4th period Input pin (ex. VIN1) ≥384 times VDET bit ≥384 times “0” “1” Input pin (ex. VIN1) ≤384 times VDET bit ≥384 times ≥384 times “0” Figure 15. VDET “1” (VDMD bit =“1”) MS0627-J-01 2010/09 - 19 - [AK4220] 3. INT pin ADETL/R bit, VDET bit OR INT pin “L” INT pin INT pin INT pin=“Hi-Z” INT pin “H” INT pin=“L” “1” +3.3V DVDD AK4220 10k VDET MVDET INT pin ADETL MADETL ADETR MADETR DVSS Figure 16. INT pin MVDET bit 0 0 0 0 1 1 1 1 MADETL bit 0 0 1 1 0 0 1 1 MADETR bit 0 1 0 1 0 1 0 1 INT pin output source VDET bit, ADETL bit, ADETR bit “OR” VDET bit, ADETL bit “OR” VDET bit, ADETR bit “OR” VDET bit ADETL bit, ADETR bit “OR” ADETL bit ADETR bit “L”(INT pin = “Hi-Z”) (default) Table 12. INT pin MS0627-J-01 2010/09 - 20 - [AK4220] ■ INT Q0-4 bit DVDD SDA pin SDA Q0-4 pin 10kohm INT pin Figure 16 I2C DVDD DVDD DVDD AK4220 AK4220 DVDD DVDD DVDD OFF DVDD PDN pin =“L” VVDD1-2,AVDD AK4220 +3.3V DVDD 10k AK4220 Q0-4 pin Q0~Q4 bit DVSS Figure 17. Q0-Q4, INT pin +3.3V DVDD AK4220 SDA pin DVSS Figure 18. SDA pin MS0627-J-01 2010/09 - 21 - [AK4220] ■ 1. 4 (IICN pin = “H”) 4 I/F (CSN, CCLK, CDTI, CDTO) I/F Chip address (2bits, “00” Register address (MSB first, 5bits) Control Data (MSB first, 8bits) “↑” CSN “ ” CSN “↑” Hi-Z CCLK (max) PDN pin= “L” ), Read/Write (1bit), CCLK “↓” 16 CCLK“ ” 5MHz CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK WRITE CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z CDTO READ CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z CDTO C1,C0: R/W: A4-A0: D7-D0: D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z Chip Address: ( “00” ) READ/WRITE (0:READ, 1:WRITE) Register Address Control Data Figure 19. 4 I/F MS0627-J-01 2010/09 - 22 - [AK4220] 2. I2C (IICN pin = “L”) AK4220 I2C (max:400kHz) 1. WRITE I2C (Start Condition) (Figure 26) (R/W) (Figure 21) Figure 20 “H” SDA SCL 5 AK4220 SDA R/W “00100” IC “L” “H” 7 CAD0-1 pin 2 (Acknowledge) 8 (Figure 27) R/W “0” “1” 2 ( (Figure 22) 3 (Figure 23) AK4220 (Stop Condition) (Figure 26) ) 8 SCL MSB first 8 “H” 4 SDA AK4220 “0” MSB first “L” “H” 1 “08H” “00H” “H” SCL SDA “L” S T A R T SDA “H” “L” “H” SDA (Figure 28) SCL S T O P R/W="0" Slave S Address Sub Address(n) Data(n) A C K A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 20. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 CAD1 CAD0 R/W A2 A1 A0 D2 D1 D0 Figure 21. The First Byte 0 0 0 0 A3 Figure 22. The Second Byte D7 D6 D5 D4 D3 Figure 23. Byte Structure after the second byte MS0627-J-01 2010/09 - 23 - [AK4220] 2. READ R/W “1” AK4220 READ “08H” “00H” AK4220 2 READ 2-1. AK4220 (READ WRITE ) “n” “n+1” = “1”) AK4220 READ (R/W bit 1 READ S T A R T SDA S T O P R/W="1" Slave S Address Data(n+1) Data(n+2) A C K Data(n+3) A C K A C K Data(n+1+x) A C K A C K P A C K Figure 24. CURRENT ADDRESS READ 2-2. READ (R/W bit = “1”) WRITE WRITE AK4220 (R/W bit = “1”) (R/W bit = “0”) READ AK4220 1 READ S T A R T SDA S T A R T R/W="0" Slave S Address Slave S Address Sub Address(n) A C K A C K S T O P R/W="1" Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 25. RANDOM ADDRESS READ MS0627-J-01 2010/09 - 24 - [AK4220] SDA SCL S P start condition stop condition Figure 26. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 27. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 28. Bit Transfer on the I2C-Bus MS0627-J-01 2010/09 - 25 - [AK4220] ■ Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H Register Name Power Down & Reset Input Selector 1 Input Selector 2 Input Selector 3 Detection Control1 Detection Control2 Detection Control3 Parallel Output AV Detection Note: PDN pin = “L” “0” 00H ∼08H D7 0 0 0 0 0 RTM1 VDMD 0 0 D6 0 VSEL12 VSEL22 VSEL32 VDSEL2 RTM0 MVDET 0 VDET D5 0 VSEL11 VSEL21 VSEL31 VDSEL1 ACT1 D4 SAGN VSEL10 VSEL20 VSEL30 VDSEL0 ACT0 MADETR MADETL 0 ADETR Q4 ADETL D3 0 0 0 0 0 0 0 Q3 0 D2 0 ASEL12 ASEL22 ASEL32 0 ADSEL2 LV2 Q2 0 D1 BIAS ASEL11 ASEL21 ASEL31 0 ADSEL1 LV1 Q1 0 D0 PW ASEL10 ASEL20 ASEL30 0 ADSEL0 LV0 Q0 0 “1” ■ Register Definitions Reset & Initialize Addr 00H Register Name Power Down & Reset R/W Default D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 SAGN 0 0 BIAS PW R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 D3 D2 D1 D0 PW: 0: 1: (default) PDN pin=“L” PW bit=”1” PDN pin BIAS: 0: 1: (default) SAGN: 0: SAG 1: DC Addr 01H Register Name Input Selector 1 R/W Default (default) D7 D6 D5 D4 0 VSEL12 VSEL11 VSEL10 0 ASEL12 ASEL11 ASEL10 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 ASEL12-10: Table 1 VSEL12-10: Table 4 1 1 MS0627-J-01 2010/09 - 26 - [AK4220] Addr Register Name Input Selector 2 R/W Default 02H D7 D6 D5 D4 D3 D2 D1 D0 0 VSEL22 VSEL21 VSEL20 0 ASEL22 ASEL21 ASEL20 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 ASEL22-20: Table 2 VSEL22-20: Table 5 Addr Register Name Input Selector 3 R/W Default 03H 2 2 D7 D6 D5 D4 D3 D2 D1 D0 0 VSEL32 VSEL31 VSEL30 0 ASEL32 ASEL31 ASEL30 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 D5 D4 D3 D2 D1 D0 0 0 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 D2 D1 D0 ASEL32-30: Table 3 VSEL32-30: Table 6 Addr 04H Register Name Detection Control1 R/W Default 3 3 D7 0 R/W 0 D6 VDSEL2 VDSEL1 VDSEL0 R/W 0 R/W 0 VDSEL2-0: Table 8 Addr 05H Register Name Detection Control2 R/W Default D7 D6 D5 D4 D3 RTM1 RTM0 ACT1 ACT0 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 ADSEL2 ADSEL1 ADSEL0 R/W 0 R/W 0 R/W 0 ADSEL2-0: Table 7 ACT1-0: Table 10 RTM1-0: Table 11 MS0627-J-01 2010/09 - 27 - [AK4220] Addr 06H Register Name Detection Control3 R/W Default D7 VDMD R/W 0 D6 D5 D4 MVDET MADETR MADETL R/W 0 R/W 0 R/W 0 D3 D2 D1 D0 0 LV2 LV1 LV0 R/W 0 R/W 0 R/W 1 R/W 0 LV2-0: Table 9 MADETL/R: Table 12 Lch/Rch MVDET: Table 12 VDMD: “0”: 1 VDET bit “1” 08H (default) “1”: VDET bit( Addr ) Register Name Parallel Output R/W Default 07H VDET bit “0” (P19) D7 D6 D5 D4 D3 D2 D1 0 0 0 Q4 Q3 Q2 Q1 D0 Q0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 D0 Q4-0: “0”: “L” “1”: Hi-Z(default) Addr Register Name AV Detection R/W Default 08H ADETL/R: “0”: “1”: D7 D6 D5 D4 D3 D2 D1 0 VDET ADETR ADETL 0 0 0 0 READ 0 READ 0 READ 0 READ 0 READ 0 READ 0 READ 0 READ 0 Lch/Rch (default) VDET: “0”: “1”: (default) 08H MS0627-J-01 2010/09 - 28 - [AK4220] Figure 29 (AKD4220) Analog Ground Audio in 0.47u 0.47u LIN+2 49 RIN+2 50 0.47u 0.47u 0.47u 0.47u GND3 51 LIN+3 52 RIN+3 53 GND4 54 0.47u LIN+4 55 0.47u 0.47u 0.47u 0.47u 0.47u 0.47u 0.47u 0.47u RIN+4 56 GND5 57 LIN+5 58 RIN+5 59 GND6 60 LIN+6 61 RIN+6 62 LIN+7 64 GND2 48 2 PDN RIN+1 47 0.47u 3 CAD1 LIN+1 46 0.47u 4 SCL GND1 45 0.47u 5 SDA ROUT3 44 6 CAD0 LOUT3 43 7 INT ROUT2 42 8 Q0 LOUT2 41 AK4220 9 Q1 ROUT1 40 10 Q2 LOUT1 39 11 Q3 AVSS 38 10u 0.1u + 13 DVDD MUTET 36 14 DVSS R 35 AVDD 34 300 10u 300 10u 300 10u 300 Audio out 12k + 0.1u 10u 1u Analog 5V 32 VIN5 31 IICN 30 VIN4 29 VVSS1 27 VVDD1 28 VIN3 0.1u 75 75 0.1u 0.1u 75 0.1u 75 2.2u 100u 300 10u + 0.1u 10u 0.1u 26 VIN2 25 VVSS3 24 VIN1 23 VVSS2 22 VFB3 21 VOUT3 20 VVDD2 + VIN6 33 300 10u 75 2.2u 2.2u 100u 75 75 100u 10u 0.1u 19 VFB2 17 TEST 16 VFB1 18 VOUT2 15 VOUT1 10u 75 0.1u 10k Audio in + 0.1u 2.2u VCOM 37 12 Q4 Digital 3.3V 0.47u 1 RIN+7 75 External Block Micro Controller GND7 63 0.47u 0.47u Digital Ground Video out Video in Analog 5V Figure 29. Typical Connection Diagram MS0627-J-01 2010/09 - 29 - [AK4220] 1. AVDD, VVDD1-2, DVDD AVSS, VVSS1-3, PC DVSS 2. VCOM 2.2μF 0.1μF AVSS VCOM pin VCOM pin MUTET 1.0μF AVSS MUTET pin MUTET pin 3. 4. AK4220 150Ω Figure 30 3ch 100μF+2.2μF 600 mV(typ) DC SAGN bit Figure 31 DC VOUT pin VFB pin Table 13 C3 100uF +6dB VOUT R1 75Ω C4 2.2uF R2 75Ω VFB Figure 30. DC (SAGN bit=“0”, ) R1 75Ω +6dB VOUT R2 75Ω VFB Figure 31. SAGN bit 0 1 (SAGN bit=“1”, DC ) (default) DC Table 13. MS0627-J-01 2010/09 - 30 - [AK4220] 64pin LQFP(Unit: mm) 12.0 Max 1.85 10.0 1.40 0.00~0.25 33 32 48 12.0 49 64 17 16 1 0.2±0.1 0.5 0.09~0.25 0.10 M 0°~10° 0.50±0.25 0.10 ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0627-J-01 2010/09 - 31 - [AK4220] AKM AK4220VQ XXXXXXX 1 1) Pin #1 indication 2) Asahi Kasei Logo 3) Marking Code: AK4220VQ 4) Date Code: XXXXXXX (7 digits) Date (YY/MM/DD) 07/05/10 10/09/28 Revision 00 01 Reason Page Contents 21 ■ ( INT Figure 9) → ( SDA Figure 16) 31 MS0627-J-01 2010/09 - 32 - [AK4220] z z z z z z MS0627-J-01 2010/09 - 33 -