AK2346B

ASAHI KASEI
[AK2346B]
AK2346B
Two-way Radio Audio Processor
1. Features
• Audio processing
• TX and RX amplifier
• Pre/De-emphasis circuit
• Compressor and Expander with no external components
• Scrambler and De-scrambler in frequency inversion type
• Limiter with level adjuster
• Splatter filter for wide and narrow band
• Digital controlled amplifier for microphone, modulator and demodulator sensitivity
• 1200/2400bps MSK MODEM with frame detection
• Wide range operation voltage: 1.9V to 5.5V, temperature: -30 to 75 °C
• Oscillator circuit for 3.6864MHz crystal
• Serial control interface operation
• Compact plastic packaging, 24-pin SSOP
2. Description
AK2346B includes audio filter, limiter, splatter filter, COMPANDOR, scrambler, MSK MODEM, which
is highly integrated two-way radio baseband functions for FRS and LMR.
Audio high-pass filter shows a high attenuation in magnitude response characteristics under 250Hz
that supports to eliminate a subaudio tone clearly.
TX limiter for deviation control has a limiting level adjuster by applying a DC voltage via external
components. Splatter filter has the magnitude response for narrowband(fc=2.55kHz) and
wideband(3.0kHz) to meet various regulatory agencies in the world wide.
COMPANDOR is no adjustment type because it includes all parametric components inside the chip.
Scrambler circuit is composed of frequency inversion circuit by double balanced mixer that has
3.388kHz carrier clock.
MSK MODEM for data communication can be chosen either 2400bps or 1200bps. 2400bps data rate
provides a high speed data transmission and 1200bps supports a low BER(bit error rate) performance
that is suitable for under weak electrical field condition application.
There are four signal level adjusters for microphone, modulator and demodulator sensitivity by digital
controlled amplifier (volume).
• Pin Assignment
AGNDIN
1
24
TEST
AGND
2
23
RXIN
TXIN
3
22
RXINO
TXINO
4
21
RXLPFO
LIMLV
5
20
RXAF
EXTLIMIN
6
19
RXAFIN
MOD
7
18
EXPOUT
VSS
8
17
VDD
TCLK
9
16
XIN
TDATA
10
15
XOUT
DI/O
11
14
DIR
RDF/FD
12
13
SCLK
MS1409-E-01
2013/12
-1-
ASAHI KASEI
[AK2346B]
3. Contents
1. Features............................................................................................................................... 1
2. Description ........................................................................................................................... 1
3. Contents .............................................................................................................................. 2
4. Block Diagram ..................................................................................................................... 3
5. Circuit Configuration ............................................................................................................ 4
6. Pin/Function ......................................................................................................................... 5
7. Absolute Maximum Ratings ................................................................................................. 7
8. Recommended Operating Conditions .................................................................................. 7
9. Digital DC characteristics ..................................................................................................... 7
10. Power Consumption........................................................................................................... 8
11. Analog characteristics ........................................................................................................ 9
12. Level Diagram .................................................................................................................. 14
13. Serial Interface Configuration .......................................................................................... 15
14. Digital AC timing .............................................................................................................. 20
15. MSK MODEM Description ............................................................................................... 23
16. Recommended External Application Circuits ................................................................... 26
17. Packaging ........................................................................................................................ 30
18. Important Notice............................................................................................................... 31
MS1409-E-01
2013/12
-2-
ASAHI KASEI
[AK2346B]
4. Block Diagram
MS1409-E-01
2013/12
-3-
[AK2346B]
5. Circuit Configuration
Block
TXA1
VR1
(HPF)
Compressor
Pre-emphasis
TX/RXHPF
Scrambler/
Descrambler
Limiter
Splatter
VR2
SMF
RXA1
VR3
RXLPF
De-emphasis
Expander
VR4
RXA2
MSK Modulator
MSK BPF
MSK Demodulator
Description
The operational amplifier for transmit audio gain adjustment and for the filter to eliminate
aliasing noise by the SCF(switched capacitor filter) in the following stage. Please select
an external resistor and capacitor to set the gain less than 30dB and the cut-off frequency
to about 10kHz.
Digitally controlled amplifier (volume) for transmit audio signal level which is adjustable in
1.5dB steps over a –6.0dB to +4.5dB range by setting VR12 to VR10 register.
The circuit to compress transmits audio signal level by 1/2 in dB scale.
Standard cross-point is –10dBx. TC register sets OFF/ON to the circuit.
The circuit to emphasis the high-frequency component of transmit audio signal to improve
S/N ratio of the modulation signal.
The High-pass filter to eliminate the low-frequency component less than 250Hz for
transmit and receive audio signal.
Scramble/De-scramble circuit to inverse transmit and receive audio spectrum by
3.388kHz carrier signal.
EM and PCONT register can set scramble/De-scramble or Emphasis circuit. Both circuits
do not use simultaneously.
An amplitude limiting circuit to suppress the frequency deviation of the modulation signal.
The limitation level can be adjusted by applying a DC voltage to the LIMLV pin. If the
LIMLV pin is open, the limitation level is applied to a predetermined level.
The circuit to eliminate the high frequency component higher than 3kHz included in the
limiter output signal or the MSK modulator signal. The cut-off frequency can be selected
by SPL register.
Digitally controlled amplifier (volume) for MOD output level which is adjustable in 0.2dB
steps over a –3.2dB to +3.0dB range by setting VR25 to VR20 register. VR25 is a –6/0dB
coarse bit.
The smoothing filter to eliminate the high frequency and clock component caused in SCF
circuits.
The operational amplifier for receives audio gain adjustment and for the filter to eliminate
aliasing noise by the SCF in the following stage. Please select an external resistor and
capacitor to set the gain less than 20dB and the cut-off frequency to about 40kHz.
Digitally controlled amplifier (volume) for receive audio signal level which is adjustable in
0.5dB steps over a –4.0dB to +3.5dB range by setting VR33 to VR30 register.
The Low-pass filter to eliminate the high frequency component higher than 3kHz for
receive audio signal.
The circuit to de-emphasis the emphasized signal by pre-emphasis circuit.
The circuit to expand the receive audio signal level to double in dB scale compressed by
compressor
Standard cross-point is –10dBx. TC register sets OFF/ON to the circuit.
Digitally controlled amplifier (volume) for EXPOUT output level which is adjustable in
1.5dB, steps over a –18dB and –4.5dB to +4.5dB range by setting VR42 to VR40 register.
The operational amplifier used on smoothing filter to eliminate clock component included
in EXPOUT output signal. Please set the gain to 0dB and the cut-off frequency to about
20kHz by external resistor and capacitor.
The circuit to generate a MSK signal according to the received digital data from TDATA
pin.
The Band-pass filter to eliminate the low and high frequency component for received MSK
signal.
The circuit to reproduce the 1200/2400bps receive clock and data from MSK signal at
RXIN pin.
MS1409-E-01
2013/12
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[AK2346B]
Block
AGND
Description
The circuit to generate the reference voltage (1/2VDD) for internal analog signal.
The circuit to oscillate the 3.6864MHz reference clock with an external crystal oscillator
and resistor and capacitors.
The control register controls the status of internal switches and digitally controlled
amplifiers of IC by serial data that consists of 3 address bits and 8 data bits. At the start
up a power-on-reset circuit works and “Reset” data are set to the control register. (Refer
to the control register map)
The data buffer stores 8 bits of the MSK received data to smooth the signal interface with
microprocessor.
OSC
Control
Register
6. Pin/Function
Package
Pin No
Signal
Name
Type
1
AGNDIN
I
2
AGND
O
3
TXIN
I
4
TXINO
O
5
LIMLV
I
6
EXTLIMIN
I
7
MOD
O
8
VSS
PWR
9
TCLK
O
10
TDATA
I
11
DI/O
I/O
12
RDF/FD
O
Function
Analog ground input pin.
Connect the capacitor to stabilize the analog ground level. This pin also has
reset function for the registers. Connecting to the low level, “Reset” data are set
to the control register.
Analog ground output pin.
Connect the capacitor to stabilize the analog ground level.
Transmit audio signal input pin.
This is the inverting input pin for TXA1. It composes a microphone amplifier with
an external resister and capacitor.
TXA1 feedback output pin.
Limit level adjuster pin.
A limit level can be adjusted by applying a DC voltage to this pin. If it is open,
the level is fixed to a predetermined level.
External signal input pin pre-limiter circuit.
This pin is available for external tone signal.
The modulated transmit signal output pin.
Load impedance larger than 10kΩ can be drive.
Negative power supply pin.
Normally supply 0V to this pin.
Clock output pin for MSK transmission data.
Setting the register named TXSW2 to “0” puts out 1.2/2.4kHz clock. If the
register is set to “1”, it goes to High level.
MSK transmission data input pin.
Data are latched synchronizing with the TCLK rising edge.
Serial data input and output pin.
Input for register setting data and output for MSK receive data.
MSK signal received flag and frame detection signal output pin.
This pin puts out two types of signal that depends on the status of register
named FSL.
In case FSL equal “1”, it is received flag mode (RDF). So the pin puts out low
level after 8 bits of MSK receive signal have been written to the internal register.
In case FSL equal “0”, it is frame detection mode (FD). So the low pulse is put
out after a frame pattern is detected.
MS1409-E-01
2013/12
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[AK2346B]
Package
Signal
Pin No
Name
Type
13
SCLK
I
Function
Clock input pin for serial data I/O.
14
DIR
I
Serial data I/O control pin.
15
XOUT
I
16
XIN
I/O
17
VDD
PWR
18
EXPOUT
O
19
RXAFIN
I
20
RXAF
O
21
RXLPFO
O
22
RXINO
O
23
RXIN
I
24
TEST
I
Crystal oscillator connecting input pin.
Crystal oscillator connecting input and output pin.
To connect a 3.6864MHz crystal oscillator between this pin and XOUT pin
generates the reference clock internally.
In case of externally supplied clock operation, connect to this pin. For more
information, please refer to external application circuits.
Positive power supply pin.
Normally connect to 1.9V to 5.5V noiseless power-supply. Also this pin must be
decoupled to VSS pin by 0.1uF capacitor mounted close to the device pins.
Expander and VR4 output pin.
Receive audio signal input pin.
This is the inverting input of RXA2. It composes a smoothing filter by external
resistor and capacitor.
Receive audio signal output pin.
This is the output pin of RXA2. Load impedance more than 10kΩ can be driven.
Receive LPF output pin.
This is a monitor pin for tone signal. 57.6kHz sampling-clock is included, so
please eliminate this signal component by LPF externally.
Load impedance more than 10kΩ can be driven.
RXA1 feedback output pin.
Demodulated audio signal input pin.
This is the inverting input of RXA1. It composes a pre-filter with external resistor
and capacitor.
Test register control input pin.
When this pin set to high level, test register is controllable. Please set to low
level or open for normal operation.
MS1409-E-01
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[AK2346B]
7. Absolute Maximum Ratings
Parameter
Symbol
Power Supply Voltage
VDD
Ground Level
VSS
Input Voltage
VIN
Input Current
IIN
(Except power supply pin)
Storage Temperature
Tstg
Note : All voltages with respect to the VSS pin.
Min.
-0.3
0
-0.3
Max.
6.5
0
VDD+0.3
Units
V
V
V
-10
+10
mA
-55
130
°C
Caution : Exceeding these maximum ratings can result in damage to the device.
Normal operation cannot be guaranteed under this extreme.
8. Recommended Operating Conditions
Parameter
Operating Temperature
Power Supply Voltage
Symbol
Condition
Ta
VDD
AGND
Analog Reference Voltage
RL1
MOD, RXAF, RXLPFO
Output Load Resistance
RL2
TXINO, RXINO, EXPOUT
CL1
MOD, RXAF, RXLPFO
Output Load Capacitance
CL2
TXINO, RXINO, EXPOUT
FCK
XIN, XOUT
Master Clock Frequency
Note : All voltages with respect to the VSS pin.
Min.
-30
1.9
Typ.
3.0
1/2VDD
Max.
75
5.5
10
30
Units
°C
V
V
kΩ
50
15
3.6864
pF
MHz
9. Digital DC characteristics
Parameter
High level input voltage
Low level input voltage
Symbol
VIH1
VIH2
VIL1
VIL2
High level input current
IIH
Low level input current
IIL
High level output voltage
VOH
Low level output voltage
VOL
Condition
TDATA, DI/O
SCLK, DIR
Min.
0.7VDD
0.8VDD
TDATA, DI/O
SCLK, DIR
VIH=VDD
TDATA, DI/O, SCLK, DIR
VIL=0V
TDATA, DI/O, SCLK, DIR
IOH=+0.2mA
TCLK, RDF/FD, DI/O
IOL=-0.4mA
TCLK, RDF/FD, DI/O
MS1409-E-01
Typ.
Max.
Units
V
0.3VDD
0.2VDD
V
10
uA
-10
uA
VDD-0.4
VDD
V
0.0
0.4
V
2013/12
-7-
[AK2346B]
10. Power Consumption
Parameter
Symbol
IDD0
IDD1
Current
Consumption
IDD2
IDD3
IDD4
Condition
Min.
Mode 0
OSC:OFF, Audio: OFF, MODEM:OFF
Mode 1
OSC:ON , Audio: OFF, MODEM:OFF
Mode 2
OSC:ON , Audio: ON , MODEM:OFF
Mode 3
OSC:ON , Audio: OFF, MODEM:ON
Mode 4
OSC:ON , Audio: ON , MODEM:ON
MS1409-E-01
Typ.
Max.
0.1
0.3
0.9
1.7
5.5
7.6
2.2
3.4
6.1
8.4
Units
mA
2013/12
-8-
[AK2346B]
11. Analog characteristics
For the following conditions unless otherwise specified: f=1kHz, Emphasis: on, COMPANDOR: on,
Scrambler: off, VR1=VR2=VR3=VR4=0dB with the external circuit shown in example page.26 to 29.
“dBx” is standardized unit for 1.9V to 5.5V operation, 0dBx=-5+20log(VDD/2)dBm, 0dBm=0.775Vrms.
1) TX Audio System
Parameter
Condition
Standard Input Level
@TXINO
Absolute Gain
Limit Level
TXINO to MOD
Noise Level with no
signal input
VR1
Attenuation Error
VR2 ATT Error
(VR24,23,22,21,20)
VR2 ATT Error
(VR25=0)
EXTLIMIN to MOD
Without external R adjustment
With external R adjustment
TXINO to MOD
TXINO=-44dBx
TXINO=-50dBx
Relative value to 0dB for MOD
level of -10dBx TXINO.
TXINO to MOD
TXINO=-10dBx
30kHz Low-pass filtering
TXINO to MOD
C-Message filtering
TXINO to MOD
-6.0 dB to 4.5dB, 1.5dB/step
TXINO to MOD
-3.2dB to +3.0dB, 0.2dB/step
TXINO to MOD
Relative error for -6/0dB
2) RX Audio System
Parameter
Condition
Compressor
Linearity
Compressor
Distortion
Standard Input Level
Absolute Gain
Min.
Typ.
Max.
Units
-1.5
-10
0
+1.5
dBx
dB
-8.6
-7.6
-6.6
-6.6
-20.0
-24.0
-17.0
-20.0
-14.0
-16.0
dB
-35
dB
-36.5
dBm
-1.5
+1.5
dB
-0.2
+0.2
dB
dBx
-6.4
-6
-5.6
dB
Min.
Typ.
Max.
Units
RXINO to RXLPFO
-1.5
-10
0
+1.5
dBx
dB
RXINO to RXAF
-1.5
0
+1.5
dB
-33.0
-45.0
-30.0
-40.0
-27.0
-35.0
dB
-35
dB
-70
dBm
-0.5
+0.5
dB
-1.5
+1.5
dB
-16
dB
@RXINO
Expander
Linearity
RXINO to RXAF
RXINO=-25dBx
RXINO=-30dBx
Relative value to 0dB for RXAF
level of -10dBx RXINO
Expander
RXINO to RXAF
Distortion
RXINO=-5dBx
30kHz Low-pass filtering
Noise Level with no RXINO to RXAF
signal input
C-Message Filtering
VR3
RXIN0 to RXAF
-4.0dB to +3.5dB, 0.5dB/step
Attenuation Error
VR4
RXIN0 to RXAF
-4.5 to +4.5dB, 1.5dB/step
Attenuation Error
VR4 ATT Error
RXIN0 to RXAF
(VR42,41,40=0,0,0) Relative error for -18/0dB
MS1409-E-01
-20
-18
Notes
Notes
2013/12
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[AK2346B]
3) Audio Filter Characteristics
3.1) Emphasis: off, COMPANDOR: off, Scrambler: off
Parameter
Condition
TX overall
250Hz
TXINO to MOD
characteristics
300Hz to 2.0kHz
2.5kHz
Relative value
3.0kHz
to gain at
6.0kHz
1kHz
300Hz to 2.5kHz
3.0kHz
6.0kHz
RX overall
250Hz
RXINO to RXAF
characteristics
300Hz
350Hz to 3.0kHz
Relative value
6.0kHz
to gain at 1kHz
3.2) Emphasis: on, COMPANDOR: off, Scrambler: off
Parameter
Condition
TX overall
250Hz
TXINO to MOD
characteristics
300Hz
2.5kHz
3.0kHz
Relative value
6.0kHz
to gain at
300Hz
1kHz
2.5kHz
3.0kHz
6.0kHz
RX overall
250Hz
RXINO to RXAF
characteristics
300Hz
3.0kHz
Relative value
6.0kHz
to gain at 1kHz
MS1409-E-01
(Design target values)
Min.
Typ.
Max.
-50
-38
-1.0
+1.0
-1.5
+1.0
-4.0
-1.0
-32
-28
-1.0
+1.0
-1.5
+1.0
-26
-22
-49
-38
-1.5
+1.0
-1.0
+1.0
-38
-28
Min.
Typ.
-57
-12.5
+6.0
+4.5
-23
-12.5
+6.0
+7.0
-17
-38
+8.5
-11.5
-52
Max.
-40
-9.5
+9.0
+8.5
-18
-9.5
+9.0
+10.5
-12
-26
+11.5
-8.5
-40
Units
dB
dB
dB
Notes
SPL=0
fc=2.55K
SPL=1
fc=3.0K
dB
Units
dB
dB
dB
Notes
SPL=0
fc=2.55K
SPL=1
fc=3.0K
dB
2013/12
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[AK2346B]
• Audio path frequency response (Emphasis:off)
20
10
GAIN(dB)
0
-10
SPL=0
SPL=1
-20
-30
-40
-50
-60
1.E+03
1.E+02
1.E+04
FREQUENCY(Hz)
Figure 1:
TX overall response without pre-emphasis.
20
10
GAIN(dB)
0
-10
-20
-30
-40
-50
-60
1.E+02
1.E+03
1.E+04
FREQUENCY(Hz)
Figure 2:
RX overall response without de-emphasis.
MS1409-E-01
2013/12
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[AK2346B]
• Audio path frequency response (Emphasis:on)
20
10
GAIN(dB)
0
-10
SPL=0
SPL=1
-20
-30
-40
-50
-60
1.E+02
1.E+03
1.E+04
FREQUENCY(Hz)
Figure 3:
TX overall response with pre-emphasis.
20
10
GAIN(dB)
0
-10
-20
-30
-40
-50
-60
1.E+02
1.E+03
1.E+04
FREQUENCY(Hz)
Figure 4:
RX overall response with de-emphasis.
MS1409-E-01
2013/12
- 12 -
[AK2346B]
4) Scrambler Characteristics (Scrambler: on, Emphasis: off, COMPANDOR: off)
Parameter
Condition
Min.
Typ.
Max.
Carrier Frequency
3.388
Modulated Output
Level
TXINO to MOD, RXINO to RXAF
High Frequency
Rejection Level
TXINO to MOD, RXINO to RXAF
Carrier Signal
Leakage Level
TXINO to MOD, RXINO to RXAF
Original Signal
Leakage Level
TXINO to MOD, RXINO to RXAF
Input level
1.0kHz -10dBx
Measuring-freq. 2.388kHz
RX Signal Level
-10
Input level
1.0kHz -10dBx
Measuring-freq. 4.388kHz
Input level
No signal
Measuring-freq. 3.388kHz
Input level
1.0kHz -10dBx
Measuring-freq. 1.0kHz
5) MSK MODEM Characteristics
Parameter
Condition
TX Signal Level
@MOD
TX Signal Distortion
-12
1.2kHz signal out
@MOD
1.2kHz signal out
@RXINO
1.2kHz signal out
-8
dBx
-50
dBx
-50
dBx
-50
dBx
Typ.
Max.
Units
-12
-11
-10
dBx
-32
dB
-1
dBx
-11
Notes
kHz
Min.
-17
MS1409-E-01
Units
Notes
2013/12
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[AK2346B]
12. Level Diagram
1) TX audio system : TXRX=0
MSK
Modulator
f=1kHz
TXINO
TXA1
TXIN
G = 30dB
EXTLMIN
VR1
Compressor
Pre-emphasis
+4.5
dB
0
-6.0
Crosspoint
-10dBx
0dB
TXHPF
0dB
Splatter
+VR2
Limitter
SMF
+3.0
dB
0
-9.2
-7.6dBx
MOD
0dB
Scrm
/Descrm
0dB
dBx
10
0
0
-5
-5.5
-7.0
-10dBx (Audio)
-10
-10
-10
-11
-11dBx (MSK)
-19.2
-16
-20
-27
-27dBx
-30
-30dBx
-30
-40
-44
-50
-50
-60
-70
-80
-90
2) RX audio system : TXRX=1
f=1kHz
RXIN
RXLPFO
RXINO
VR3
RXA1
G = 20dB
0
+3.5
dB
-4.0
EXPOUT
RXLPF
RXHPF
0dB
+5dB
De-emphasis
Expander
-5dB
Crosspoint
-10dBx
Scrm
/Descrm
VR4
RXA2
+4.5
dB
0
-18.0
G = 0dB
RXAF
-5dB
dBx
10
0
0
-5
-5
-10
-20
-25
-10
-14
-10
-5.5
-10dBx (Typ.)
-20
-25
-28
-25
-30
-40
0dBx (Max.)
-6.5
-40
-30
-40dBx
-45
-50
-50dBx
-50
-60
“dBx” is standardized unit for 1.9V to 5.5V operation, 0dBx=-5+20log(VDD/2)dBm, 0dBm=0.775Vrms.
MS1409-E-01
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[AK2346B]
13. Serial Interface Configuration
1) Register Configuration
Address
Data
Function
D7
D6
D5
D4
D3
D2
D1
D0
Control register 1
BS3
BS2
BS1
TXRX
TXSW2
TXSW1
RXSW
FSL
1
Control register 2
-
-
TC
EM
PCONT
SPL
MSKSL
FCLN
1
0
Volume register 1
-
-
-
-
-
VR12
VR11
VR10
0
1
1
Volume register 2
-
-
VR25
VR24
VR23
VR22
VR21
VR20
1
0
0
Volume register 3
-
VR33
VR32
VR31
VR30
VR42
VR41
VR40
1
0
1
MODEM register 1
Lower 8 bit of MODEM Flame pattern
1
1
0
MODEM register 2
Upper 8 bit of MODEM Flame pattern
1
1
1
Test register
TST1
TST0
-
-
-
MODEM register 3
A2
A1
A0
0
0
0
0
0
0
TST7
TST6
TST5
TST4
TST3
TST2
MODEM Receive data
2) Register Map
2.1) Control Register 1
Address
Data
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
BS3
BS2
BS1
TXRX
TXSW2
TXSW1
RXSW
FSL
0
0
1
1
1
1
1
Reset
0
2.1.1) Operation mode setting
BS3
BS2
BS1
Mode
OSC, AGND
TX, RX, Audio
MODEM
0
0
0
Mode0
OFF
OFF
OFF
0
0
1
Mode1
ON
OFF
OFF
0
1
0
Mode2
ON
ON
OFF
0
1
1
Mode3
ON
OFF
ON
1
0/1
0/1
Mode4
ON
ON
ON
2.1.2) TX, RX Setting
Data
Function
TXRX
TX, RX Switch
RXSW
RX Audio
FSL
Operation
Notes
0
1
TX Operation
Note 1
RX Operation
Note 2
Note 3
Mute
Active
Note 4
FD enable
RDF enable
RDF/FD Switch
2.1.3) TX audio path setting
Operation
TXSW2
TXSW1
0
0
External Tone Operation
0
1
MODEM Operation
(MSK Modulator --- Splatter)
1
0
Audio Operation
(HPF --- Limiter --- Splatter)
1
1
Mute
(AGND --- Limiter --- Splatter)
Notes
(EXTLIMIN --- Limiter --- Splatter)
MS1409-E-01
2013/12
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[AK2346B]
Note 1: TXIN to EXPOUT path is available by setting TXRX=0 and RXSW=1 in register.
However, Scrambler/Descrambler circuit does not work properly on this setting, so please set
PCONT=1 (disable). To set RXSW=0 makes EXPOUT pin mute in operation.
Note 2: RXIN to MOD path is available by setting TXRX=1 and TXSW2/TXSW1=1/0 in register.
However, Scrambler/Descrambler circuit does not work properly on this setting, so please set
PCONT=1 (disable). To set TXSW2/TXSW1=1/1 makes MOD pin mute in operation.
Note 3: Please set a gain level properly in each circuit block according to level diagram in page 14.
Note 4: RXLPFO pin does not be controlled by setting RXSW=0. It is normally active in RX mode.
2.2) Control Register 2
Address
Data
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
-
-
TC
EM
PCONT
SPL
MSKSL
FCLN
1
1
1
1
0
0
Reset
Data
Operation
Function
0
1
OFF (disable)
ON (enable)
TC
COMPANDOR
SPL
Splatter
cut-off frequency
2.55kHz
3.0kHz
MSKSL
MODEM data rate
2400bps
1200bps
FCLN
MODEM flame detect
ON (enable)
OFF (disable)
Notes
Notes
Operation
EM
PCONT
1
1
Emphasis : ON (enable)
Scrambler : OFF(disable)
0
1
Emphasis : OFF(disable)
Scrambler : OFF(disable)
0/1
0
Emphasis : OFF(disable)
Scrambler : ON (enable)
2.3) Volume Register 1
Address
Data
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
-
-
-
-
-
VR12
VR11
VR10
1
0
0
Reset
VR12
0
0
0
0
1
1
1
1
VR11
0
0
1
1
0
0
1
1
VR10
0
1
0
1
0
1
0
1
MS1409-E-01
VR1 Gain (dB)
-6.0
-4.5
-3.0
-1.5
0.0
+1.5
+3.0
+4.5
2013/12
- 16 -
[AK2346B]
2.4) Volume Register 2
Address
Data
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
-
-
VR25
VR24
VR23
VR22
VR21
VR20
1
1
0
0
0
0
Reset
VR25
VR2 Gain (dB)
-6.0
0.0
0
1
VR24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VR23
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VR22
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VR21
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MS1409-E-01
VR20
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VR2 Gain (dB)
-3.2
-3.0
-2.8
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
+0.2
+0.4
+0.6
+0.8
+1.0
+1.2
+1.4
+1.6
+1.8
+2.0
+2.2
+2.4
+2.6
+2.8
+3.0
2013/12
- 17 -
[AK2346B]
2.5) Volume Register 3
Address
Data
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
-
VR33
VR32
VR31
VR30
VR42
VR41
VR40
1
0
0
0
1
0
0
Reset
VR33
VR32
VR31
VR30
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VR42
0
0
0
0
1
1
1
1
VR41
0
0
1
1
0
0
1
1
VR40
0
1
0
1
0
1
0
1
MS1409-E-01
VR3 Gain (dB)
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
+0.5
+1.0
+1.5
+2.0
+2.5
+3.0
+3.5
VR4 Gain (dB)
-18.0
-4.5
-3.0
-1.5
0.0
+1.5
+3.0
+4.5
2013/12
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[AK2346B]
2.6) MODEM Register 1,2 (Reset : Low Power Radio)
Address
Data
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
F07
F06
F05
F04
F03
F02
F01
F00
1
0
1
0
1
0
0
0
F15
F14
F13
F12
F11
F10
F09
F08
0
0
0
1
1
0
1
1
Reset
1
1
0
Reset
2.7) Test Register
Address
Data
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
1
1
1
1
1
1
1
1
Reset
Data
Function
TST7..0
Test Mode
Operation
0
1
Test mode
Normal mode
2.8) MODEM Register 3
Address
Notes
Data
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
Data
RD7…0
Function
MSKSL=”0”
MSKSL=”1”
MODEM Receive data
0
2.4kHz
1.8kHz
1
1.2kHz
1.2kHz
MS1409-E-01
Notes
RD7 is the first
received data.
2013/12
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[AK2346B]
14. Digital AC timing
1) Serial Interface Timing
Parameter
Symbol
Master clock frequency
Clock pulse width 1
Clock pulse width 2
DI/O Set up time
DI/O Hold time
DIR Set up time
DIR Hold time
DIR Falling to SCLK Falling time
SCLK Input rising time
SCLK Input falling time
Min.
fclk
ta
tb
tc
td
te
tf
tg
th
ti
Typ.
Max.
3.6864
Units
MHz
500
500
100
100
100
100
100
ns
ns
ns
250
250
ns
tb
ta
SCLK
tc
td
A2
DI/O
A1
D7
A0
D1
D0
tf
te
DIR
tg
th
ti
0.8VDD
0.2VDD
SCLK waveform
MS1409-E-01
2013/12
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[AK2346B]
2) MSK Modulator Timing
Parameter
TXSW2 Falling to TCLK Rising MSKSL=”0”
MSKSL=”1”
TCLK Period
Symbol
T1
MSKSL=”0”
MSKSL=”1”
TXSW2 Rising to TXSW1 Falling
TDATA Set up time
TDATA Hold time
TDATA Hold time2
Min.
T2
T3
TS
TH
TH2
Typ.
208.3
416.7
416.7
833.3
Max.
Units
us
us
2
1
1
2
ms
us
TCLK
TXSW1
T3
Register data
T1
T2
TXSW2
TH2
TS
TH
TDATA
(MSKSL=”0”)
MOD
Audio Signal
Audio Signal
(MSKSL=”1”)
Note: The timing of setting the internal registers TXSW1 and TXSW2 is synchronized with the falling
edge of DIR pin.
3) MSK Demodulator Timing
Parameter
RCLK Period and FD pulse width
MSKSL=”0”
MSKSL=”1”
RDF Falling to SCLK Falling time
SCLK Rising to RDF Falling time
Symbol
Min.
T
tj
tk
MS1409-E-01
Typ.
416.7
833.3
100
600
Max.
Units
us
ns
2013/12
- 21 -
[AK2346B]
DIR
tj
SCLK
DI/O
(Input)
FSL=FCLN=0
FCLN=0
RXSW=0
FSL=1
DI/O
(Output)
RD7~RD0
FSL
(Internal Register)
FCLN
FCLN=1 automatically
(Internal Register)
RCLK_n
(Internal Node)
T
RDATA_n
MD7
MD6 MD5
MD4
MD3 MD2
MD1
MD0
MD7
MD6
MD5
MD4
MD3 MD2
MD1
MD0 MD7
MD6
(Internal Node)
T
FD_n
(Internal Node)
tk
RDF_n
(Internal Node)
MS1409-E-01
2013/12
- 22 -
ASAHI KASEI
[AK2346B]
15. MSK MODEM Description
1) MSK Modulator control flow
MSK data transmitter, Modulator interfaces with TCLK, TDATA and MOD pins and also TXRX,
TXSW2 and TXSW1 register as below.
TXRX=0
TXSW2=0
TXSW1=1
: MSK data transmit start
MSK data are transmitted
synchronized to TCLK clock
: MSK data transmitting
N
Required bit
number completed
Y
Y
: MSK data transmit compete
TXSW2=1
Waiting 2ms or more
: Switching to audio signal
TXSW1=0
(1)
(2)
(3)
(4)
Setting TXRX=0, TXSW2=0 and TXSW1=1, MSK data transmit is provided.
A 1200/2400Hz clock is put out from TCLK pin. Synchronizing with the rising edge of TCLK,
AK2346B reads the MSK transmit data from TDATA pin and puts out them to MOD pin.
After transmitting the necessary bit number, please set TXSW2=1
Afterwards, before switching to audio signal mode, please wait for at least 2ms after setting
TXSW2=1 to complete sending the MSK data final data bit transmit. Then set TXSW1=1.
MS1409-E-01
2013/12
- 23 -
ASAHI KASEI
2)
[AK2346B]
MSK Demodulator control flow
MSK data receiver, Demodulator interfaces with RXIN, RDF/FD, SCLK, DI/O and DIR pins and
also FCLN, FSL, and RXSW registers as below.
N
FCLN=0
: Setting flame detect (FD) enable
FSL=0
: Setting for FD signal put out from
RDF/FD pin.
: Synchronized frame pattern
detect or not ?
RDF/FD “Low”
Y
: FD is disable automatically
FCLN=1 (automatically)
: Receive audio mute
RXSW=0
: Setting for received flag (RDF) signal
put out from RDF/FD pin.
FSL=1
N
RDF/FD “Low”
: 8 bit data received or not ?
Y
Reading receive data
N
Have all receive data
been read out?
: Having read 8bit data, RDF/FD pin
puts out high level.
Y
FCLN=0
: Waiting for the next synchronized
flame.
(1)
Setting FCLN=0 and FSL=0 for flame detect mode and also SCLK pin sets high level
and DIR pin sets low level, RDF/FD pin puts out high level and wait for synchronized frame.
(2)
After a synchronized frame is detected, RDF/FD pin works as frame detect (FD) mode.
FD goes to low level during the period of time “T”, then FCLN is sets to “1” automatically.
(3)
Monitoring low level of RDF/FD pin, set RXSW=0 for audio signal mute. Then set FSL=1 for
received flag (RDF), signal put out from RDF/FD pin.
MS1409-E-01
2013/12
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ASAHI KASEI
[AK2346B]
(4)
After 8 bit received data (MD7…0) have been entered to the internal buffer from node RDATA,
RDF/FD pin goes to low level as RDF mode.
(5)
After CPU detects this low level at RDF/FD pin, please puts in 8 clock to SCLK pin. Then
modulated data (RD7…0) put out from DI/O pin synchronized with falling edge of SCLK clock.
(6)
After 8 clock have been put into SCLK pin completely, RDF/FD pin goes to high level that
shows all modulated data coming from DI/O pin.
(7)
By repeating the steps (4), (5), (6), the data come out from DI/O pin continuously.
(8)
After the necessary data have been read, DIR pin sets to high level and FCLN=0. Then
internal node RCLK and RDATA are set to “1” for initializing and system waits for the next
synchronization frame data.
This frame detection circuit does not have reset function. In case of stopping the sequence
during the steps (1) to (8), please set again from the first step (1). Especially, when RDF/FD
pin goes out low level on frame detecting, FCLN register is sets to “1” automatically as written
in (2). If you set FCLN=0 during this operation, the date set “0” is ignored. So please set the
data again after RDF/FD pin puts out high level.
When frame detection is not used, please set FCLN=1 and FSL=1 from the beginning. In that
case, monitoring the low level put out from RDF/FD pin, then puts 8 clock into the SCLK pin as
written in step (4). In this sequence, please program the frame detecting operation by
microprocessor.
MS1409-E-01
2013/12
- 25 -
ASAHI KASEI
[AK2346B]
16. Recommended External Application Circuits
1) TXA1 Amplifier
This is an operational amplifier required for typical transmit microphone. The gain should be less
than 30dB. To eliminate high frequency noise component over than 100kHz from input signal,
please compose 1st or 2nd order anti-aliasing filter. The following simplified schematic shows an
example of 2nd order anti-aliasing filter that has 30dB gain and 10kHz cut-off frequency.
4
C1=0.47uF
TXINO
C2=33pF
R3
C2
R1 C1
C3=2200pF
_
+
3
TXIN
R2
C3
TXA1
R1=R2=10kΩ
R3=330kΩ
AGND
LSI
2) EXTLIMIN pin configuration
To eliminate an external DC offset must be decoupled by capacitor to signal input.
6
EXTLIMIN
C=0.047uF
C
LSI
3) RXA1 Amplifier
This is an operational amplifier suitable for receive gain adjuster and anti-aliasing filter to
eliminate high frequency noise component over 100kHz The gain should be less than 20dB.
The following simplified schematic shows an example of 2nd order anti-aliasing filter that has
20dB gain and 39kHz cut-off frequency.
22
C1=0.47uF
RXINO
C2=33pF
R3
C2
R1 C1
C3=560pF
_
+
23
RXIN
R2
C3
RXA1
R1=10kΩ
R2=9.1kΩ
AGND
R3=100kΩ
LSI
MS1409-E-01
2013/12
- 26 -
ASAHI KASEI
[AK2346B]
4) RXA2 Amplifier
This is an operational amplifier suitable for receive gain adjuster and smoothing filter to eliminate
461kHz sampling clock component included in EXPOUT pin. The following simplified schematic
shows an example of 1st order Low-pass filter that has 0dB gain and 19kHz cut-off frequency.
EXPOUT
18
C1
C1=0.022uF
R1
RXAFIN
19
C2=150pF
C2
_
R2
R1=R2=56kΩ
+
RXAF
20
RXA2
LSI
5) Power supply stabilizing capacitors
To connect capacitors between VDD and VSS pin reduce the ripple and noise included in power
supply. These capacitors are mounted close to the device pins.
VDD
17
VDD
C1=22uF (Electrolytic cap)
C2
C1
C2=0.1uF (Ceramic cap)
VSS
8
VSS
LSI
6) AGND, AGNDIN pin stabilizing
Please decouple to VSS level by the 0.3uF or larger capacitor. These capacitors are mounted
close to the device pins.
1
AGNDIN
2
AGND
C
C
C=1uF
LSI
MS1409-E-01
2013/12
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ASAHI KASEI
[AK2346B]
7) Clock Generation
The clock source can be chosen either internally generating with crystal oscillator or externally
supplied.
Figure 1 shows internally generating using the on-chip amplifier, a crystal oscillator, resistor and
capacitors. AK2346B is designed to get a stable oscillation for the electrical equivalent circuitry of
quartz crystal unit: resonance resistance≤150Ω(Max.) and shunt capacitance≤5pF(Max.).
Recommended external capacitance is 22pF due not to exceed the load capacitance≤16pF
(5pF+22pF//22pF). These external components are mounted close to the device pins.
Figure 2 and 3 show externally supplied example of clock generation. The first gate of XIN pin is
composed of non-voltage-tracking type amplifier that threshold level is 0.8V.
In case the high level of input clock amplitude equals or greater than 1.5V and the low level
equals or smaller than 0.5V, recommended configuration is Figure 2.
In case clock peak-to-peak level equals or greater than 0.2V and equals or smaller than 1.0V,
recommended configuration is Figure 3.
Please be careful not to let the clock amplitude exceed the absolute maximum ratings.
External Clock IN
22pF
XIN
16
XIN
15
XOUT
3.6864MHz
3.6864MHz
1MΩ
XOUT
22pF
LSI
LSI
Figure 2
Figure 1
XIN
0.01uF
External Clock IN
3.6864MHz
1MΩ
XOUT
LSI
Figure 3
MS1409-E-01
2013/12
- 28 -
ASAHI KASEI
[AK2346B]
8) LIMLV pin configuration
LIMLV pin is an adjuster for the limit level of audio signal at baseband. It operates in left open or
applying a DC voltage.
In case of left open, limit level sets predetermined value depending on the VDD level, which can
be calculated using the following formula:
HVref = 0.256 x (VDD - AGND) [Vo-p]
For example at VDD=3V HVref=0.256 x (3.0 - 1.5)=0.384Vo-p
So typical peak-to-peak limit level is calculated as 1.5±0.384Vp-p
In case of applying a DC voltage higher than AGND(=1/2VDD) level, the limit level can be
adjusted according to following formula:
Vlimit = AGND ± (LIMLV-AGND)
For example at VDD=3V, typical limit level: Vlimit is calculated as below.
LIMLV = 1.6V → Vlimit = 1.5 ± 0.1V
1.7V →
1.5 ± 0.2V
1.8V →
1.5 ± 0.3V
1.9V →
1.5 ± 0.4V
1.933V →
1.5 ± 0.433V (corresponding to –6.6dBx (Max.) )
Limiter circuitry operates at AGND level common. In case of applying a DC voltage usage,
recommended external configuration is composed of VDD and AGND level separation with
resistors. Typical resistor value is R1+R2=51kΩ
VDD
R1
5
LIMLV
R2
R1+R2
AGND
VSS
LSI
MS1409-E-01
2013/12
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ASAHI KASEI
[AK2346B]
17. Packaging
• Marking
AKM
AK2346
YWWLZ
[ Contents of YWWLZ ]
Y:
Last digit of calendar year. (Year 2011->1, 2012->2)
WW: Manufacturing week number.
L:
Lot identification, given to each product lot which is made in a week.
LOT ID is given in alphabetical order (A, B, C…).
Z:
Assembly plant code
8.40 Max
13
1
12
5.9 Max
24
7.90±0.20
0.22±0.05
0° to 8°
0.13 M
0.65±0.08
0.60±0.15
• 24-pin SSOP Mechanical Outline
0.30±0.10
Unit : mm
MS1409-E-01
2.10 Max
0.10±0.10
0.10
2013/12
- 30 -
ASAHI KASEI
[AK2346B]
18. Important Notice
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of AKM or any third party with respect to the information
in this document. You are fully responsible for use of such information contained in this document in
your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES
INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION
IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human
life, bodily injury, serious property damage or serious public impact, including but not limited to,
equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment,
equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment,
equipment used to control combustions or explosions, safety devices, elevators and escalators, devices
related to electric power, and equipment used in finance-related fields. Do not use Product for the above
use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or
corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in
this document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations
and follow the procedures required by such laws and regulations. The Products and related technology
may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation, the
EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in
this document shall immediately void any warranty granted by AKM for the Product and shall not create
or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
MS1409-E-01
2013/12
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