Practical debugging and testing BGA by David Kim Paramit Co. Oct. 11th, 2007 PCB1 $4.5k with BGA’s ( $50~$800 each) PCB2 $3.5k with BGA’s ( $50~$800 each) PCB3 $5k with BGA’s ( $100~$700 each) MORE’s with BGA PCB: • • • • More PCB’s with BGA’s More expensive PCB’s with expensive BGA’s More tests on BGAs More complicated tests (BSCAN and Silicon nail test) ICT: • • • • More false BGA failures More rework on false BGA failures More rework and replacement cost on false BGA failures More troubleshooting time on false BGA failures More false BGA failure Î More Rework and materials Î More Time and $ = $ Loss Less false BGA failures Î Less rework and materials Î Less Time and $ cost = $ Profit Testing BGA • “pins” < “connectcheck” < “testjet” (<VTEP) < BSCAN •AOI / SJ50 < X-Ray/5Dx AXI Test coverage on BGA testjet/VTEP has less test coverage on Shielded BGA and micro BGA. BGA Rework • • • • Bake - takes long hours. 8 ~ 24Hs Reflow Reball - not as good as a new one Replace - expensive BGA • Retest - may still show false failure False BGA failures with BSCAN test Caused by • Contact problem (dirty nail bed, dirty probe, contaminated test vias, etc) • Signal delay caused by contact resistance • Missing and improper disables • Random initial condition after power-on • Unpredictable bus contention during the output test • Other defected devices • etc. Verifying BGA failures • • • • Check Test target(s) - probe, test via(pad) Continuity from Test point to BGA pin R and Diode test comparing with the KGB Testing only failed pin in input mode for input/bidirectional pin or in output mode for output pin. • Test with longer vector cycle/receive delay • Set TCLK at dh3.3/dl-0.2 and slew rate 250 R and Diode test on failed pin to Pwr/GND • R test Internal pull-up R, pull-down R, or internal circuit impedance to Power or Ground • Diode test CMOS SCR Latch-up resistant circuit as ESD protection on bidirectional bus has diodes to power and ground. Separating output-only pins • Separate output-only pins from each connect test. • Use “test inputs only” option for bidirectional pins and input-only pins • Create a script to split “digital/unn_connect_x” into “digital/unn_connect_x_out” and “digital/unn_connect_x_in” ex. $ dksplite_bscan u14 $ dkrdtest_bga_pin u14.ac5 !"tundra310.bsd", "HPBGA_304_23x23", no -- STD_1149_1_1994 VHDL Package and Package Body -------------------------------------------------------------------------entity tsi310 is generic (PHYSICAL_PIN_MAP : string := "HPBGA_304_23x23"); -- Port List port ( S_DEVSEL : inout bit; <******* S_FRAME : out bit; <******* S_GNT1REQ : out bit; <******* S_INT_ARB_EN : out bit; <******* : JTG_TCK : in bit; JTG_TDI : in bit; JTG_TDO : out bit; JTG_TRST_b : in bit; JTG_TMS : in bit ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of tsi310: entity is "STD_1149_1_1993"; attribute PIN_MAP of tsi310: entity is PHYSICAL_PIN_MAP; constant HPBGA_304_23x23: PIN_MAP_STRING:= "GND : (A1,A6,A10,A116,D20,F1,F23), " & "VDD2 : (A8,A12,A22,C5,D5,D7,D17,D19,E4,E20,G4,G20,H23,M1,T1), " & "S_DEVSEL "S_FRAME "S_GNT1REQ "S_INT_ARB_EN : : : : AA9 , " & AA1 , " & AB4 , " & AA19 , " & <******* <******* <******* <******* "TEST_CEO : Y23 " ; end STD_1149_1_1994; -- End of 1149.1-1994 Package !itl “digital/u3d1_connect_c” connect "u3d1" ground bounce suppression family "TTL_3V3" on !IPG: Connect test generated with CONNECTMAX value of 25 test inputs only !* tests bidirectional pins as input and ignores Output pins. chain "u3d1_u3d1" tdi "PCIX1_TDO" tdo "CE_TDO" tms "CE_TMS" family "CMOS_3V3" tck "CE_TCK5" devices "u3d1", "_bsdl_lib/tundra310_ok.bsd", "HPBGA_304_23x23", no end devices end chain vector cycle 900n receive delay 800n set ref on nodes "CE_TCK5" to dh 3.3, dl -0.2 set slew rate on nodes "CE_TCK5" to 250 nodes fixed low "NETIFPCIXPD_OPAQUE_EN" test "u3d1.AA18" node node node node "NETIFS_AD0" "NETIFS_GNT1_L" "NETIFS_GNT2_L" "NETIFS_GNT5_L" end nodes end connect hybrid hybrid hybrid hybrid test test test test "u3d1.AA9" "u3d1.AA19" "u3d1.AB1" "u3d1.AB4" !*bi !*out !*out !*out •itl without "test inputs only" -----------------------------------------------------------------------------AGILENT 3070 VCL Wed Sep 26, 2007 09:40:12 AM digital/u3d1_connect_bx.vcl -----------------------------------------------------------------------------C O M P I L A T I O N S U M M A R Y ------------------------------------4050 vectors executed. 27 Vector RAM slots used, 0 % full. 1026 Sequence RAM slots used, 0 % full. 110 Directory RAM slots used, 0 % full. P I N S T A T E R E P O R T ------------------------------DEVICE PIN STATES PIN NODE TYPE EXECUTED -----------------CE_TCK5 DRIVE D0 D1 CE_TDO RECEIVE R0 R1 CE_TMS DRIVE D0 D1 CE_TRST_L DRIVE D1 CENTRALPU_OE_B DRIVE D0 HARDRESET_L DRIVE D1 NETIF_STITCH DRIVE D1 NETIFS_AD0 **bi** BIDIRECTIONAL D0 D1 R0 R1 NETIFS_GNT1_L **out* RECEIVE R0 R1 NETIFS_GNT2_L **out* RECEIVE R0 R1 NETIFS_GNT5_L **out* RECEIVE R0 R1 PCIX1_TDO DRIVE D0 D1 * itl with "test inputs only" -----------------------------------------------------------------------------AGILENT 3070 VCL Wed Sep 26, 2007 09:42:45 AM digital/u3d1_connect_bx.vcl -----------------------------------------------------------------------------C O M P I L A T I O N S U M M A R Y ------------------------------------2504 vectors executed. 24 Vector RAM slots used, 0 % full. 764 Sequence RAM slots used, 0 % full. 72 Directory RAM slots used, 0 % full. P I N S T A T E R E P O R T ------------------------------DEVICE PIN STATES PIN NODE TYPE EXECUTED -----------------CE_TCK5 DRIVE D0 D1 CE_TDO RECEIVE R0 R1 CE_TMS DRIVE D0 D1 CE_TRST_L DRIVE D1 CENTRALPU_OE_B DRIVE D0 HARDRESET_L DRIVE D1 NETIF_STITCH DRIVE D1 NETIFS_AD0 **bi** BIDIRECTIONAL D0 D1 NETIFS_GNT1_L **out* RECEIVE NETIFS_GNT2_L **out* RECEIVE NETIFS_GNT5_L **out* RECEIVE PCIX1_TDO DRIVE D0 D1 Improving BGA test for less false failures • • • • • • • • put “pins” test at the beginning of the test apply “connectcheck” to each BGA as well as “testjet” (VTEP is better). apply “vector cycle” and “receive delay” ( 500n~1000n/400n~900n) with the regular fixture maintenance. Separate output-only pins from inputs-only or bidirectional pins Test bidirectional pins as only input with “test inputs only” option. (Use dktools to split in/out/bi/single pin automatically.) Separate the unstable pin(s) from other pins. ( good for pins with “!IPG: Disable problems, …..”) Use debugging tool for BGA failures to verify the result as false failure or true failure, such like testing R and diode junction of the failed pin to power and ground. Option: X-ray test with 5Dx or others, if needed. Conclusion • By improving the existing ICT test for BGA’s, the number of false failures is reduced. (more than 50%, depending on the program quality and the complexity of the circuit) . • False BGA failures can be efficiently verified with improved BSCAN test and R/Diode test. • BSCAN test can be efficiently developed and debugged more stable with the automated scripts. ÎShorter development time and less sustaining time ÎLess false failures Î Less rework and replacement Î Time and $ saving Need dktools and my help ? David Kim Test Development Manager Paramit Co. Ph) 408-782-2445 [email protected]