ETC SPT7910SCJ

SPT7910
12-BIT, 10 MSPS, ECL, A/D CONVERTER
FEATURES
APPLICATIONS
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Monolithic
12-Bit 10 MSPS Converter
67 dB SNR @ 500 kHz Input
On-Chip Track/Hold
Bipolar ±2.0 V Analog Input
Low Power (1.4 W Typical)
5 pF Input Capacitance
ECL Outputs
Radar Receivers
Professional Video
Instrumentation
Medical Imaging
Electronic Warfare
Digital Communications
Digital Spectrum Analyzers
Electro-Optics
GENERAL DESCRIPTION
The SPT7910 analog-to-digital converter is industry's first
12-bit monolithic analog-to-digital converter capable of sample
rates greater than 10 MSPS. On board input buffer and track/
hold function assures excellent dynamic performance without the need for external components. Drive requirement
problems are minimized with an input capacitance of only
5 pF.
Inputs and outputs are ECL to provide a higher level of noise
immunity in high speed system applications. An overrange
output signal is provided to indicate overflow conditions.
Output data format is straight binary. Power dissipation is
very low at only 1.4 watts with power supply voltages of +5.0
and -5.2 volts. The SPT7910 also provides a wide input
voltage range of ±2.0 volts.
The SPT7910 is available in a 32-lead ceramic sidebrazed
DIP package and in die form. A commercial temperature
range of 0 to +70 °C is currently offered.
BLOCK DIAGRAM
VIN
INPUT
BUFFER
4-BIT FLASH
CONVERTER
4
ERROR
CORRECTION,
DECODING
AND
OUTPUT ECL
DRIVERS
ANALOG GAIN
COMPRESSION
PROCESSOR
TRACK AND HOLD
AMPLIFIERS
ASYNCHRONOUS
SAR
8
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370
DIGITAL
OUTPUT
12
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VCC ............................................................... -0.3 to +6 V
VEE ............................................................... +0.3 to -6 V
Output
Digital Outputs .............................................. 0 to -30 mA
Temperature
Operating Temperature ................................... 0 to 70 °C
Junction Temperature ........................................... 175 °C
Lead Temperature, (soldering 10 seconds) .......... 300 °C
Storage Temperature ................................ -65 to +150 °C
Input Voltages
Analog Input ............................................... VFB≤VIN≤VFT
VFT, VFB. ................................................... +3.0 V, -3.0 V
Reference Ladder Current ..................................... 12 mA
Note:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VCC =+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=10 MHz, 50% clock duty cycle,
unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy (+25 °C)
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
Analog Input
Input Voltage Range
Input Bias Current
Input Resistance
Input Capacitance
Input Bandwidth
+FS Error
-FS Error
Reference Input
Reference Ladder Resistance
Reference Ladder Tempco
Timing Characteristics
Maximum Conversion Rate
Overvoltage Recovery Time
Pipeline Delay (Latency)
Output Delay
Aperture Delay Time
Aperture Jitter Time
Dynamic Performance
Effective Number of Bits
fIN=500 kHz
fIN=1.0 MHz
fIN=3.58 MHz
SPT
TEST
CONDITIONS
TEST
LEVEL
± Full Scale
250 kHz Sample Rate
VIN=0 V
3 dB Small Signal
MIN
12
SPT7910
TYP
V
V
VI
±2.0
±0.8
Guaranteed
VI
VI
VI
V
V
V
V
±2.0
30
300
5
120
±5.0
±5.0
100
VI
V
500
VI
V
IV
V
V
V
10
MAX
UNITS
Bits
LSB
LSB
60
V
µA
kΩ
pF
MHz
LSB
LSB
800
0.8
Ω
Ω/°C
20
MHz
ns
1
5
1
5
10.2
10.0
9.5
Clock Cycle
ns
ns
ps-RMS
Bits
Bits
Bits
SPT7910
2
3/11/97
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VCC =+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=±2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=10 MHz, 50% clock duty cycle,
unless otherwise specified.
PARAMETERS
Dynamic Performance
Signal-To-Noise Ratio
(without Harmonics)
fIN=500 kHz
fIN=1 MHz
fIN=3.58 MHz
Harmonic Distortion1
fIN=500 kHz
fIN=1.0 MHz
fIN=3.58 MHz
Signal-to-Noise and Distortion
fIN=500 kHz
fIN=1.0 MHz
fIN=3.58 MHz
Spurious Free Dynamic Range2
Differential Phase3
Differential Gain3
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT7910
TYP
+25 °C
TMIN to TMAX
+25 °C
TMIN to TMAX
+25 °C
TMIN to TMAX
I
IV
I
IV
I
IV
64
58
64
58
62
58
67
61
66
60
64
60
dB
dB
dB
dB
dB
dB
+25 °C
TMIN to TMAX
+25 °C
TMIN to TMAX
+25 °C
TMIN to TMAX
I
IV
I
IV
I
IV
63
59
63
59
59
57
66
62
65
61
61
59
dB
dB
dB
dB
dB
dB
+25 °C
TMIN to TMAX
+25 °C
TMIN to TMAX
+25 °C
TMIN to TMAX
+25 °C
+25 °C
+25 °C
I
IV
I
IV
I
IV
V
V
V
60
55
60
55
57
54
63
58
62
57
59
56
74
0.2
0.7
dB
dB
dB
dB
dB
dB
dB
Degree
%
VI
VI
VI
VI
IV
IV
-1.1
Digital Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Pulse Width Low (CLK)
Pulse Width High (CLK)
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
Power Supply Requirements
Voltages VCC
-VEE
Currents ICC
-IEE
Power Dissipation
Power Supply Rejection Ratio
50 Ω to -2 V
50 Ω to -2 V
Outputs Open
(5 V±0.25 V, -5.2 V ±0.25 V)
-500
-500
30
30
±200
±300
VI
VI
-1.1
-0.8
-1.8
IV
IV
VI
VI
VI
V
+4.75
-4.95
150
125
1.4
1.0
MAX
UNITS
300
V
V
µA
µA
ns
ns
-1.5
V
V
-1.5
+750
+750
+5.25
-5.45
190
160
1.8
V
V
mA
mA
W
LSB
Typical thermal impedances (unsoldered, in free air): 32L sidebrazed DIP. θ ja = 50 °C/W.
164 distortion BINS from 4096 pt FFT.
2f
IN = 1 MHz.
3f
IN = 3.58 and 4.35 MHz.
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TEST LEVEL
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Figure 1A: Timing Diagram
OUTPUT
DATA
100% production tested at the specified temperature.
II
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
AA AA
AA AA AAA
A AAA
t pwH
CLK
I
N+1
N
CLK
TEST PROCEDURE
AA
A
N+2
t pwL
td
N-2
DATA VALID
N
N-1
DATA VALID
N+1
Figure 1B: Single Event Clock
AA
A
AA
A
AAAA
CLK
CLK
td
OUTPUT
DATA
DATA VALID
Table I - Timing Parameters
PARAMETERS
SPT
DESCRIPTION
MIN
TYP
MAX
UNITS
td
CLK to Data Valid Prop Delay
-
5
tpwH
CLK High Pulse Width
30
-
300
ns
tpwL
CLK Low Pulse Width
30
-
-
ns
ns
SPT7910
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3/11/97
SPECIFICATION DEFINITIONS
APERTURE DELAY
DIFFERENTIAL NONLINEARITY (DNL)
Aperture delay represents the point in time, relative to the
rising edge of the CLOCK input, that the analog input is
sampled.
Error in the width of each code from its theoretical value.
(Theoretical = VFS/2N)
INTEGRAL NONLINEARITY (INL)
APERTURE JITTER
Linearity error refers to the deviation of each individual code
(normalized) from a straight line drawn from -Fs through +Fs.
The deviation is measured from the edge of each particular
code to the true straight line.
The variations in aperture delay for successive samples.
DIFFERENTIAL GAIN (DG)
A signal consisting of a sine wave superimposed on various
DC levels is applied to the input. Differential gain is the
maximum variation in the sampled sine wave amplitudes at
these DC levels.
OUTPUT DELAY
Time between the clock's triggering edge and output data
valid.
DIFFERENTIAL PHASE (DP)
OVERVOLTAGE RECOVERY TIME
A signal consisting of a sine wave superimposed on various
DC levels that is applied to the input. Differential phase is the
maximum variation in the sampled sine wave phases at these
DC levels.
The time required for the ADC to recover to full accuracy after
an analog input signal 125% of full scale is reduced to 50%
of the full-scale value.
SIGNAL-TO-NOISE RATIO (SNR)
EFFECTIVE NUMBER OF BITS (ENOB)
The ratio of the fundamental sinusoid power to the total noise
power. Harmonics are excluded.
SINAD = 6.02N + 1.76, where N is equal to the effective
number of bits.
N=
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
SINAD - 1.76
6.02
The ratio of the fundamental sinusoid power to the total noise
and distortion power.
+/- FULL-SCALE ERROR (GAIN ERROR)
TOTAL HARMONIC DISTORTION (THD)
Difference between measured full scale response
[(+Fs) - (-Fs)] and the theoretical response (+4 V -2 LSBs)
where the +FS (full scale) input voltage is defined as the
output transition between 1-10 and 1-11 and the -FS input
voltage is defined as the output transition between 0-00 and
0-01.
The ratio of the total power of the first 64 harmonics to the
power of the measured sinusoidal signal.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The ratio of the fundamental sinusoidal amplitude to the
single largest harmonic or spurious signal.
INPUT BANDWIDTH
Small signal (50 mV) bandwidth (3 dB) of analog input stage.
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TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency
THD vs Input Frequency
80
80
Total Harmonic Distortion (dB)
Signal-to-Noise Ratio (dB)
fs = 10 MSPS
70
70
60
50
fs = 10 MSPS
40
30
60
50
40
30
20
20
10 -1
100
10-1
101
100
SNR, THD, SINAD (dB)
70
60
50
AA
AA
AA
A
SINAD vs Input Frequency
SNR, THD, SINAD vs Sample Rate
80
SNR, THD
70
Signal-to-Noise and Distortion (dB)
80
SINAD
fin = 1 MHz
40
30
20
10 -1
101
Input Frequency (MHz)
Input Frequency (MHz)
60
fs =10 MSPS
50
40
30
20
100
10 -1
101
100
101
Input Frequency (MHz)
Sample Rate (MSPS)
Spectral Response
SNR, THD, SINAD vs Temperature
0
75
fS = 10 MSPS
fIN = 1 MHz
70
SNR, THD, SINAD (dB)
Amplitude (dB)
-30
-60
-90
SNR
65
THD
60
SINAD
fs = 10 MSPS
fin = 1 MHz
55
-120
50
0
1
2
3
4
5
Frequency (MHz)
SPT
-25
0
+25
+50
+75
Temperature (°C)
SPT7910
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3/11/97
the SPT7910. The AGND and the DGND ground planes
should be separated from each other and only connected
together at the device through an inductance or ferrite bead.
Doing this will minimize the ground noise pickup.
TYPICAL INTERFACE CIRCUIT
The SPT7910 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7910 in
normal circuit operation. The following section provides a
description of the pin functions and outlines critical performance criteria to consider for achieving the optimal device
performance.
VOLTAGE REFERENCE
The SPT7910 requires the use of two voltage references: VFT
and VFB. VFT is the force for the top of the voltage reference
ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for the bottom
of the voltage reference ladder. Both voltages are applied
across an internal reference ladder resistance of 800 ohms.
In addition, there are five reference ladder taps (VST,VRT1,
VRT2, VRT3, and VSB). VST is the sense for the top of the
reference ladder (+2.0 V), VRT2 is the midpoint of the ladder
(0.0 V typ) and VSB is the sense for the bottom of the
reference ladder (-2.0 V). VRT1 and VRT3 are quarter point
ladder taps (+1.0 and -1.0 V typical, respectively). The
voltages seen at VST and VSB are the true full scale input
voltages of the device when VFT and VFB are driven to the
recommended voltages (+2.5 V and -2.5 V typical respectively). VST and VSB should be used to monitor the actual full
scale input voltage of the device. VRT1, VRT2 and VRT3
should not be driven to the expected ideal values as is
commonly done with standard flash converters. When not
being used, a decoupling capacitor of .01 uF connected to
AGND from each tap is recommended to minimize high
frequency noise injection.
POWER SUPPLIES AND GROUNDING
The SPT7910 requires the use of two supply voltages, VEE
and VCC. Both supplies should be treated as analog supply
sources. This means the VEE and VCC ground returns of the
device should both be connected to the analog ground plane.
All other -5.2 V requirements of the external digital logic circuit
should be connected to the digital ground plane. Each power
supply pin should be bypassed as closely as possible to the
device with .01 µF and 10 µF capacitors as shown in
figure 2.
The two grounds available on the SPT7910 are AGND and
DGND. DGND is used only for ECL outputs and is to be
referenced to the output pulldown voltage. These grounds
are not tied together internal to the device. The use of ground
planes is recommended to achieve the best performance of
Figure 2 - Typical Interface Circuit
CLK
CLK-IN
2
CLK
CLK-IN
D12 (OVERRANGE)
VIN1
Analog
Input
D11 (MSB)
4
Coarse
A/D
VIN2
D10
Analog
Input
VOUT
5
GND
4
.01 µF
.01 µF
3
2
8
6
+5 V
-5.2 V
AA
2R
.01 µF
2R
4
R3*
30 kΩ
AA
AA
SUCCESSIVE
INTERPOLATION
STAGE # i
IC2
(OP-07)
+
R4
10 kΩ
T/H AMPLIFIER
BANK
2R
VRM
-
+
7
1
10 µF
R
VST
R2*
30 kΩ
+5 V
.01 µF
D8
VFT
+2.5 V
R1
10 kΩ
.01 µF
VIN
(REF-03)
Trim
+
SUCCESSIVE
INTERPOLATION
STAGE # N
2R
VSB
.01 µF
*R2 and R3
matched to 0.1%
-2.5 V
10 µF
D6
D5
D4
D3
D2
D1
D0 (LSB)
13 x 50 Ω
R
VFB
.01 µF
+
10 µH
.01 µF
+
+5 V
D1
DG
L
+ 10 µF
-5.2 V
DG
AG
AG
VCC
VCC
VEE
VEE
+
D7
Digital Outputs
2
6
Decoding Network
IC1
10 µF
D9
ANALOG
PRESCALER
10 µF
.01 µF
10 µF
.01 µF
D2
-5.2 V
+5 V
AGND
( 5 V RTN &
-5.2 V RTN )
DGND
( -2 V RTN )
-2 V
NOTE: D1=D2=1N5817 or equivalent. (Used to prevent damage caused by power sequencing.)
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The analog input range will scale proportionally with respect
to the reference voltage if a different input range is required.
The maximum scaling factor for device operation is ± 20% of
the recommended reference voltages of VFT and VFB. However, because the device is laser trimmed to optimize performance with VSB and VST equal to -2.0 V and +2.0 V respectively, the accuracy of the device will degrade if operated
beyond a ± 2% range.
CLOCK INPUT
The clock inputs (CLK, CLK ) are designed to be driven
differentially with ECL levels. Differential clock driving is
highly recommended to minimize the effects of clock jitter.
The clock may be driven single ended since CLK is internally
biased to -1.3 V. CLK may be left open, but a .01 µF bypass
capacitor to AGND is recommended. As with all high speed
circuits, proper terminations are required to avoid signal
reflections and possible ringing that can cause the device to
trigger at an unwanted time.
The following errors are defined:
+FS error = top of ladder offset voltage = ∆(+FS -VST)
-FS error = bottom of ladder offset voltage = ∆(-FS -VSB)
The clock input duty cycle should be 50% where possible, but
performance will not be degraded if kept within the range of
40-60%. However, in any case the clock pulse width (tpwH)
must be kept at 300 ns maximum to ensure proper operation
of the internal track and hold amplifier. (See the timing
diagram.) The analog input signal is latched on the rising edge
of the CLK.
Where the +FS (full scale) input voltage is defined as the input
approximately 1 LSB above the output transition of 1—10
and 1—11 and the -FS input voltage is defined as the input
approximately 1 LSB below the output transition of 0—00 and
0—01.
An example of a reference driver circuit recommended is
shown in figure 2. IC1 is REF-03, the +2.5 V reference with a
tolerance of 0.6% or ± 0.015 V. The potentiometer R1 is
10 kΩ and supports a minimum adjustable range of up to
150 mV. IC2 is recommended to be an OP-07 or equivalent
device. R2 and R3 must be matched to within 0.1% with good
TC tracking to maintain a 0.3 LSB matching between VFT and
VFB. If 0.1% matching is not met, then potentiometer R4 can
be used to adjust the VFB voltage to the desired level. R1 and
R4 should be adjusted such that VST and VSB are exactly
+2.0 V and -2.0 V respectively.
DIGITAL OUTPUTS
The format of the output data (D0-D11) is straight binary.
(See table II.) These outputs are ECL 10K and 10KH
compatible with the output circuit shown in figure 3. The
outputs are latched on the rising edge of CLK with a propagation delay of 5 ns. There is a one clock cycle latency
between CLK and the valid output data (see timing diagram).
These digital outputs can drive 50 ohms to ECL levels when
pulled down to -2 V. Output loading pulled down to -5.2 V is
not recommended. The total specified power dissipation of
the device does not include the power used by these loads.
The additional power used by these loads can vary between
10 and 300 mW typically (including the overrange load)
depending on the output codes. If lower power levels are
desired, the output loads can be reduced, but careful consideration to the resistive and capacitive loads in relation to the
operating frequency must be considered.
ANALOG INPUT
VIN1 and VIN2 are the analog inputs. Both inputs are tied to
the same point internally. Either one may be used as an
analog input sense and the other for an input force. The inputs
can also be tied together and driven from the same source.
The full scale input range will be 80% of the reference voltage
or ±2 volts with VFB=-2.5 V and VFT=+2.5 V.
Table II - Output Data Information
The drive requirements for the analog inputs are minimal
when compared to conventional Flash converters due the
SPT7910’s extremely low input capacitance of only 5 pF and
very high input impedance of 300 kΩ. For example, for an
input signal of ± 2 V p-p with an input frequency of 10 MHz,
the peak output current required for the driving circuit is only
628 µA.
ANALOG INPUT
OVERRANGE
D12
OUTPUT CODE
D11-DO
>+2.0 V + 1/2 LSB
1
1111 1111
1111
+2.0 V -1 LSB
O
1111 1111
111Ø
0.0 V
O
ØØØØ ØØØØ ØØØØ
-2.0 V +1 LSB
O
OOOO OOOO OOOØ
<-2.0 V
O
OOOO OOOO OOOO
(Ø indicates the flickering bit between logic 0 and 1).
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Figure 3 - Output Circuit
EVALUATION BOARD
AGND
•
DGND
The EB7910 Evaluation Board is available to aid designers in
demonstrating the full performance of the SPT7910. This
board includes a reference circuit, clock driver circuit, output
data latches and an on-board reconstruction of the digital
data. An application note (AN7910) describing the operation
of this board as well as information on the testing of the
SPT7910 is also available. Contact the factory for price and
availability.
•
•
Data Out
•
OVERRANGE OUTPUT
The OVERRANGE OUTPUT (D12) is an indication that the
analog input signal has exceeded the full scale input voltage
by 1 LSB. When this condition occurs, the output will switch
to logic 1. All other data outputs are unaffected by this
operation. This feature makes it possible to include the
SPT7910 into higher resolution systems.
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PACKAGE OUTLINE
32-Lead Sidebrazed
32
H
I
1
J
G
A
SYMBOL
E
F
C
B
SPT
D
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
A
0.081
0.099
2.06
2.51
B
C
D
E
F
G
0.016
0.095
0.020
0.105
.050 typ
0.41
2.41
0.040
0.175
1.580
0.225
1.620
1.02
4.45
40.13
0.51
2.67
1.27
5.72
41.15
15.37
H
I
J
0.585
0.009
0.600
0.605
0.012
0.620
14.86
0.23
15.24
0.30
15.75
15.75
SPT7910
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3/11/97
PIN FUNCTIONS
PIN ASSIGNMENTS
NAME
FUNCTION
DGND
Digital Ground
AGND
Analog Ground
D0-D11
ECL Outputs (D0=LSB)
V
D12
ECL Output Overrange
28
V
CLK
Clock
6
27
V
CLK
Inverted Clock
7
26
V
VEE
-5.2 V Supply
D5
VCC
+5.0 V supply
D6
8
25
V
VRT1,VRT2,VRT3
Voltage Reference Taps
D7
9
24
V
VIN1, VIN2
Inputs (tied together at the die)
D8
10
23
V
VFT
Force for Top of Reference Ladder
D9
11
22
V
VST
Sense for Top of Reference Ladder
D10
12
21
V
VFB
Force for Bottom of Reference Ladder
VSB
Sense for Bottom of Reference Ladder
D11
13
20
V
D12
14
19
AGND
DGND 15
18
V
CLK
17
CLK
DGND
1
32
V
D0
2
31
AGND
D1
3
30
V
D2
4
29
D3
5
D4
DIP
16
EE
CC
FB
SB
RT1
RT2
IN1
IN2
RT3
ST
FT
CC
EE
ORDERING INFORMATION
PART NUMBER
SPT7910SCJ
SPT7910SCU
TEMPERATURE RANGE
PACKAGE
0 to +70 °C
+25 °C
32L Sidebrazed DIP
Die*
*Please see the die specification for guaranteed electrical performance.
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly
granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.
WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.
Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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