PI6C9910 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero-Delay Clock Buffer Features Description The PI6C9910 is a low-skew clock driver designed to simplify clock distribution in systems requiring near synchronous clocks. A typical application is in SDRAM modules. Each of the eight outputs (Q0-Q7) can drive individual 50Ω transmission lines with minimal distortion or skew, and full 5V swing. Zero input to output delay Eight clock copies from one clock input 15 - 80 MHz output operation Fifty percent duty cycle Low skew (< 250ps typ.) VCC = 5.0V +/- 10%, TA = 0° to 70° Low jitter (< 250 ps cycle to cycle), < 60ps RMS Low noise unbalanced drive outputs (PI6C9910-5) Low noise balanced drive outputs (PI6C9910A) Packages available: 24-pin 300 mil wide SOIC (S) 24-pin 209 mil wide SSOP (H) Compatible with Cypress CY7B9910-5 An on-chip phase-locked loop (PLL) synchronizes the feedback (FB) to the reference (REF) input, achieving zero-delay buffered outputs. Inserting an external counter between any of the Qx outputs and the FB pin allows for generation of eight synchronous clock copies whose frequency is a multiple of a lower frequency REF input. The voltage-controlled oscillator (VCO) frequency is determined by the filtered ouput coming from the Phase/Frequency Detector. The frequency select (FS) input sets the VCO operating range. Test Mode In normal operation the TEST pin is tied to ground. For testing purposes it can have a removable jumper to ground or a 100Ω pull-down resistor. When the TEST pin is driven HIGH, the VCO output is disconnected, and all eight outputs (Q0-Q7) are directly driven from the REF input. Block Diagram PI6C9910-5 has unbalanced output drivers (TTL), and is fully compatible with the Cypress CY7B9910-5. The PI6C9910A features balanced-drive outputs (CMOS) for improved rise/fall time symmetry. The FS and TEST inputs have internal pull-up resistors. Pinout TEST FB Freq. REF REF VCCQ FS NC VCCQ VCCN Q0 Q1 GND Q2 Q3 VCCN Phase Det Filter Voltage Controlled Oscillator FS Q0 Q1 Q2 Q3 1 2 3 4 5 6 7 8 9 10 11 12 24-Pin S, H 24 23 22 21 20 19 18 17 16 15 14 13 GND TEST NC GND VCCN Q7 Q6 GND Q5 Q4 VCCN FB Q4 Q5 Q6 Q7 108 PS8341B 03/05/99 PI6C9910 Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature................................................. 65°C to +150°C Ambient Temperature with Power Applied .............. 55°C to +125°C Supply Voltage to Ground Potential ............................ 0.5V to +7.0V DC Input Voltage ......................................................... 0.5V to +7.0V Output Current into Outputs (LOW) ........................................... 64mA Static Discharge Voltage (per MIL-STD-883, Method 3015) >2001V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Latch-Up Current .................................................................... >200mA Operating Range Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% Pin Description Pin Name I/O Functional Description REF I Reference Frequency Input. This input supplies the frequency and timing against which all functional variation is measured. FB I PLL feedback input (typically connected to one of eight outputs). FS I Two-level frequency range select. See Table 1. Internal Pullup. TEST I Two-level select. See Test Mode Section. Internal Pull-up Q[0-7] O Clock Outputs. VCCN PWR Power supply for output drivers. VCCQ PWR Power supply for internal circuitry. GND PWR Ground. 109 PS8341B 03/05/99 PI6C9910 Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Electrical Characteristics Over Operating Range(1) Symbol Parame te r Te s t Conditions M in. M ax. VOH Output HIGH Voltage (PI6C9910- 5) VCC = Min., IOH = - 16mA 2.4 VOL Output LOW Voltage (PI6C9910- 5) VCC = Min., IOL = 46mA 0.45 VOH Output HIGH Voltage (PI6C9910A) VCC = Min., IOH = - 24mA 2.4 VOL Output LOW Voltage (PI6C9910A) VCC = Min., IOL = 24mA 0.40 IIH Input HlGH Leakage Current (REF, Test, FS, and FB inputs only) VCC = Max., VIN = Max. 10 −10 - 500 Input LOW Leakage Current (REF and FB inputs only) IIL IOS Output Short Circuit Current(2) VCC = Max., VOUT = GND (25°C only) −250 ICCQ Operating Current Used by Internal Circuitry VCCN = VCCQ = Max., All Inputs Selects Open 85 Output Buffer Current per Output Pair VCCN = VCCQ = Max., IOUT = 0mA Inputs Selects Open, fMAX 14 Power Dissipation per Output Pair VCCN = VCCQ = Max., IOUT = 0mA Inputs Selects Open, fMAX 78 PD V µA VCC = Max., VIN = 0.4V Input LOW Leakage Current (Test and FS inputs only) ICCN Units mA mW Notes: 1. These inputs are normally wired to VCC, GND. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time betore all datasheet limits are achieved. 2. Tested one output at a time, output shorted for less than one second, less than l0% duty cycle. Room temperature only. Capacitance (TA = 25°C, f = 1 MHz) Parameter CIN Description Input Capacitance REF and FB Test Conditions Max. Units TA = 25C, f = 1 MHz, VCC = 5.0V 10 pF 110 PS8341B 03/05/99 PI6C9910 Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Unbalanced Output Drive AC Test Load and Waveform 5V 3.0V R1 CL R1 = 130Ω R2 = 91Ω CL = 30pF (Includes fixture and probe capacitance) R2 2.0V Vth = 1.5V 0.8V 2.0V Vth = 1.5V 0.8V 0.0V ≤1 ns ≤1 ns TTL Input Test Waveform TTL AC Test Load Table 1. Frequency Range Select fNOM (M Hz) FS M inimum M aximum LOW 15 35 HIGH 25 80 AC Timing Diagram t REF t RPWH REF t PD t RPWL t ODCV t ODCV FB Q t SKEW OTHER Q t JR t SKEW 111 PS8341B 03/05/99 PI6C9910 Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics Over Operating Range(1) Symbol De s cription M in. Typ. M ax. FS = LOW 15 35 FS = HIGH 25 80 fNOM Operation Clock Frequency in MHz tRPWH REF Pulsewidth HIGH 5.0 tRPWL REF Pulsewidth LOW 5.0 tSKEW Zero Output Skew (All Outputs)(2,3) 0.25 0.5 tDEV Device- to- Device Skew(4,5) 1.0 tPD Propagation Delay, REF Rise to FB Rise - 0.5 0.0 +0.5 tODCV Output Duty Cycle Variation(6) - 1.0 0.0 +1.0 tORISE Output Rise Time(7,8) 0.15 1.0 1.5 tOFALL Output Fall Time(7,8) 0.15 1.0 1.5 tLOCK PLL Lock Time(9) 0.5 Cycle- to- Cycle 250 RMS(5) 60 (5) tJR Output Jitter Units MHz ns ms ps Notes: 1. Test measurement levels for the PI6C9910-5 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 2. Skew is defined as the time between the earliest and the latest output transition among all outputs with AC Test Load. 3. tSKEW is defined as the skew between outputs. 4. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, etc.). 5. Tested initially and after any design or process changes that may affect these parameters. 6. tODCV is the deviation of the output from a 50% duty cycle. 7. Specified with outputs loaded with AC Test Load (30pF). 8. tORISE and tOFALL measured between 0.8V and 2.0V. 9. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 112 PS8341B 03/05/99 PI6C9910 Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Package Mechanical Information 24 .2914 .2992 7.40 7.60 0.254 x 45˚ 0.737 .010 .029 1 .0091 .0125 0-8˚ .5985 15.20 .6141 15.60 0.23 0.32 0.41 .016 1.27 .050 .021 0.533 .031 0.787 .0926 2.35 .1043 2.65 .394 .419 10.00 10.65 SEATING PLANE .050 BSC .013 .020 0.33 0.51 1.27 .0040 .0118 0.10 0.30 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 300-Mil 24-Pin SOIC 24 .197 5.00 .220 5.60 1 .311 .334 7.90 8.50 .004 .009 0.55 .022 0.95 .037 .078 2.0 Max .291 .322 7.40 8.20 SEATING PLANE .0256 BSC 0.65 0.09 0.25 .002 Min 0.050 .0098 Max. 0.25 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 209-Mil 24-Pin SSOP Ordering Information Part Numbe r Package PI6C9910AS 300- Mil 24- pin SOIC Package S24 PI6C9910AH 209- Mil 24- pin SSOP Package H24 PI6C9910- 5S 300- Mil 24- pin SOIC Package S24 PI6C9910- 5H 209- Mil 24- pin SSOP Package H24 113 PS8341B 03/05/99