Design for Manufacturing (DFM) 1 Creating Robust Designs using Advanced Design System January 29, 2009 Advanced DFM Tools for Robust Designs Designers need not worry whether their circuits will require redesign. Managers need not be concerned with the high costs of multi-wafer runs. ADS Advanced DFM Tools help designers achieve “First Pass Success.” 2 January 29, 2009 The Value of ADS DFM Technology Designing circuits that will work no matter what First to market High manufacturing yield (Lower cost per chip) Insensitive to changes in temp and supply voltage First pass success ADS DFM Tools Tremendous amount of time and $$ savings Reliable, high quality designs Unique DFM design tools that allow designers to transform their standard designs into robust ones with first-pass success and high yield. 3 January 29, 2009 MMIC Up-Converter Design Example Mixer 2 Mixer 1 Wafer measured Results Standard Design A wide, 10 dB Variation – Very sensitive 4 X-band Amp2 Ku-band K-band LO Ku-band K-band LO X-band Amp1 Wafer measured Results DOE Based Design Consistent Results 1.3 dB variation January 29, 2009 The DFM Process for MMIC Obtain process parameters Statistical device model or actual measured parameters DFM Tools Sensitivity histograms / find sensitive network Sensitivity analysis Design Of Experiments (DOE) - find sensitive network Start nominal design 5 Optimize and design center Fix Design Monte Carlo Yield analysis Design centering / yield optimization January 29, 2009 Example: 2.4 GHz MIC LNA on Alumina Substrate MIC Design Example • Alumina Substrate • Er=9.9 H=25 mils • Device: NEC 67383 FET • Freq: 2.4 GHz • NF Spec: .7 dB 6 January 29, 2009 Example: 2.4 GHz MIC LNA on Alumina Substrate NEC 67383 FET Optimum Noise Match 2-3 GHz Alumina Substrate Er = 9.9 H=25 mils Design Spec: .7 dB NF @ 2.4 GHz 7 January 29, 2009 Example: 2.4 GHz LNA - MIC Design Three of many different ways to match for optimum noise Γm Goal is to have the matching network impedance coincide with the optimum noise figure impedance, Γm 8 January 29, 2009 Example: Ruby Mask - 2.4 GHz LNA Bypass Caps Drain bias Alumina Substrate FET Tuning Confetti Carrier 9 January 29, 2009 Initial Test Results (Major Problem) NF Spec: .7 dB Measured: 8 dB Simulation: .5 dB 10 January 29, 2009 Finding a solution in the lab Take the Input Matching Network out A wire loop 1- Diamond scribe out the input matching network 2- Solder a loop of inductive wire from FET to connector 11 January 29, 2009 Finding a solution in the lab Very surprisingly, this solution achieved a .5 db NF @ 2.4 GHz A wire loop 1- Diamond scribe out the input matching network 2- Solder a loop of inductive wire from FET to connector 12 January 29, 2009 Example: Ruby Mask - 2.4 GHz LNA Wire loop from input port to FET’s Gate Back to the drawing board for further investigation and understanding 13 January 29, 2009 Understanding What Went Wrong 2.4 GHz 14 January 29, 2009 Single Line Matching – Low Q Use of high impedance, single line was the best technique for achieving robust & optimum Results, but too narrow to realize. Suspended line concept was utilized to produce a realizable, wider, high impedance line with a low Q broadband network 15 January 29, 2009 Matching with Single Line – Low Q Option 2 is even more robust, but non-realizable 16 January 29, 2009 NF Simulation of the Various Matching Networks hing c t a M Line e l g n i S 17 January 29, 2009 Real MMIC Designs – Fabricated on the Same Wafer A reticle contains a few circuits, stepped and repeated across the whole wafer Amp Amp1 A mp2 1) Used a standard design technique 18 2) Used a DFM / DOE Based design technique All designs went through the same wafer fab process January 29, 2009 Our Goal is to Create Something Like Amp2 Amp1 Standard Design Technique 19 Amp2 DFM based Design Technique January 29, 2009 Real MMIC Designs – Fabricated on the Same Wafer A reticle contains a few circuits, stepped and repeated across the whole wafer Amp Mixer LO Amp Amp1 A mp2 U/C 1 U/C 2 macro macro 1) Used a standard design technique 20 2) Used a DFM Based design technique All designs went through the same Wafer Fab Process January 29, 2009 Our Goal is to Create Something Like U/C 2 Mixer 1 Amp1 Amp2 U/C 2 Standard Design Technique DFM Based Design Technique LO U/C 1 LO 21 Mixer 2 January 29, 2009 The DFM Process for MMIC Obtain process parameters Statistical device model or actual measured parameters DFM Tools Sensitivity histograms / find sensitive network Sensitivity analysis Design Of Experiments (DOE) - find sensitive network Start nominal design 22 Optimize and design center Fix Design Monte Carlo Yield analysis Design centering / yield optimization January 29, 2009 Example Number of Chips This curve could represent a foundry’s output of 100,000 Driver Amps with Gain=20 dB (+/- 3 σ = 6 dB) 17 23 20 23 January 29, 2009 Example – Six Sigma Design Number of Chips 100,000 Driver Amps with Gain=20 dB (+/- 3 σ = 6 dB) Spec = 20 dB +/- 6 dB Yield is about 99.99966 % Specification 14 LSL 17 20 Width 23 26 USL Lower Spec Limit 24 January 29, 2009 Typical Process Yield Curve Number of Chips 100,000 Power Amps with Gain=20 dB (+/- 3 σ = 6 dB) Spec = 20 dB +/- 1 dB Yields about 65% Tighter Specs; Many failed parts 17 25 Spec 20 23 January 29, 2009 Make the Process Yield Curve Narrower 100,000 Power Amps with Gain=20 dB (+/- 3 σ = 6 dB) Change Design to Yield Gain=20 dB (+/- 3 σ = 2 dB Spec = 20 dB +/- 1 dB Yields about 65% Spec 17 26 Spec 20 23 January 29, 2009 Our Goal is to Create Something like Amp2 Amp1 27 Amp2 January 29, 2009 Amp1 & Amp2 “Yield Distributions” Amp2 Amp1 28 January 29, 2009 The DFM Process Curve 1 Original design Curves 2,3 Fixing the design to achieve robustness Curves 4 Further improvement towards achieving robustness Curve 5 Final shift the response by design centering to meet specifications 29 January 29, 2009 The DFM Process for MMIC Obtain process parameters Statistical device model or actual measured parameters DFM Tools Sensitivity histograms / find sensitive network Sensitivity analysis Design Of Experiments (DOE) - find sensitive network Start nominal design 30 Optimize and design center Fix Design Monte Carlo Yield analysis Design centering/ yield optimization January 29, 2009 Sensitivity Analysis Absolute Sensitivity Gain drops .162 dB for every 1 ohm increase in R1 Normalized Sensitivity Gain drops .25% for every 1% increase in R1 31 January 29, 2009 Design For Manufacturing - Yield Analysis Yield Analysis indicates that there is a problem with yield. Design Of Experiments (DOE) and Yield Sensitivity Histograms (YSH) tools are like X-rays. They allow us to pinpoint the exact location in the design that is causing the problem with the low yield. 32 January 29, 2009 Yield Sensitivity Histograms 33 January 29, 2009 Yield Sensitivity Histograms Yield as a function of resistor OMN_R1 Notice the yield go up if we lower OMN_R1 34 January 29, 2009 DOE Analysis S22 is affected mostly by OMN_C1 and line widths: C1 adds 2 dB to S22 Line widths add 1.5 dB to S22 There is an interaction effects between OMN_R1 and line widths 35 January 29, 2009 This is the End of Section One In the next three short sections, we will show detailed information on each one of the DFM tools in ADS • Sensitivity Analysis • Yield and Yield Sensitivity Histograms • Design of Experiments (DOE) 36 January 29, 2009