ETC INA-31063-BLK

DC – 2.5 GHz 3 V, High Isolation
Silicon RFIC Amplifier
Technical Data
INA-31063
Features
• High Reverse Isolation
-40 dB at 1.9 GHz
Surface Mount SOT-363
(SC-70) Package
• Single +3V Supply
• 15 dB |S21|2 at 1.9 GHz
• 200 Ω Output Impedance
• Ultra-Miniature Package
• Unconditionally Stable
Pin Connections and
Package Marking
Applications
GND 2 1
GND 1 2
31
• LO Buffer and Amplifier for
Cellular, Cordless, Special
Mobile Radio, PCS, ISM,
Wireless LAN, DBS, TVRO,
and TV Tuner
INPUT 3
6 OUTPUT
& Vd
5 GND 1
4 Vd
Note: Package marking provides
orientation and identification.
Simplified Schematic
Vd
Output & Vd
Input
Gnd1
Gnd2
Description
Hewlett-Packard’s INA-31063 is a
Silicon RFIC amplifier that has
excellent gain and isolation for
applications to 2.5 GHz. Packaged
in an ultra-miniature SOT-363
package, it requires half the board
space of a SOT-143 package.
The INA-31063 uses a unique
circuit topology that provides
broadband gain and 50 Ω input
and 200 Ω output impedance.
With more than 35 dB of isolation
to 2.5 GHz makes it an excellent
candidate for LO buffer
applications.
The INA-31063 is fabricated using
HP’s 30 GHz fMAX ISOSAT TM
Silicon bipolar process which
uses nitride self-alignment,
submicrometer lithography,
trench isolation, ion implantation,
and polyimide intermetal dielectric and scratch protection to
achieve superior performance,
uniformity, and reliability.
2
Absolute Maximum Ratings
Symbol
Parameter
Units
Absolute
Maximum[1]
V
6.0
dBm
+7.0
Vd
Device Voltage,
output to ground
Pin
CW RF Input Power
Tj
Junction Temperature
°C
150
T STG
Storage Temperature
°C
-65 to 150
Thermal Resistance [2]:
θjc = 170°C/W
Notes:
1. Operation of this device above any one
of these limits may cause permanent
damage.
2. TC = 25°C (TC is defined to be the
temperature at the package pins where
contact is made to the circuit board)
INA-31063 Electrical Specifications, TC = 25°C, ZO = 50 Ω,Vd = 3 V
Symbol
|S 21 |2
NF50
P1dB
IP3
VSWRin
VSWRout
Ιd
Parameters and Test Conditions
Gain in 50 Ω system
f = 0.9 GHz
f = 1.9 GHz
f = 2.4 GHz
Noise Figure
f = 1.9 GHz
Output Power at 1 dB Gain Compression
f = 0.9 GHz
f = 1.9 GHz
f = 2.4 GHz
Output Third Order Intercept Point
f = 0.9 GHz
f = 1.9 GHz
f = 2.4 GHz
Input VSWR
f = 0.1 – 2.4 GHz
Output VSWR
f = 0.1 – 2.4 GHz
Device Current
Units Min.
dB
13.0[3]
dB
dBm
dBm
mA
Typ. Max. Std.
Dev.[4]
14.0
15.1
0.44
15.0
6.1
0.25
-1.8
-2.1
-3.5
9.1
8.5
6.8
1.35:1
3.5:1
11.0 13.5 [3] 0.47
Notes:
3. Guaranteed specifications are 100% tested in production.
4. Standard deviation number is based on measurement of a large number of parts from three non-consecutive wafer lots
during the initial characterization of this product, and is intended to be used as an estimate for distribution of the
typical specification.
3
INA-31063 Typical Performance, TC = 25°C, ZO = 50 Ω, V d = 3 V
20
7.5
4
2.7 V
3.0 V
3.3 V
7
NOISE FIGURE (dB)
10
5
6.5
6
5.5
2.7 V
3.0 V
3.3 V
0
0
0.5
P1 dB (dBm)
GAIN (dB)
15
5
1.5
2.0
2.5
-2
-4
-8
0
0.5
FREQUENCY (GHz)
1.0
1.5
2.0
2.5
0
0.5
P1 dB (dBm)
NOISE FIGURE (dB)
6
0
-2
-4
5
-40°C
+25°C
+85°C
0
2.5
-40°C
+25°C
+85°C
2
7
5
2.0
4
-40°C
+25°C
+85°C
10
1.5
Figure 3. Output Power for 1 dB Gain
Compression vs. Frequency and
Voltage.
8
15
1.0
FREQUENCY (GHz)
Figure 2. Noise Figure vs. Frequency
and Voltage.
20
0
0.5
FREQUENCY (GHz)
Figure 1. Gain vs. Frequency and
Voltage measured in a 50 Ω system.
GAIN (dB)
0
-6
4.5
1.0
2.7 V
3.0 V
3.3 V
2
-6
4
1.0
1.5
2.0
-8
0
2.5
0.5
FREQUENCY (GHz)
1.0
1.5
2.0
2.5
0
0.5
Figure 5. Noise Figure vs. Frequency
and Temperature.
4
1.5
2.0
2.5
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 4. Gain vs. Frequency and
Temperature measured in a 50 Ω
system.
1.0
Figure 6. Output Power for 1 dB Gain
Compression vs. Frequency and
Temperature.
25
14
-40°C
+25°C
+85°C
20
3
12
IP3 (dBm)
10
Id (mA)
VSWR
15
2
10
8
6
1
5
VSWR in
VSWR out
0
0
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
Figure 7. Input and Output VSWR vs.
Frequency.
-40°C
+25°C
+85°C
4
2
0
1
2
3
4
5
Vd (V)
Figure 8. Supply Current vs. Voltage
and Temperature.
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
Figure 9. Third Order Intercept
Point, IP3 vs. Frequency and
Temperature.
2.5
4
INA-31063 Typical Scattering Parameters[5], TC = 25°C, Z O = 50 Ω,Vd = 3.0 V
Freq.
GHz
Mag
S11
Ang
dB
S21
Mag
Ang
dB
S12
Mag
Ang
Mag
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
0.14
0.15
0.14
0.15
0.15
0.14
0.14
0.15
0.14
0.14
0.14
0.13
0.13
0.13
0.13
0.12
0.12
0.12
0.12
0.11
0.10
0.08
0.07
0.05
0.04
0.04
0.05
0.06
0.08
0.10
0.13
0.15
0.17
0.19
0.21
0.22
0.24
0.25
0.25
0.26
0.27
0.27
0.28
0.29
0.29
0.30
0.31
0.32
0.33
0.33
171
167
164
163
152
152
151
147
143
138
137
136
132
129
125
128
130
130
130
128
129
130
134
144
166
-176
-159
-151
-149
-150
-152
-153
-155
-158
-160
-161
-163
-165
-167
-169
-172
-175
-178
180
177
174
171
169
166
164
13.6
13.7
13.7
13.7
13.8
13.8
13.9
14.0
14.0
14.1
14.2
14.3
14.4
14.5
14.6
14.6
14.8
14.9
15.1
15.2
15.3
15.3
15.1
15.0
14.8
14.5
14.1
13.7
13.3
12.8
12.3
11.8
11.3
10.7
10.1
9.6
9.1
8.5
8.0
7.5
7.0
6.5
6.1
5.6
5.1
4.7
4.3
3.8
3.4
3.0
4.81
4.84
4.83
4.86
4.88
4.88
4.93
4.99
5.04
5.06
5.12
5.20
5.26
5.33
5.34
5.36
5.49
5.57
5.69
5.77
5.83
5.79
5.71
5.63
5.50
5.29
5.06
4.84
4.62
4.36
4.11
3.89
3.65
3.42
3.20
3.02
2.84
2.66
2.51
2.37
2.24
2.12
2.01
1.90
1.81
1.72
1.63
1.55
1.48
1.41
-5
-11
-15
-20
-26
-30
-35
-40
-45
-51
-56
-61
-67
-73
-80
-85
-91
-97
-104
-111
-119
-127
-135
-143
-152
-160
-167
-174
178
172
165
159
153
147
142
137
132
128
124
120
116
112
109
105
102
98
95
92
89
87
-32.5
-37.1
-36.0
-37.6
-39.8
-37.1
-38.6
-41.3
-45.5
-45.2
-44.1
-45.3
-47.3
-46.8
-41.9
-41.5
-44.3
-45.0
-46.4
-45.8
-44.7
-43.4
-42.4
-41.7
-41.8
-42.2
-43.2
-43.1
-43.3
-44.2
-44.0
-43.0
-42.0
-42.2
-41.3
-38.9
-38.0
-37.3
-35.5
-34.2
-33.2
-32.4
-31.3
-30.5
-29.7
-28.9
-28.3
-27.7
-27.0
-26.2
0.024
0.014
0.016
0.013
0.010
0.014
0.012
0.009
0.005
0.005
0.006
0.005
0.004
0.005
0.008
0.008
0.006
0.006
0.005
0.005
0.006
0.007
0.008
0.008
0.008
0.008
0.007
0.007
0.007
0.006
0.006
0.007
0.008
0.008
0.009
0.011
0.013
0.014
0.017
0.019
0.022
0.024
0.027
0.030
0.033
0.036
0.039
0.041
0.045
0.049
10
11
-3
-39
-6
-18
-35
-46
-35
-4
-6
-16
20
40
58
30
27
31
53
61
74
78
79
76
74
76
77
85
86
96
105
115
118
125
139
143
144
151
155
153
153
154
154
154
153
152
151
151
151
150
0.49
0.52
0.51
0.54
0.53
0.51
0.53
0.55
0.56
0.55
0.54
0.55
0.55
0.55
0.53
0.49
0.50
0.50
0.51
0.52
0.53
0.52
0.50
0.49
0.49
0.47
0.44
0.40
0.39
0.36
0.34
0.32
0.30
0.29
0.27
0.25
0.24
0.23
0.21
0.21
0.20
0.20
0.19
0.19
0.19
0.19
0.19
0.19
0.19
0.19
Note:
5. Reference plane per Figure 19 in Applications Information section.
S22
Ang
-3
-4
-4
-3
-5
-5
-5
-8
-11
-14
-17
-19
-24
-28
-35
-36
-37
-40
-44
-48
-54
-62
-68
-73
-80
-87
-93
-97
-100
-105
-108
-109
-111
-113
-115
-114
-114
-115
-113
-111
-109
-108
-105
-103
-101
-99
-98
-97
-95
-93
K
Factor
3.45
5.37
4.79
5.60
7.31
5.38
6.02
7.66
13.54
13.71
11.32
13.20
16.34
12.92
8.32
8.84
11.23
11.18
12.80
12.59
10.20
8.94
8.22
8.42
8.64
9.24
11.43
12.34
13.10
16.46
17.71
16.22
15.17
16.23
15.49
13.50
12.09
12.00
10.55
9.98
9.10
8.83
8.26
7.82
7.47
7.17
6.94
6.89
6.54
6.30
5
INA-31063 Applications
Information
Introduction
The INA-31063 is a +3 volt silicon
RFIC amplifier that is designed
with a two stage internal network
to provide a broadband gain and
50 Ω input and 200 Ω output
impedance. With a P-l dB compressed output power of -3 dBm
and high isolation of 40 dB, the
INA-31063 is well suited for LO
buffer amplifier applications in
mobile communication systems.
The 200 Ω output impedance of
the amplifier allows easy connections to additional RFICs and
some filters.
In addition to use in buffer
applications in the cellular
market, the INA-31063 will find
many applications in battery
operated wireless communication
systems.
Operating Details
The INA-31063 is a voltage biased
device that operates from a
+3 volt power supply with a
typical current drain of 11 mA.
All bias regulation circuitry is
integrated into the RFIC.
Figure 10 shows a typical implementation of the INA-31063. The
supply voltage for the INA-31063
must be applied to two terminals,
the Vd pin and the RF Output pin.
Cout
Gnd2
31
Gnd1
Gnd1
RF
Output
RFC
The Vd connection to the amplifier is RF bypassed by placing a
capacitor to ground near the Vd
pin of the amplifier package. The
power supply connection to the
RF Output pin is achieved by
means of a RF choke (inductor).
The value of the RF choke must
be large relative to 50 Ω in order
to prevent loading of the RF
Output. The supply voltage end of
the RF choke is bypassed to
ground with a capacitor. If the
physical layout permits, this can
be the same bypass capacitor that
is used at the Vd terminal of the
amplifier. Blocking capacitors are
normally placed in series with the
RF Input and the RF Output to
isolate the DC voltages on these
pins from circuits adjacent to the
amplifier. The values for the
blocking and bypass capacitors
are selected to provide a reactance at the lowest frequency of
operation that is small relative to
50 Ω. Since the gain of the
INA-31063 extends down to DC,
the frequency response of the
amplifier is limited only by the
values of the capacitors and
choke.
An example for the RF layout for
the INA-31063 is shown in
Figure 11.
Gnd 1
Gnd 2
50 Ω
RF Output
and Vd
Gnd 1
Vd
RF
Input
Cblock
Figure 10. Basic Amplifier
Application.
Cbypass
Gnd 1
Gnd 2
VIA
Figure 12. INA-31063 Potential
Ground Loop.
Gnd 1
VIA
Gnd 2
VIA
Figure 13. INA-31063 Suggested
Layout.
RF Layout
50 Ω
the circuit board). The circuit
board material is 0.031-inch thick
FR4. Plated through holes (vias)
are used to bring the ground to
the top side of the circuit where
needed. The performance of
INA-31063 is sensitive to ground
path inductance. The two-stage
design creates the possibility of a
feedback loop being formed
through the ground returns of the
stages, Gnd 1 and Gnd 2.
Figure 11. RF Layout
This example uses a
microstripline design (solid
groundplane on the backside of
At least one ground via should be
placed adjacent to each ground
pin to assure good RF grounding.
Multiple vias are used to reduce
the inductance of the path to
ground and should be placed as
close to the package terminals as
practical.
The effects of the potential
ground loop shown in Figure 12
may be observed as a “peaking” in
the gain versus frequency
response, an increase in input
VSWR, or even as return gain at
the input of the INA-31063.
6
blocking capacitors were 100 pF
and the bypass capacitor was
1000 pF.
RFM
Cshunt
Frequency RFC
400 M Hz 120 nH
Cout
31
RFC
Vd
Cblock
Cbypass
Figure 15. Impedance Matched
Output Amplifier Circuit.
These values provide excellent
amplifier performance at 900 MHz.
Larger values for the choke and
capacitors can be used to extend
the lower end of the bandwidth. A
convenient method for making RF
connection to the demonstration
board is to use a PCB mounting
type of SMA connector (Johnson
142-0701881, or equivalent). These
connectors can be slipped over
the edge of the PCB and the
center conductor soldered to the
input and output lines. The ground
pins of the connectors can be
soldered to the ground plane on
the backside of board.
900 MHz 50 Ω Matched
Example
The use of a simple impedance
matching network will typically
increase both gain and output
power by 1.5 dB and 1.5 dBm,
respectively. The values that were
chosen for the two tuning elements were a 12 nF series inductor and a 1.0 pF shunt capacitor.
The RF choke was a 56 nH
(Coilcraft 1008CS-221, TOKO
LL2012-F or equivalent). The two
CSHUNT
56 nH 12 nH
1.0 pF
1900 MHz
33 nH
4.7 nH
None
2400 MHz
27 nH
1.8 nH
None
900 MHz
RF
Output
RF
Input
RFM
27 nH
The test results for the INA-31063
were measured on the 50 Ω input
and output impedance matched
amplifier described above.
4
900 MHz
1900 MHz
0
Ltune C2
31
RFC
C3
C4
Vd
-8
-16
-30
-25
-20
-15
-10
-5
Figure 17. Measured Input Power vs.
Output Power on Assembled 50 Ω
Amplifier at 900 MHz and 1900 MHz.
An important specification when
selecting a LO buffer amplifier is
reverse isolation under P1dB input
conditions. Figure 18 shows the
measured reverse isolation with
-10 dBm applied to the input of
the device.
-20
-30
-40
-50
-60
0
0.5
1.0
1.5
2.0
FREQUENCY (GHz)
Figure 14. Assembled Amplifier.
0
Pin (dBm)
REVERSE ISOLATION (dB)
Ctune
-4
-12
INA-3XX63 DEMO BOARD
C1
2.7 pF
Figure 16. Suggested Matching
Elements for Common Frequency
Bands.
Pout (dBm)
Figure 14 shows an assembled
50 Ω amplifier. The +3 volt supply
is fed directly into the Vd pin of
the INA-31063 and into the RF
Output pin through the RF choke
(RFC). Capacitor C3 provides RF
bypassing for both the Vd pin and
the power supply end of the RFC.
Capacitor C4 is optional and may
be used to add additional
bypassing for the Vd line. A wellbypassed Vd line is especially
necessary in cascades of amplifier stages to prevent oscillation
that may occur as a result of RF
feedback through the power
supply lines.
Figure 18. Measured Isolation.
2.5
7
PCB Materials
Typical choices for PCB material
for low cost wireless applications
are FR-4 or G-10 with a thickness
of 0.025 (0.636 mm) or 0.031 inches
(0.787 mm). A thickness of 0.062
inches (1.574 mm) is the maximum
that is recommended for use with
this particular device. The use of a
thicker board material increases
the inductance of the plated
through vias used for RF grounding
and may deteriorate circuit
performance. Adequate grounding
is needed not only to obtain
maximum amplifier performance
but also to reduce any possibility
of instability.
Phase Reference Planes
The positions of the reference
planes used to measure
S-Parameters for this device are
shown in Figure 19. As seen in the
illustration, the reference planes
are located at the point where the
package leads contact the test
circuit.
REFERENCE
PLANES
TEST CIRCUIT
Figure 19. Phase Reference Planes.
SOT-363 PCB Layout
The INA-31063 is packaged in the
miniature SOT-363 (SC-70)
surface mount package. A PCB
pad layout for the SOT-363
package is shown in Figure 20
(dimensions are in inches). This
layout provides ample allowance
for package placement by automated assembly equipment
without adding pad parasitics that
could impair the high frequency
performance of the INA-31063
The layout that is shown with a
nominal SOT-363 package footprint superimposed on the PCB
pads for reference.
0.026
0.075
0.035
0.016
Figure 20. PCB Pad Layout for
INA-31063 (dimensions in inches).
Statistical Parameters
Several categories of parameters
appear within this data sheet.
Parameters may be described
with values that are either
“minimum or maximum,” “typical,” or “standard deviations.” The
values for parameters are based
on comprehensive product
characterization data, in which
automated measurements are
made on a large number of parts
taken from 3 non-consecutive
process lots of semiconductor
wafers. The data derived from
product characterization tends to
be normally distributed, e.g., fits
the standard “bell curve.” Parameters considered to be the most
important to system performance
are bounded by minimum or
maximum values. For the
INA-31063, these parameters are:
Power Gain ( |S21| 2), and the
Device Current (Id). Each of these
guaranteed parameters is 100%
tested. Values for most of the
parameters in the table of Electrical Specifications that are described by typical data are the
mathematical mean (µ), of the
normal distribution taken from
the characterization data. For
parameters where measurements
or mathematical averaging may
not be practical, such as
S-parameters or Noise Parameters and the performance
curves, the data represents a
nominal part taken from the
“center” of the characterization
distribution. Typical values are
intended to be used as a basis for
electrical design.
To assist designers in optimizing
not only the immediate circuit
using the INA-31063, but to also
optimize and evaluate trade-offs
that affect a complete wireless
system, the standard deviation
(σ) is provided for three of the
Electrical Specifications parameters (at 25°C) in addition to the
mean. The standard deviation is a
measure of the variability about
the mean. It will be recalled that a
normal distribution is completely
described by the mean and
standard deviation. Standard
statistics tables or calculations
provide the probability of a
parameter falling between any
two values, usually symmetrically
located about the mean. Referring
to Figure 21 for example, the
probability of a parameter being
between ±1σ is 68.3%; between
±2σ is 95.4%; and between ±3σ is
99.7%.
68%
95%
99%
-3σ
-2σ
-1σ Mean +1σ +2σ
(µ), typ
Parameter Value
Figure 21. Normal Distribution.
+3σ
8
SMT Assembly
Reliable assembly of surface
mount components is a complex
process that involves many
material, process, and equipment
factors, including: method of
heating (e.g., IR or vapor phase
reflow, wave soldering, etc.)
circuit board material, conductor
thickness and pattern, type of
solder alloy, and the thermal
conductivity and thermal mass of
components. Components with a
low mass, such as the SOT-363
package, will reach solder reflow
temperatures faster than those
with a greater mass.
The INA-31063 has been qualified
to the time-temperature profile
shown in Figure 22. This profile is
representative of an IR reflow
type of surface mount assembly
process. After ramping up from
room temperature, the circuit
board with components attached
to it (held in place with solder
paste) passes through one or
more preheat zones. The preheat
zones increase the temperature of
the board and components to
prevent thermal shock and begin
evaporating solvents from the
solder paste. The reflow zone
briefly elevates the temperature
sufficiently to produce a reflow of
the solder.
The rates of change of temperature for the ramp-up and cool
down zones are chosen to be low
enough to not cause deformation
of the board or damage to components due to thermal shock.
These parameters are typical for
a surface mount assembly
process for the INA-31063. As a
general guideline, the circuit
board and components should
only be exposed to the minimum
250
TMAX
TEMPERATURE (°C)
200
150
Reflow
Zone
Cool Down
Zone
50
0
0
60
120
180
TIME (seconds)
Figure 22. Surface Mount Assembly Profile.
For more information on mounting considerations for packaged
microwave semiconductors,
please refer to Hewlett-Packard
application note AN-A006.
Electrostatic
Sensitivity
RFICs are electrostatic
discharge (ESD)
sensitive devices. Although the
INA-31063 is robust in design,
permanent damage may occur to
these devices if they are subjected to high-energy electrostatic
discharges. Electrostatic charges
as high as several thousand volts
(which readily accumulate on the
human body and on test equipment) can discharge without
degradation in performance,
reliability, or failure. Electronic
devices may be subjected to ESD
damage in any of the following
areas:
• Storage & handling
• Inspection & testing
• Assembly
• In-circuit use
The INA-31063 is an ESD Class 1
device. Therefore, proper ESD
precautions are recommended
when handling, inspecting,
testing, assembling, and using
these devices to avoid damage.
100
Preheat
Zone
temperatures and times necessary to achieve a uniform reflow
of solder.
240
300
For more information on Electrostatic Discharge and Control refer
to Hewlett-Packard application
note AN-A004R.
9
Package Dimensions
Outline 63 (SOT-363/SC-70)
1.30 (0.051)
REF.
2.20 (0.087)
2.00 (0.079)
1.35 (0.053)
1.15 (0.045)
0.650 BSC (0.025)
0.425 (0.017)
TYP.
2.20 (0.087)
1.80 (0.071)
0.10 (0.004)
0.00 (0.00)
0.30 REF.
1.00 (0.039)
0.80 (0.031)
0.25 (0.010)
0.15 (0.006)
10°
0.30 (0.012)
0.10 (0.004)
0.20 (0.008)
0.10 (0.004)
DIMENSIONS ARE IN MILLIMETERS (INCHES)
INA-31063 Part Number Ordering Information
Part Number
Devices per Container
Container
INA-31063-BLK
100
tape strip in antistatic bag
INA-31063-TR1
3,000
7" reel
INA-31063-TR2
10,000
13" reel
10
Tape Dimensions and Product Orientation
For Outline 63
P
P2
D
P0
E
F
W
C
31
31
D1
t1 (CARRIER TAPE THICKNESS)
Tt (COVER TAPE THICKNESS)
K0
8° MAX.
A0
DESCRIPTION
5° MAX.
B0
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A0
B0
K0
P
D1
2.24 ± 0.10
2.34 ± 0.10
1.22 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.088 ± 0.004
0.092 ± 0.004
0.048 ± 0.004
0.157 ± 0.004
0.039 + 0.010
PERFORATION
DIAMETER
PITCH
POSITION
D
P0
E
1.55 ± 0.05
4.00 ± 0.10
1.75 ± 0.10
0.061 ± 0.002
0.157 ± 0.004
0.069 ± 0.004
CARRIER TAPE
WIDTH
THICKNESS
W
t1
8.00 ± 0.30
0.255 ± 0.013
0.315 ± 0.012
0.010 ± 0.0005
COVER TAPE
WIDTH
TAPE THICKNESS
C
Tt
5.4 ± 0.10
0.062 ± 0.001
0.205 ± 0.004
0.0025 ± 0.00004
DISTANCE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
F
3.50 ± 0.05
0.138 ± 0.002
CAVITY TO PERFORATION
(LENGTH DIRECTION)
P2
2.00 ± 0.05
0.079 ± 0.002
www.hp.com/go/rf
For technical assistance or the location of
your nearest Hewlett-Packard sales
office, distributor or representative call:
Americas/Canada: 1-800-235-0312 or
408-654-8675
Far East/Australasia: Call your local HP
sales office.
Japan: (81 3) 3335-8152
Europe: Call your local HP sales office.
Data subject to change.
Copyright © 1998 Hewlett-Packard Co.
Obsoletes 5967-5770E
Printed in U.S.A.
5967-????E (7/98)