SiC403A, SiC403BCD www.vishay.com Vishay Siliconix 6 A microBUCK® SiC403A/B Integrated Buck Regulator with Programmable LDO DESCRIPTION FEATURES The Vishay Siliconix SiC403A/B an advanced stand-alone synchronous buck regulator featuring integrated power MOSFETs, bootstrap switch, and a programmable LDO in a space-saving PowerPAK MLP55-32L pin packages. • • • • • • • • • • • • • • • • High efficiency > 93 % 6 A continuous output current capability Integrated bootstrap switch Programmable 200 mA LDO with bypass logic Temperature compensated current limit All ceramic solution enabled Pseudo fixed-frequency adaptive on-time control Programmable input UVLO threshold Independent enable pin for switcher and LDO Selectable ultra-sonic power-save mode (SiC403A) Selectable power-save mode (SiC403B) Programmable soft-start 1 % internal reference voltage Power good output Over-voltage and under-voltage protections PowerCAD Simulation software available at www.vishay.com/power-ics/powercad-list/ • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 The SiC403A/B is capable of operating with all ceramic solutions and switching frequencies up to 1 MHz. The programmable frequency, synchronous operation and selectable power-save allow operation at high efficiency across the full range of load current. The internal LDO may be used to supply 5 V for the gate drive circuits or it may be bypassed with an external 5 V for optimum efficiency. Additional features include cycle-by-cycle current limit, voltage soft-start, under-voltage protection, programmable over-current protection, soft shutdown and selectable power-save. The Vishay Siliconix SiC403A/B also provides an enable input and a power good output. PRODUCT SUMMARY Input Voltage Range 3 V to 28 V Output Voltage Range 0.6 V to VIN x 0.75 a Operating Frequency 200 kHz to 1 MHz Continuous Output Current APPLICATIONS • • • • • • 6A Peak Efficiency 93 % Package PowerPAK MLP55-32L Note a. See “High Output Voltage Operation” section Notebook, desktop and server computers Digital HDTV and digital consumer applications Networking and telecommunication equipment Printers, DSL, and STB applications Embedded applications Point of load power supplies TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS EN/PSV (Tri-State) PGOOD LX ILIM PGOOD LX AGND TON ENL VOUT EN\PSV LDO_EN 32 31 30 29 28 27 26 25 FB VOUT VDD AGND FBL VIN VIN 24 1 PAD 1 2 23 AGND 3 22 PAD 3 4 5 LX PAD 2 6 SS 7 BST 21 20 19 VIN LX PGND PGND PGND PGND 16 PGND 15 PGND 13 NC 14 11 10 NC 12 LX VIN 9 VIN VOUT PGND 18 P 17 GND 8 VIN LX Typical Application Circuit for SiC403A/B (PowerPAK MLP5x5-32L) S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM PGOOD EN/PSV VIN 29 A 26 VIN VDD VDD Bootstrap Switch AGND D Control & Status Reference 8 BST 12 NC B LX 13 LXBST 28 LXS C PGND 27 ILIM 14 NC VDD DL SS FB Hi-side MOSFET Soft Start 7 Gate Drive Control On-- time Generator 1 VDD FB Comparator TON 31 VOUT 2 DL Lo-side MOSFET Zero Cross Detector Bypass Comparator Valley Current Limit VDD VDD 3 A VIN Y B LDO VLDO Switchover MUX FBL 5 32 A = connected to pins 6, 9-11, PAD 2 B = connected to pins 23-25, PAD 3 C = connected to pins 15-22 D = connect to pins 4, 30, PAD 1 ENL SiC403A/B Functional Block Diagram LX PGOOD ILIM LX AGND EN\PSV tON ENL PIN CONFIGURATION 32 31 30 29 28 27 26 25 1 VIN 6 7 BST 8 LX 23 LX 22 PGND 21 PGND 20 PGND 19 PGND 18 PGND 17 PGND PAD 2 VIN VIN 9 SS LX 24 PGND 16 5 PGND 15 4 FBL PAD 3 LX 13 AGND AGND NC 14 3 NC 12 2 VDD VIN 11 VOUT PAD 1 VIN 10 FB SiC403A/B Pin Configuration (Top View) S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION 1 FB Feedback input for switching regulator used to program the output voltage - connect to an external resistor divider from VOUT to AGND. 2 VOUT Switcher output voltage sense pin - also the input to the internal switch-over between VOUT and VLDO. The voltage at this pin must be less than or equal to the voltage at the VDD pin. 3 VDD Bias supply for the IC - when using the internal LDO as a bias power supply, VDD is the LDO output. When using an external power supply as the bias for the IC, the LDO output should be disabled. 4, 30, PAD 1 AGND Analog ground 5 FBL Feedback input for the internal LDO - used to program the LDO output. Connect to an external resistor divider from VDD to AGND. 6, 9 to 11, PAD 2 VIN Input supply voltage 7 SS The soft start ramp will be programmed by an internal current source charging a capacitor on this pin. 8 BST Bootstrap pin - connect a capacitor of at least 100 nF from BST to LX to develop the floating supply for the high-side gate drive. 12, 14 NC No connection 13 LXBST 23 to 25, PAD3 LX LX Boost - connect to the BST capacitor. 15 to 22 PGND 26 PGOOD Open-drain power good indicator - high impedance indicates power is good. An external pull-up resistor is required. 27 ILIM Current limit sense pin - used to program the current limit by connecting a resistor from ILIM to LXS. 28 LXS LX sense - connects to RILIM 29 EN/PSV 31 tON On-time programming input - set the on-time by connecting through a resistor to AGND 32 ENL Enable input for the LDO - connect ENL to AGND to disable the LDO. Drive with logic signal for logic control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND. Switching (phase) node Power ground Enable/power save input for the switching regulator - connect to AGND to disable the switching regulator, connect to VDD to operate with power-save mode and float to operate in forced continuous mode. ORDERING INFORMATION PART NUMBER PACKAGE MARKING (LINE 1: P/N) SiC403ACD-T1-GE3 PowerPAK MLP55-32L SiC403A SiC403BCD-T1-GE3 PowerPAK MLP55-32L SiC403B SiC403DB Reference board Format: LINE 1: P/N LINE 2: Siliconix logo + Lot code + ESD symbol LINE 3: Factory code + Year code + Work week code S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) ELECTRICAL PARAMETER VIN CONDITIONS LIMITS to PGND -0.3 to +30 VIN to VDD -0.4 max. LX to PGND -0.3 to +30 LX (Transient < 100 ns) to PGND -2 to +30 VDD to PGND -0.3 to +6 Reference to AGND -0.3 to + (VDD + 0.3) to PGND -0.3 to + (VDD - 1.5) EN/PSV, PGOOD, ILIM, SS, VOUT, FB, FBL tON BST to LX -0.3 to +6 to PGND -0.3 to +35 ENL UNIT V -0.3 to VIN AGND to PGND -0.3 to +0.3 Temperature Maximum Junction Temperature 150 Storage Temperature °C -65 to +150 Power Dissipation Junction to Ambient Thermal Impedance (RthJA) b Maximum Power Dissipation IC Section 50 Ambient Temperature = 25 °C 3.4 Ambient Temperature = 100 °C 1.3 HBM 2 CDM 1 °C/W W ESD Protection kV Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability . RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V) PARAMETER SYMBOL MIN. Input Voltage VIN 3 3 5.5 VOUT 0.6 VIN x 0.75 VDD to PGND Output Voltage TYP. MAX. UNIT 28 V Temperature Ambient Temperature S14-2048-Rev. B, 13-Oct-14 -40 to +85 °C Document Number: 62768 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS PARAMETER SYMBOL TEST CONDITIONS UNLESS SPECIFIED VIN = 12 V, VDD = 5 V, TA = +25 °C for typ., -40 °C to +85 °C for min. and max., TJ = < 125 °C, typical application circuit MIN. TYP. MAX. UNIT Input Power Supplies Input Supply Voltage VIN 3 - 28 VDD VDD 3 - 5.5 VIN UVLO Threshold a VUVLO VIN UVLO Hysteresis VUVLO, HYS VDD UVLO Threshold VUVLO VDD UVLO Hysteresis VUVLO, HYS VIN Supply Current VDD Supply Current IIN IDD FB On-Time Threshold Frequency Range fSW Sensed at ENL pin, rising 2.4 2.6 2.95 Sensed at ENL pin, falling 2.23 2.4 2.57 - 0.25 - Measured at VDD pin, rising 2.5 - 3 Measured at VDD pin, falling 2.4 - 2.9 - 0.2 - ENL, EN/PSV = 0 V, VIN = 28 V - 12 20 Standby mode; ENL = VDD, EN/PSV = 0 V - 160 - V μA ENL, EN/PSV = 0 V - 190 300 SiC403A, EN/PSV = VDD, no load (fSW = 25 kHz), VFB > 0.6 V b - 0.3 - SiC403B, EN/PSV = VDD, no load, VFB > 0.6 V b - 0.7 - VDD = 5 V, fSW = 250 kHz, EN/PSV = floating, no load b - 8 - VDD = 3 V, fSW = 250 kHz, EN/PSV = floating, no load b - 5 - Static VIN and load 0.594 0.600 0.606 Continuous mode operation - - 1000 Minimum fSW, (SiC403A only) - 25 - - 10 - 999 1110 1220 - 80 - VDD = 5 V - 250 - VDD = 3 V - 370 - - 3 - μA - 1.5 - V - 500 - k +3 mV Bootstrap Switch Resistance mA V kHz Timing On-Time Minimum On-Time b Minimum Off-Time b tON Continuous mode operation VIN = 12 V, VOUT = 5 V, fSW = 300 kHz, Rton = 133 k tON, min. tOFF, min. ns Soft Start Soft Start Current b ISS Soft Start Voltage b VSS When VOUT reaches regulation Analog Inputs/Outputs VOUT Input Resistance RO-IN Current Sense Zero-Crossing Detector Threshold Voltage VSense-th LX-PGND -3 - PG_VTH_UPPER Upper limit, VFB > internal 600 mV reference - +20 - PG_VTH_LOWER Lower limit, VFB < internal 600 mV reference - -10 - VDD = 5 V, CSS = 10 nF - 12 - VDD = 3 V, CSS = 10 nF - 7 - Power Good Power Good Threshold % Start-Up Delay Time (between PWM enable and PGOOD high) PG_Td Fault (noise-immunity) Delay Time b PG_ICC - 5 - μs Leakage Current PG_ILK - - 1 μA PG_RDS_ON - 10 - Power Good On-Resistance S14-2048-Rev. B, 13-Oct-14 ms Document Number: 62768 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS TEST CONDITIONS UNLESS SPECIFIED VIN = 12 V, VDD = 5 V, TA = +25 °C for typ., -40 °C to +85 °C for min. and max., TJ = < 125 °C, typical application circuit MIN. VDD = 5 V, RILIM = 4750, TJ = 0 °C to +125 °C VDD = 3.3 V, RILIM = 4750 VILM-LK With respect to AGND Output Under-Voltage Fault VOUT_Fault VFB with respect to Internal 600 mV reference, 8 consecutive clocks Smart Power-Save Protection Threshold Voltage b PSave_VTH PARAMETER SYMBOL TYP. MAX. UNIT 4.8 6 7.2 - 5.1 - - 10 - μA -10 0 +10 mV - -25 - VFB with respect to internal 600 mV - +10 - VFB with respect to internal 600 mV - +20 - - 5 - μs - 150 - °C Fault Protection Valley Current Limit ILIM ILIM Source Current ILIM Comparator Offset Voltage Over-Voltage Protection Threshold Over-Voltage Fault Delay b tOV-Delay Over Temperature Shutdown b TShut 10 °C hysteresis A % Logic Inputs/Outputs Logic Input High Voltage VIH 1 - - Logic Input Low Voltage VIL - - 0.4 2.2 - 5 1 - 2 EN/PSV Input for P-Save Operation b VDD = 5 V EN/PSV Input for Forced Continuous Operation b EN/PSV Input for Disabling Switcher EN/PSV Input Bias Current IEN ENL Input Bias Current FBL, FB Input Bias Current EN/PSV = VDD or GND 0 - 0.4 -10 - +10 IENL ENL = VIN = 28 V - 11 18 FBL_ILK FBL, FB = VDD or GND -1 - +1 V μA Linear Dropout Regulator FBL b VLDO ACC LDO Current Limit 0.75 - - 65 - Start-up and foldback, VIN = 12 V, 0.75 < VDD < 90 % of final VDD value - 115 - Operating current limit, VIN = 12 V, VDD > 90 % of final VDD value 135 200 - VLDO-BPS -130 - +130 VLDO-NBPS -500 - +500 VOUT = 5 V - 2 - From VIN to VDD, VDD = +5 V, IVLDO = 100 mA - 1.2 - V LDO_ILIM VLDO to VOUT Switch-over Threshold d VLDO to VOUT Non-switch-over Threshold VLDO to VOUT Switch-over Resistance LDO Drop Out Voltage Short-circuit protection, VIN = 12 V, VDD < 0.75 V e d RLDO V mA mV Notes a. VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference. b. Typical value measured on standard evaluation board. c. SiC403A/B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout. d. The switch-over threshold is the maximum voltage differential between the VLDO and VOUT pins which ensures that VLDO will internally switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures that VLDO will not switch-over to VOUT. e. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point. S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS 2.5 100 1.26 0.14 2 VIN=20V V IN=6V REGULATION 1.5 1 40 VOUT(VDC) PLOSS(W) Efficiency(%) 1.22 VIN=12V 60 0.08 0.06 0.04 1.16 VIN=6V 0 0.1 Vin=6V 1.2 0.5 V IN=20V 0.01 0.1 1.18 VIN=12V 20 0.001 0.12 Vin=12V Vin=20V VPEAK(Vrms) 80 1.24 1 0 Vin=20V 0.001 0.02 Vin=6V Vpeak 1.14 10 Vin=12V 0 0.01 0.1 1 10 IOUT(A) IOUT(A) Efficiency vs. Load-Forced Continuous Mode VOUT = 1.2 V, VDD = 5 V, EN/PSV is Floating, External Bias, SiC403B VOUT vs. Load-Forced Continuous Mode VOUT = 1.2 V, VDD = 5 V, EN/PSV is Floating, External Bias, SiC403B Efficiency Vin=6V 0.12 1.26 2.5 100 Vin=12V 1.24 Vin=20V 80 0.1 Vin=12V 2 Vin=20 1 40 VOUT(VDC) PLOSS(W) Efficiency(%) Regula o Vin=6 1.2 0.06 VPEAK(Vrms) 0.08 1.22 1.5 60 0.04 1.18 Vin=12 Vin=20V 20 0.5 1.16 Vin=12V Vin=6 Vin=6V 0.01 0.1 1 0 1.14 0 0 0.001 0.02 Vin=20 Vpeak PLOSS 0.001 10 0.01 0.1 1 10 IOUT(A) IOUT(A) Efficiency vs. Load-PSAVE Mode VOUT = 1.2 V, VDD = EN/PSV = 5 V, External Bias, SiC403B 100 VOUT vs. Load-PSAVE Mode VOUT = 1.2 V, VDD = EN/PSV = 5 V, External Bias, SiC403B 2.5 1.26 0.12 1.24 0.1 VDD=3.3V VDD=5V 2 VDD=5V 40 1 VDD=5V 20 Regula on 1.2 0.06 1.18 0.04 0.5 1.16 VDD=3.3V 0 0.01 0.1 0.02 VDD=5V VPEAK VDD =3.3V 0 0.001 0.08 VDD=3.3V VPEAK(Vrms) 1.5 VOUT(VDC) 1.22 60 PLOSS(W) Efficiency(%) 80 1 10 0 1.14 0.001 0.01 0.1 1 10 OUT(A) IOUT(A) Efficiency vs. Load-PSAVE Mode VOUT = 1.2 V, VIN = 12 V, VDD = EN/PSV = 5 V, External Bias, SiC403B VOUT vs. Load-PSAVE Mode VOUT = 1.2 V, VIN = 12 V, VDD = EN/PSV = 5 V, External Bias, SiC403B S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS 400 400 350 350 VIN=12V 300 VIN=6V Frequency(kHz) Frequency(kHz) 300 250 VIN=20V 200 150 250 VIN=20V VIN=12V 200 150 100 100 50 50 0 VIN=6V 0 0.01 0.1 1 10 0.001 0.01 0.1 1 10 IOUT(ADC) IOUT(ADC) Frequency vs. Load-PSAVE Mode VOUT = 1.2 V, VDD = EN/PSV = 5 V, External Bias, SiC403B Frequency vs. Load-Forced Continuous Mode VOUT = 1.2 V, VDD = 5 V, EN/PSV is Floating, External Bias, SiC403B 1.575 0.150 1.55 0.125 400 350 1.5 0.075 1.475 0.050 Vpeak 1.45 Frequency(kHz) 0.100 VOUT VPEAK(Vrms) VOUT(VDC) 1.525 300 0.025 1.425 8.8 11.6 14.4 17.2 20 22.8 200 150 100 50 0 0.000 6 250 6 25.6 8 10 12 VIN(VDC) 14 16 18 20 22 24 26 28 VIN(VDC) VOUT vs. Line-Forced Continuous Mode VOUT = 1.5 V, VLDO = VDD = ENL = 5 V, EN/PSV is Floating, SiC403B Frequency vs. Line-FCM Mode VOUT = 1.5 V, VLDO = VDD = ENL = 5 V, EN/PSV is Floating, SiC403B 1200 2.5 100 1000 80 VIN=6V 2 VIN=20V 600 3.3V 400 60 1.5 VIN=12V 1 40 PLOSS(W) Efficiency(%) On-Time(ns) 800 VIN=20V 5V 200 20 0.5 VIN=12V VIN=6V 0 0 0 6 8 10 12 14 16 18 20 22 24 26 28 Input Voltage(V) On Time vs. Line VOUT = 1.5 V, VLDO = VDD = ENL = 5 V, IOUT = 0 A, SiC403B S14-2048-Rev. B, 13-Oct-14 0.001 0.01 0.1 IOUT(ADC) 1 10 Efficiency vs. Load-Forced Continuous Mode VOUT = 1.2 V, VDD = 5 V, EN/PSV is Floating, External Bias, SiC403A Document Number: 62768 8 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS 100 90 2 80 2.5 1.5 Efficiency 40 1 VIN=20V 30 20 10 0.5 VIN=12V VIN=6V 0 0.001 Efficiency 60 1.5 V DD=5V 1 40 0.5 20 VDD=5V Ploss PLOSS 0.01 0.1 1 2 VDD3.3V VDD=3.3V 0 0 0 0.001 0.01 10 0.1 1 10 IOUT(ADC) IOUT(ADC) Efficiency vs. Load-PSAVE Mode VOUT = 1.2 V, VDD = 5 V = EN/PSV, External Bias, SiC403A PLOSS(W) VIN=20V Efficiency(%) VIN=12V 60 PLOSS(W) 70 Efficiency(%) 100 VIN=6V 80 50 2.5 Efficiency vs. Load-PSAVE Mode VOUT = 1.2 V, VIN = 12 V, VDD = EN/PSV = 5 V, External Bias, SiC403A Vout Vout (50mV/div) (20mV/div) LX LX (5V/div) (5V/div) Time(20µs/div) Powersave Mode - No Load VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A, VDD = EN/PSV = ENL = 5 V, SiC403A (10V/div) LX Time(2µs/div) Forced Continuous Mode - No Load VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A, VDD = EN/PSV = ENL = 5 V (10V/div) Vout Vout (500mV/div) (500mV/div) VDD VDD (5V/div) (5V/div) LX (5V/div) Pgood Pgood (5V/div) Time(1ms/div) Time(1ms/div) Self-Biased Start-Up - Power Good True VIN = 12 V step, VOUT = 1.2 V, IOUT = 0 A, VDD = EN/PSV = ENL = 5 V Enable Start-Up - Power Good True VIN = 12 V, VOUT = 1.2 V, IOUT = 1 A, VDD = EN/PSV= 5 V S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 9 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS Vout (20mV/div) LX (5V/div) Time(10ms/div) Powersave Mode - No Load VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A, VDD = EN/PSV = ENL = 5 V, SiC403B Vout Vout (500mV/div) (200mV/div) IOUT (5A/div) LX LX (10V/div) (10V/div) Pgood (5V/div) (5V/div) Pgood Time(200µs/div) Time(500µs/div) Output Under-Voltage Response VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A, VDD = ENL = 3.3 V, EN/PSV is floating (500mV/div) Output Over-Current Response VIN = 12 V, VOUT = 1.2 V, VDD = ENL = 3.3 V, EN/PSV is floating VOUT Vout (200mV/div) IOUT IOUT (5A/div) (5A/div) LX LX (10V/div) (10V/div) Pgood (5V/div) Pgood (5V/div) Time(50µs/div) Short Output Response VIN = 12 V, VOUT = 1.2 V, VDD = ENL = 3.3 V, EN/PSV is floating S14-2048-Rev. B, 13-Oct-14 Time(500µs/div) Shorted Output Response at Soft-Start Operation VIN = 12 V, VOUT = 1.2 V, VDD = ENL = 3.3 V, EN/PSV is floating Document Number: 62768 10 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS Vout Vout (100mV/div) (100mV/div) LX LX (10V/div) (2A/div) (10V/div) IOUT (2A/div) Iout Time(10µs/div) Transient Response in Power Saving Mode VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A to 6 A, VDD = EN/PSV = 5 V Time(10µs/div) Transient Response in Forced Continuous Mode VIN = 12 V, VOUT = 1.2 V, IOUT = 0 A to 6 A, VDD = EN/PSV = 5 V OPERATIONAL DESCRIPTION Device Overview The SiC403A/B is a step down synchronous DC/DC buck converter with integrated power MOSFETs and a 200 mA capable programmable LDO. The device is capable of 6 A operation at very high efficiency. A space saving 5 x 5 (mm) 32-pin package is used. The programmable operating frequency of up to 1 MHz enables optimizing the configuration for PCB area and efficiency. The buck controller uses a pseudo-fixed frequency adaptive on-time control. This control method allows fast transient igponse which permits the use of smaller output capacitors. logic low, the output voltage discharges into the VOUT pin through an internal FET. Pseudo-Fixed Frequency Adaptive On-Time Control The PWM control method used by the SiC403A/B is pseudo- fixed frequency, adaptive on-time, as shown in figure 1. The ripple voltage generated at the output capacitor ESR is used as a PWM ramp signal. This ripple is used to trigger the on-time of the controller. tON VIN VLX Input Voltage Requirements The SiC403A/B requires two input supplies for normal operation: VIN and VDD. VIN operates over a wide range from 3 V to 28 V. VDD requires a 3 V to 5.5 V supply input that can be an external source or the internal LDO configured to supply 3 V to 5.5 V from VIN. Power Up Sequence When the SiC403A/B uses an external power source at the VDD pin, the switching regulator initiates the start up when VIN, VDD, and EN/PSV are above their respective thresholds. When EN/PSV is at logic high, VDD needs to be applied after VIN rises. It is also recommended to use a 10 resistor between an external power source and the VDD pin. To start up by using the EN/PSV pin when both VDD and VIN are above their respective thresholds, apply EN/PSV to enable the start-up process. For SiC403A/B in self-biased mode, refer to the LDO section for a full description. Shutdown The SiC403A/B can be shut-down by pulling either VDD or EN/PSV below its threshold. When using an external power source, it is recommended that the VDD voltage ramps down before the VIN voltage. When VDD is active and EN/PSV at S14-2048-Rev. B, 13-Oct-14 CIN VFB Q1 VLX FB threshold VOUT L Q2 ESR FB + COUT Fig. 1 - Output Ripple and PWM Control Method The adaptive on-time is determined by an internal one- shot timer. When the one-shot is triggered by the output ripple, the device sends a single on-time pulse to the high- side MOSFET. The pulse period is determined by VOUT and VIN; the period is proportional to output voltage and inversely proportional to input voltage. With this adaptive on-time arrangement, the device automatically anticipates the on-time needed to regulate VOUT for the present VIN condition and at the selected frequency. Document Number: 62768 11 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix The advantages of adaptive on-time control are: k is shown by the following equation. • Predictable operating frequency compared to other variable frequency methods. • Reduced component count by eliminating the error amplifier and compensation components. k= The maximum RtON value allowed is shown by the following equation • Reduced component count by removing the need to sense and control inductor current. • Fast transient response - the response time is controlled by a fast comparator instead of a typically slow error amplifier. (VDD - 1.75) x 10 VIN Rton = (ton - 10 ns) x VIN 25 pF x VOUT • Reduced output capacitance due to fast transient response. Immediately after the on-time, the DL (drive signal for the low side FET) output drives high to turn on the low-side MOSFET. DL has a minimum high time of ~320 ns, after which DL continues to stay high until one of the following occurs: One-Shot Timer and Operating Frequency • VFB falls below the reference The one-shot timer operates as shown in figure 2. The FB comparator output goes high when VFB is less than the internal 600 mV reference. This feeds into the gate drive and turns on the high-side MOSFET, and also starts the one-shot timer. The one-shot timer uses an internal comparator and a capacitor. One comparator input is connected to VOUT, the other input is connected to the capacitor. When the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to VIN. When the capacitor voltage reaches VOUT, the on-time is completed and the high-side MOSFET turns off. • The zero cross detector senses that the voltage on the LX node is below ground. Power save is activated eight switching cycles after a zero crossing is detected. Gate drives FB comparator FB VREF + DH VOUT VIN Rton DL Q1 VLX VOUT L Q2 COUT FB + On-time = K x Rton x (VOUT/VIN) Fig. 2 - On-Time Generation This method automatically produces an on-time that is proportional to VOUT and inversely proportional to VIN. Under steady-state conditions, the switching frequency can be determined from the on-time by the following equation. fSW = VOUT tON x VIN The SiC403A/B uses an external resistor to set the on-time which indirectly sets the frequency. The on-time can be programmed to provide an operating frequency from 200 kHz to 1 MHz using a resistor between the tON pin and ground. The resistor value is selected by the following equation. Rton = k 25 pF x fSW The constant, k, equals 1, when VDD is greater than 3.6 V. If VDD is less than 3.6 V and VIN is greater than (VDD -1.75) x 10, S14-2048-Rev. B, 13-Oct-14 For VDD below 4.5 V, the tON accuracy may be limited by the input voltage. The original RtON equation is accurate if VIN satisfies the relationship over the entire VIN range, as follows. VIN < (VDD - 1.6 V) x 10 If VIN exceeds (VDD - 1.6 V) x 10, for all or part of the VIN range, the RtON equation is not accurate. In all cases where VIN > (VDD - 1.6 V) x 10, the RtON equation must be modified, as follows. Rton = ESR One-shot timer tON Limitations and VDD Supply Voltage (ton - 10 ns) x (VDD - 1.6 V) x 10 25 pF x VOUT Note that when VIN > (VDD - 1.6 V) x 10, the actual on-time is fixed and does not vary with VIN. When operating in this condition, the switching frequency will vary inversely with VIN rather than approximating a fixed frequency. VOUT Voltage Selection The switcher output voltage is regulated by comparing VOUT as seen through a resistor divider at the FB pin to the internal 600 mV reference voltage, see figure 3. To FB pin VOUT R1 R2 Fig. 3 - Output Voltage Selection Note that this control method regulates the valley of the output ripple voltage, not the DC value. The DC output voltage VOUT is offset by the output ripple according to the following equation. VOUT = 0.6 x 1 + R1 R2 + VRIPPLE 2 Document Number: 62768 12 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix When a large capacitor is placed in parallel with R1 (CTOP) VOUT is shown by the following equation. VOUT = 0.6 x 1 + R1 R2 + VRIPPLE 2 1 + (R1ωCTOP)2 x 1+ R2 x R1 ωC R2 + R1 TOP 2 Enable and Power-Save Inputs The EN/PSV input is used to enable or disable the switching regulator. When EN/PSV is low (grounded), the switching regulator is off and in its lowest power state. When off, the output of the switching regulator soft-discharges the output into a 15 internal resistor via the VOUT pin. When EN/PSV is allowed to float, the pin voltage will float to 33 % of the voltage at VDD. The switching regulator turns on with power-save disabled and all switching is in forced continuous mode. When EN/PSV is high (above 44 % of the voltage at VDD), the switching regulator turns on with power-save enabled. The SiC403A/B P-Save operation reduces the switching frequency according to the load for increased efficiency at light load conditions. Forced Continuous Mode Operation The SiC403A/B operates the switcher in FCM (Forced Continuous Mode) by floating the EN/PSV pin (see figure 4). In this mode one of the power MOSFETs is always on, with no intentional dead time other than to avoid cross-conduction. This feature results in uniform frequency across the full load range with the trade-off being poor efficiency at light loads due to the high-frequency switching of the MOSFETs. DH is gate signal to drive upper MOSFET. DL is lower gate signal to drive lower MOSFET. Ultrasonic Power-Save Operation (SiC403A) The SiC403A provides ultrasonic power-save operation at light loads, with the minimum operating frequency fixed at slightly under 25 kHz. This is accomplished by using an internal timer that monitors the time between consecutive high-side gate pulses. If the time exceeds 40 μs, DL drives high to turn the low-side MOSFET on. This draws current from VOUT through the inductor, forcing both VOUT and VFB to fall. When VFB drops to the 600 mV threshold, the next DH (the drive signal for the high side FET) on-time is triggered. After the on-time is completed the high-side MOSFET is turned off and the low-side MOSFET turns on. The low-side MOSFET remains on until the inductor current ramps down to zero, at which point the low-side MOSFET is turned off. Because the on-times are forced to occur at intervals no greater than 40 μs, the frequency will not fall far below 25 kHz. Figure 5 shows ultrasonic power-save operation. minimum fSW ~ 25 kHz FB ripple voltage (VFB) FB threshold (600 mV) (0A) Inductor current On-time (tON) DH on-time is triggered when VFB reaches the FB threshold DH 40 µs time-out DL After the 40 µs time-out, DL drives high if VFB has not reached the FB threshold. FB ripple voltage (VFB) FB threshold (600 mV) DC load current Inductor current On-time (tON) DH on-time is triggered when VFB reaches the FB threshold DH DL DL drives high when on-time is completed. DL remains high until VFB falls to the FB threshold. Fig. 4 - Forced Continuous Mode Operation S14-2048-Rev. B, 13-Oct-14 Fig. 5 - Ultrasonic Power-Save Operation Power-Save Operation (SiC403B) The SiC403B provides power-save operation at light loads with no minimum operating frequency. With power-save enabled, the internal zero crossing comparator monitors the inductor current via the voltage across the low-side MOSFET during the off-time. If the inductor current falls to zero for 8 consecutive switching cycles, the controller enters MOSFET on each subsequent cycle provided that the power-save operation. It will turn off the low-side MOSFET on each subsequent cycle provided that the current crosses zero. At this time both MOSFETs remain off until VFB drops to the 600 mV threshold. Because the MOSFETs are off, the load is supplied by the output capacitor. If the inductor current does not reach zero on any switching cycle, the controller immediately exits power-save and returns to forced continuous mode. Figure 6 shows power-save operation at light loads. Document Number: 62768 13 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix circuit automatically drives the high-side MOSFET on at a rapid rate. This technique reduces switching losses while maintaining high efficiency and also avoids the need for snubbers for the power MOSFETs. Current Limit Protection Smart Power-Save Protection Active loads may leak current from a higher voltage into the switcher output. Under light load conditions with power-save enabled, this can force VOUT to slowly rise and reach the over-voltage threshold, resulting in a hard shut-down. Smart power-save prevents this condition. When the FB voltage exceeds 10 % above nominal, the device immediately disables power-save, and DL drives high to turn on the low-side MOSFET. This draws current from VOUT through the inductor and causes VOUT to fall. When VFB drops back to the 600 mV trip point, a normal tON switching cycle begins. This method prevents a hard OVP shut-down and also cycles energy from VOUT back to VIN. It also minimizes operating power by avoiding forced conduction mode operation. Figure 7 shows typical waveforms for the Smart Power Save feature. VOUT drifts up to due to leakage current flowing into COUT Smart power save threshold (825 mV) VOUT discharges via inductor and low-side MOSFET Normal VOUT ripple FB threshold DH and DL off IPEAK Inductor Current Fig. 6 - Power-Save Mode The device features programmable current limiting, which is accomplished by using the RDS-on of the lower MOSFET for current sensing. The current limit is set by RILIM resistor. The RILIM resistor connects from the ILIM pin to the LXS pin which is also the drain of the low-side MOSFET. When the low-side MOSFET is on, an internal ~ 10 μA current flows from the ILIM pin and through the RILIM resistor, creating a voltage drop across the resistor. While the low-side MOSFET is on, the inductor current flows through it and creates a voltage across the RDS-on. The voltage across the MOSFET is negative with respect to ground. If this MOSFET voltage drop exceeds the voltage across RILIM, the voltage at the ILIM pin will be negative and current limit will activate. The current limit then keeps the low-side MOSFET on and will not allow another high-side on-time, until the current in the low-side MOSFET reduces enough to bring the ILIM voltage back up to zero. This method regulates the inductor valley current at the level shown by ILIM in figure 8. ILOAD ILIM Time Fig. 8 - Valley Current Limit Setting the valley current limit to 6 A results in a peak inductor current of 6 A plus peak ripple current. In this situation, the average (load) current through the inductor is 6 A plus one-half the peak-to-peak ripple current. The internal 10 μA current source is temperature compensated at 4100 ppm in order to provide tracking with the RDS-on. The RILIM value is calculated by the following equation. High-side drive (DH) RILIM = 792 x ILIM x [0.101 x (5 V - VDD) + 1] Single DH on-time pulse after DL turn-off Low-side drive (DL) DL turns on when smart PSAVE threshold is reached DL turns off FB threshold is reached Normal DL pulse after DH on-time pulse Fig. 7 - Smart Power-Save SmartDriveTM For each DH pulse, the DH driver initially turns on the high side MOSFET at a lower speed, allowing a softer, smooth turn-off of the low-side diode. Once the diode is off and the LX voltage has risen 0.5 V above PGND, the SmartDrive S14-2048-Rev. B, 13-Oct-14 When selecting a value for RILIM be sure not to exceed the absolute maximum voltage value for the ILIM pin. Note that because the low-side MOSFET with low RDS-on is used for current sensing, the PCB layout, solder connections, and PCB connection to the LX node must be done carefully to obtain good results. RILIM should be connected directly to LXS (pin 28). Soft-Start of PWM Regulator SiC403A/B has a programmable soft-start time that is controlled by an external capacitor at the SS pin. After the controller meets both UVLO and EN/PSV thresholds, the controller has an internal current source of 3 μA flowing through the SS pin to charge the capacitor. During the start Document Number: 62768 14 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com up process (figure 9), 50 % of the voltage at the SS pin is used as the reference for the FB comparator. The PWM comparator issues an on-time pulse when the voltage at the FB pin is less than 40 % of the SS pin. As a result, the output voltage follows the SS voltage. The output voltage reaches and maintains regulation when the soft start voltage is 1.5 V. The time between the first LX pulse and VOUT reaching regulation is the soft-start time (tSS). The calculation for the soft-start time is shown by the following equation. tSS = CSS x 1.5 V 3 μA The voltage at the SS pin continues to ramp up and eventually equals 64 % of VDD. After the soft start completes, the FB pin voltage is compared to an internal reference of 0.6 V. The delay time between the VOUT regulation point and PGOOD going high is shown by the following equation. tPGOOD-DELAY = CSS x (0.64 x VDD - 1.5 V) 3 μA Vishay Siliconix Output Over-Voltage Protection Over-voltage protection becomes active as soon as the device is enabled. The threshold is set at 600 mV + 20 % (720 mV). When VFB exceeds the OVP threshold, DL latches high and the low-side MOSFET is turned on. DL remains high and the controller remains off, until the EN/PSV input is toggled or VDD is cycled. There is a 5 μs delay built into the OVP detector to prevent false transitions. PGOOD is also low after an OVP event. Output Under-Voltage Protection When VFB falls 25 % below its nominal voltage (falls to 450 mV) for eight consecutive clock cycles, the switcher is shut off and the DH and DL drives are pulled low to tristate the MOSFETs. The controller stays off until EN/PSV is toggled or VDD is cycled. VDD UVLO, and POR UVLO (Under-Voltage Lock-Out) circuitry inhibits switching and tri-states the DH/DL drivers until VDD rises above 3 V. An internal POR (Power-On Reset) occurs when VDD exceeds 3 V, which resets the fault latch and a soft-start counter cycle begins which prepares for soft-start. The SiC403A/B then begins a soft-start cycle. The PWM will shut off if VDD falls below 2.4 V. LDO Regulator SiC403A/B has an option to bias the switcher by using an internal LDO from VIN. The LDO output is connected to VDD internally. The output of the LDO is programmable by using external resistors from the VDD pin to AGND (see figure 10). The feedback pin (FBL) for the LDO is regulated to 750 mV. Fig. 9 - Soft-start Timing Diagram Pre-Bias Start-Up The SiC403A/B can start up normally even when there is an existing output voltage present. The soft start time is still the same as normal start up (when the output voltage starts from zero). The output voltage starts to ramp up when 40 % of the voltage at SS pin meets the existing FB voltage level. Pre-bias startup is achieved by turning off the lower gate when the inductor current falls below zero. This method prevents the output voltage from discharging. Fig. 10 - LDO Output Voltage Selection The LDO output voltage is set by the following equation. VLDO = 750 mV x 1 + RLDO1 RLDO2 A minimum capacitance of 1 μF referenced to AGND is normally required at the output of the LDO for stability. Note that if the LDO voltage is set lower than 4.5 V, the minimum output capacitance for the LDO is 10 μF. Power Good Output The PGOOD (power good) output is an open-drain output which requires a pull-up resistor. When the voltage at the FB pin is 10 % below the nominal voltage, PGOOD is pulled low. It is held low until the output voltage returns above -8 % of nominal. PGOOD will transition low if the VFB pin exceeds +20 % of nominal, which is also the over-voltage shutdown threshold. PGOOD also pulls low if the EN/PSV pin is low when VDD is present. S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 15 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix LDO ENL Functions has reached 90 % of its final regulation value. The ENL input is used to enable/disable the internal LDO. When ENL is a logic low, the LDO is off. When ENL is above the VIN UVLO threshold, the LDO is enabled and the switcher is also enabled if the EN/PSV and VDD are above their threshold. The table below summarizes the function of ENL and EN/PSV pins. EN/PSV ENL LDO SWITCHER Disabled Low, < 0.4 V Off Off Fig. 11 - LDO Start-Up Enabled Low, < 0.4 V Off On LDO Switch-Over Operation Disabled 1 V < High < 2.6 V On Off Enabled 1 V < High < 2.6 V On Off The SiC403A/B includes a switch-over function for the LDO. The switch-over function is designed to increase efficiency by using the more efficient DC/DC converter to power the LDO output, avoiding the less efficient LDO regulator when possible. The switch-over function connects the VDD pin directly to the VOUT pin using an internal switch. When the switch-over is complete the LDO is turned off, which results in a power savings and maximizes efficiency. If the LDO output is used to bias the SiC403A/B, then after switch-over the device is self-powered from the switching regulator with the LDO turned off. Disabled High, > 2.6 V On Off Enabled High, > 2.6 V On On The ENL pin also acts as the switcher under-voltage lockout for the VIN supply. When SiC403A/B is self-biased from the LDO and runs from the VIN power source only, the VIN UVLO feature can be used to prevent false UV faults for the PWM output by programming with a resistor divider at the VIN, ENL and AGND pins. When SiC403A/B has an external bias voltage at VDD and the ENL pin is used to program the VIN UVLO feature, the voltage at FBL needs to be higher than 750 mV to force the LDO off. Timing is important when driving ENL with logic and not implementing VIN UVLO. The ENL pin must transition from high to low within 2 switching cycles to avoid the PWM output turning off. If ENL goes below the VIN UVLO threshold and stays above 1 V, then the switcher will turn off but the LDO will remain on. LDO Start-up Before start-up, the LDO checks the status of the following signals to ensure proper operation can be maintained. 1. ENL pin 2. VLDO output When the ENL pin is high and VIN is above the UVLO point, the LDO will begin start-up. During the initial phase, when the VDD voltage (which is the LDO output voltage) is less than 0.75 V, the LDO initiates a current-limited start-up (typically 65 mA) to charge the output capacitors while protecting from a short circuit event. When VDD is greater than 0.75 V but still less than 90 % of its final value (as sensed at the FBL pin), the LDO current limit is increased to ~115 mA. When VDD has reached 90 % of the final value (as sensed at the FBL pin), the LDO current limit is increased to ~200 mA and the LDO output is quickly driven to the nominal value by the internal LDO regulator. It is recommended that during LDO start-up to hold the PWM switching off until the LDO has reached 90 % of the final value. This prevents overloading the current-limited LDO output during the LDO start-up. The switch-over starts 32 switching cycles after PGOOD output goes high. The voltages at the VDD and VOUT pins are then compared; if the two voltages are within ± 300 mV of each other, the VDD pin connects to the VOUT pin using an internal switch, and the LDO is turned off. To avoid unwanted switch-over, the minimum difference between the voltages for VOUT and VDD should be ± 500 mV. It is not recommended to use the switch-over feature for an output voltage less than VDD UVLO threshold since the SiC403A/B is not operational below that threshold. Switch-Over MOSFET Parasitic Diodes The switch-over MOSFET contains parasitic diodes that are inherent to its construction, as shown in figure 12. If the voltage at the VOUT pin is higher than VDD, then the respective diode will turn on and the current will flow through this diode. This has the potential of damaging the device. Therefore, VOUT must be less than VDD to prevent damaging the device. Switchover control Switchover MOSFET VOUT LDO Parastic diode VDD Fig. 12 - Switch-over MOSFET Parasitic Diodes Due to the initial current limitations on the LDO during power up (figure 11), any external load attached to the VDD pin must be limited to less than the start up current before the LDO S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 16 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix Design Procedure all used in the selection process. When designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specified. The ripple current will also set the boundary for PSave operation. The switching will typically enter PSave mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 4 A then PSave operation will typically start for loads less than 2 A. If ripple current is set at 40 % of maximum load current, then PSave will start for loads less than 20 % of maximum current. The maximum input voltage (VIN max.) is the highest specified input voltage. The minimum input voltage (VIN min.) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and PCB traces. The following parameters define the design: • Nominal output voltage (VOUT) • Static or DC output tolerance • Transient response • Maximum load current (IOUT) There are two values of load current to evaluate - continuous load current and peak load current. Continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. The following values are used in this design: • VIN = 12 V ± 10 % The inductor value is typically selected to provide a ripple current that is between 25 % to 50 % of the maximum load current. This provides an optimal trade-off between cost, efficiency, and transient performance. During the on-time, voltage across the inductor is (VIN - VOUT). The equation for determining inductance is shown next. L= Example In this example, the inductor ripple current is set equal to 50 % of the maximum load current. Thus ripple current will be 50 % x 6 A or 3 A. To find the minimum inductance needed, use the VIN and tON values that correspond to VINmax.. L= • VOUT = 1.5 V ± 4 % • fSW = 300 kHz (VIN - VOUT) x tON IRIPPLE (13.2 - 1.5) x 379 ns = 1.48 µH 3A A slightly larger value of 1.5 μH is selected. This will decrease the maximum IRIPPLE to 2.7 A. • Load = 6 A max. Frequency Selection Selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. Note that the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current. The ripple current under minimum VIN conditions is also checked using the following equations. The desired switching frequency is 300 kHz which results from using component selected for optimum size and cost. tON_VINmin. = A resistor (RtON) is used to program the on-time (indirectly setting the frequency) using the following equation. IRIPPLE = Rton = (ton - 10 ns) x VIN tON = VOUT VINmax. x fSW Substituting for RtON results in the following solution. RtON = 129.9 k, use RtON = 130 k. Inductor Selection In order to determine the inductance, the ripple current must first be defined. Low inductor values result in smaller size but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple current/voltage and for a given DC resistance are more efficient. However, larger inductance translates directly into larger packages and higher cost. Cost, size, output ripple, and efficiency are S14-2048-Rev. B, 13-Oct-14 + 10 ns = 461 ns (VIN - VOUT) x tON L IRIPPLE_min. = (10.8 V - 1.5 V) x 461 ns = 2.38 A 1.5 µH x (1 + 0.2) IRIPPLE_max. = (10.8 V - 1.5 V) x 379 ns = 3.7 A 1.5 µH x (1 - 0.2) 25 pF x VOUT To select RtON, use the maximum value for VIN, and for tON use the value associated with maximum VIN. 25 pF x RtON x VOUT VINmin. Capacitor Selection The output capacitors are chosen based upon required ESR and capacitance. The maximum ESR requirement is controlled by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. A change in the output ripple voltage will lead to a change in DC voltage at the output. The design goal for output voltage ripple is 4 % of 1.5 V or 60 mV. The maximum ESR value allowed is shown by the following equations. Document Number: 62768 17 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com VRIPPLE ESRmax. = IRIPPLEmax. Vishay Siliconix = 60 mV 3.7 A ESRmax. = 16.2 mΩ Stability Considerations The output capacitance is usually chosen to meet transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1 μs), the output capacitor must absorb all the inductor's stored energy. This will cause a peak voltage on the capacitor according to the following equation. 1 xI )2 2 RIPPLEmax. (VPEAK)2 - (VOUT)2 L (IOUT + COUT_min. = Assuming a peak voltage VPEAK of 1.6 V (150 mV rise upon load release), and a 6 A load release, the required capacitance is shown by the next equation. 1 x 3.7)2 2 (1.6)2 - (1.5)2 1.5 µH x (6 + COUT_min. = compared to 298 μF based on a worst case load release. To meet the two design criteria of minimum 298 μF and maximum 16 m ESR, select one capacitor of 330 μF and 9 m ESR. COUT_min. = 298 µF During the load release time, the voltage cross the inductor is approximately - VOUT. This causes a down-slope or falling di/dt in the inductor. If the load dI/dt is not much faster than the dI/dt of the inductor, then the inductor current will tend to track the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor; therefore a smaller capacitance can be used. Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or ESR loop instability. Double-pulsing occurs due to switching noise seen at the FB input or because the FB ripple voltage is too low. This causes the FB comparator to trigger prematurely after the 250 ns minimum off-time has expired. In extreme cases the noise can cause three or more successive on-times. Double-pulsing will result in higher ripple voltage at the output, but in most applications it will not affect operation. This form of instability can usually be avoided by providing the FB pin with a smooth, clean ripple signal that is at least 10 mVp-p, which may dictate the need to increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout as discussed in the Layout Guidelines section. Another way to eliminate doubling-pulsing is to add a small (~10 pF) capacitor across the upper feedback resistor, as shown in figure 13. This capacitor should be left unpopulated until it can be confirmed that double-pulsing exists. Adding the CTOP capacitor will couple more ripple into FB to help eliminate the problem. An optional connection on the PCB should be available for this capacitor. CTOP The following can be used to calculate the needed capacitance for a given dILOAD/dt. Peak inductor current is shown by the next equation. ILPK = Imax. + 1/2 x IRIPPLEmax. VOUT ILPK = 6 + 1/2 x 3.7 = 7.9 A Rate of change of load current = dILOAD dt R1 To FB pin R2 Imax. = maximum load release = 6 A COUT = ILPK x I I L x LPK - max. x dt VOUT dlLOAD 2 (VPK - VOUT) Example 2A dlLOAD = 1 µs dt This would cause the output current to move from 6 A to 0 A in 3 μs, giving the minimum output capacitance requirement shown in the following equation. Fig. 13 - Capacitor Coupling to FB PIN ESR loop instability is caused by insufficient ESR. The details of this stability issue are discussed in the ESR Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. Ringing for more than one cycle after the initial step is an indication that the ESR should be increased. 7.9 6 x 1 µs 1.5 2 2 (1.6 - 1.5) 1.5 µH x COUT = 7.9 x COUT = 194 µF Note that COUT is much smaller in this example, 194 μF S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 18 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix ESR Requirements A minimum ESR is required for two reasons. One reason is to generate enough output ripple voltage to provide 10 mVp-p at the FB pin (after the resistor divider) to avoid double-pulsing. The second reason is to prevent instability due to insufficient ESR. The on-time control regulates the valley of the output ripple voltage. This ripple voltage is the sum of the two voltages. One is the ripple generated by the ESR, the other is the ripple due to capacitive charging and discharging during the switching cycle. For most applications the minimum ESR ripple voltage is dominated by the output capacitors, typically SP or POSCAP devices. For stability the ESR zero of the output capacitor should be lower than approximately one-third the switching frequency. The formula for minimum ESR is shown by the following equation. ESRmin. = 3 2 x π x COUT x fSW Using Ceramic Output Capacitors Fig. 15 - FB Voltage by CL Voltage It is shown by the following equation. VFBCL = VCL x (R1//R2) x S x CC (R1//R2) x S x CC + 1 It is recommended that R2 be set to 1k. Figure 16 shows the magnitude of the ripple contribution due to the output voltage ripple at the FB pin. When the system is using high ESR value capacitors, the feedback voltage ripple lags the phase node voltage by 90°. Therefore, the converter is easily stabilized. When the system is using ceramic output capacitors, the ESR value is normally too small to meet the above ESR criteria. As a result, the feedback voltage ripple is 180° from the phase node and behaves in an unstable manner. In this application it is necessary to add a small virtual ESR network that is composed of two capacitors and one resistor, as shown in figure 14. Fig. 16 - FB Voltage by Output Voltage It is shown by the following equation. VFBΔVOUT = ΔVOUT x R1// R2 1 + R2 S x CC The purpose of this network is to couple the inductor current ripple information into the feedback voltage such that the feedback voltage has 90° phase lag to the switching node similar to the case of using standard high ESR capacitors. This is illustrated in figure 17. Fig. 14 - Virtual ESR Ramp Current The ripple voltage at FB is a superposition of two voltage sources: the voltage across CL and output ripple voltage. They are defined in the following equations. VCL = IL x DCR (s x L/DCR + 1) S x RL x CL + 1 ΔVOUT = ΔIL 8C x fSW Figure 15 shows the magnitude of the ripple contribution due to CL at the FB pin. Fig. 17 - FB Voltage in Phasor Diagram S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 19 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com The magnitude of the feedback ripple voltage, which is dominated by the contribution from CL, is controlled by the value of R1, R2 and CC. If the corner frequency of (R1//R2) x CC is too high, the ripple magnitude at the FB pin will be smaller, which can lead to double-pulsing. Conversely, if the corner frequency of (R1//R2) x CC is too low, the ripple magnitude at FB pin will be higher. Since the SiC403A/B regulates to the valley of the ripple voltage at the FB pin, a high ripple magnitude is undesirable as it significantly impacts the output voltage regulation. As a result, it is desirable to select a corner frequency for (R1//R2) x CC to achieve enough, but not excessive, ripple magnitude and phase margin. The component values for R1, R2, and CC should be calculated using the following procedure. Select CL (typical 10 nF) and RL to match with L and DCR time constant using the following equation. RL = L DCR x CL Select CC by using the following equation. CC ≈ 1 3 x R1//R2 2 x π x fSW The resistor values (R1 and R2) in the voltage divider circuit set the VOUT for the switcher. The typical value for CC is from 10 pF to 1 nF. Dropout Performance The output voltage adjustment range for continuous conduction operation is limited by the fixed 250 ns (typical) minimum off-time of the one-shot. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. Vishay Siliconix trip. The best way to minimize this effect is to minimize the output ripple. The use of 1 % feedback resistors may result in up to 1 % error. If tighter DC accuracy is required, 0.1 % resistors should be used. The output inductor value may change with current. This will change the output ripple and therefore will have a minor effect on the DC output voltage. The output ESR also affects the output ripple and thus has a minor effect on the DC output voltage. Switching Frequency Variation The switching frequency varies with load current as a result of the power losses in the MOSFETs and DCR of the inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. An adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from VIN as losses increase). The on-time is essentially constant for a given VOUT/VIN combination, to offset the losses the offtime will tend to reduce slightly as load increases. The net effect is that switching frequency increases slightly with increasing load. HIGH OUTPUT VOLTAGE OPERATION For the SiC40X family the recommended maximum output voltage of no more than 75 % of VIN. For applications where an output voltage greater than 5 V is required a resistive network should be used to step down the output voltage in order to provide the VOUT_PIN with 4.5 V. The duty-factor limitation is shown by the next equation. DUTY = tON(min.) R1 = R2 (VOUT - VOUT_PIN) VOUT_PIN tON(min.) x tOFF(max.) The inductor resistance and MOSFET on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. System DC Accuracy (VOUT Controller) For example, if an output voltage of VOUT = 8.5 V is required, setting R2 = 10 k and VOUT_PIN = 4.5 V results in R1 = 8870 The switching frequency will also need recalculating using a VOUT_PIN magnitude of 4.5 V. Three factors affect VOUT accuracy: the trip point of the FB error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed so that under static conditions it trips when the feedback pin is 600 mV, 1 %. The on-time pulse from the SiC403A/B in the design example is calculated to give a pseudo-fixed frequency of 300 kHz. Some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because adaptive on-time converters regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the output ripple is 50 mV with VIN = 6 V, then the measured DC output will be 25 mV above the comparator trip point. If the ripple increases to 80 mV with VIN = 28 V, then the measured DC output will be 40 mV above the comparator S14-2048-Rev. B, 13-Oct-14 fsw = VOUT_PIN tON x VIN LX SiC40X Vout R1 VOUT_PIN Cout R2 Fig. 18 - Resistor Divider Network allows 4.5 V at the VOUT Pin Document Number: 62768 20 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix LAYOUT CONSIDERATIONS The SiC40x family of footprint compatible 15 A, 10 A, and 6 A products offers the designer a scalable buck regulator solution. If the below layout recommendations are followed, the same layout can be used to cover a wide range of output currents and voltages without any changes to the board design and only minor changes to the component values in the schematic. 3. It is advisable to use ceramic capacitors at the output to reduce impedance. Place these as close to the IC PGND and output voltage node as design will allow. Place a small 10 nF/100 nF ceramic capacitor closest to the IC and inductor loop. 4. The loop between LX, VOUT and the IC GND should be as compact as possible. This will lower series resistance and also make the current loop smaller enabling the high frequency response of the output capacitors to take effect. The reference design has a majority of the components placed on the top layer. This allows for easy assembly and straightforward layout. 5. The output impedance should be small when high current is required; use high current traces, multiple layers can be used with many vias. Figure 19 outlines the pointers for the layout considerations and the explanations follow. 6. Use many vias when multiple layers are involved. This will have the effect of lowering the resistance between layers and reducing the via inductance of the PCB nets. 9 2 VIN 7. If a voltage injection network is needed then place it near to the inductor LX node. 1 7 SiC40X 0V LX VOUT 8. PGND can be used on internal layers if the resistance of the PCB is to be small; this will also help remove heat. Use extra vias if needed but be mindful to allow a path between the vias. 6 3 10 4 11 9. A quiet plane should be employed for the AGND, this is placed under the small signal passives. This can be placed on multiple layers if needed for heat removal. This should be connected to the PGND plane near to the input GND at one connection only of at least 1 mm width. 5 8 Fig. 19 - Reference Design Pointers 1. Place input ceramic capacitors close to the voltage input pins with a small 10 nF/100 nF placed as close as the design rules will allow. This will help reduce the size of the input high frequency current loop and consequently reduce the high frequency ripple noise seen at the input and the LX node. 2. Place the setup and control passive devices logically around the IC with the intention of placing a quiet ground plane beneath them on a secondary layer. S14-2048-Rev. B, 13-Oct-14 10. The LX copper can also be used on multiple layers, use a number of vias. 11. The copper area beneath the inductor has been removed (on all layers) in this design to reduce the inductive coupling that occurs between the inductor and the GND trace. No other voltage planes should be placed under this area. Document Number: 62768 21 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix PCB LAYOUT Fig. 20 - Top Layer Fig. 22 - Inner Layer 2 Fig. 21 - Inner Layer 1 Fig. 23 - Bottom Layer S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 22 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix SCHEMATIC Note • If OUT voltage setting 5 VDC, please change R10 and R11 value based on “High Output Voltage Operation” formula calculation. S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 23 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix BILL OF MATERIALS (VIN = 12 V, VOUT = 1.5 V, Fsw = 500 kHz) ITEM QTY REFERENCE PCB FOOTPRINT VALUE VOLTAGE PART NUMBER MANUFACTURER 1 3 C1, C2, C3 1206 Omit 35 V C3216X5R1V226M160AC TDK 2 1 C4 1206 22 μF 35 V C3216X5R1V226M160AC TDK 3 3 C5, C9, C12 0402 10 nF 50 V GRM155R71H103KA88D Murata 4 1 C6 0402 2.2 μF 10 V C0402C225M8PACTU Kemet 5 2 C7, C10 0402 1 nF 50 V GRM155R71H102KA01D Murata 6 1 C8 0402 100 nF 35 V CGA2B3X7R1V104K050BB Vishay 7 2 C13, C14 1206 47 μF 10 V GRM31CR61A476ME15L Murata 8 6 C15, C16, C17 C18, C19, C20 1206 Omit 10 V GRM31CR61A476ME15L Murate 9 2 C21, C22 7343 Omit - - - 10 4 P1, P3, P9, P10 Banana Jack - - 575-4K-ND Keystone 11 5 P2, P4, P5, P7, P8 Header-2 - - 826926-2 AMP (TE) 12 1 P6 Header-3 - - HTSW-103-08-T-S Samtec 13 1 L1 IHLP3232 2.2 μH - IHLP3232DZER2R2 Vishay 14 1 R1 0402 249K - CRCW0402249KFKED Vishay 15 1 R2 0402 100K - CRCW0402100KFKED Vishay 16 1 R3 0402 169K - CRCW0402169KFKED Vishay 17 1 R4 0402 30K - CRCW040230K0FKED Vishay 18 1 R5 0402 5K11 - CRCW04025K11FKED Vishay 19 1 R6 0402 76K8 - CRCW040276K8FKED Vishay 20 1 R7 0402 10R - CRCW040210R0FKEA Vishay 21 1 R8 0402 10K - CRCW040210K0FKED Vishay 22 1 R9 0805 Omit - - Vishay 23 1 R10 0402 0R - CRCW04020000Z0ED Vishay 24 1 R11 0402 Omit - - Vishay 25 1 R12 0402 1K54 - CRCW04021K54FKED Vishay 26 1 R13 0402 1K - CRCW0402249KFKED Vishay 27 1 R14 0402 10R - CRCW040210R0FKEA Vishay 28 1 R15 0402 10K - CRCW040210K0FKED Vishay 29 1 U1 MLP55-33 SIC403 - - - S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 24 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC403A, SiC403BCD www.vishay.com Vishay Siliconix PACKAGE DIMENSIONS Top View DIM. MILLIMETERS Side View INCHES MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.80 0.027 0.029 0.031 A1 0.00 - 0.05 0.00 - 0.002 A2 b 0.20 ref. 0.20 0.25 NOTE 8 0.008 ref. 0.30 0.078 0.098 0.110 4 Bottom View DIM. MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. D2-1 3.43 3.48 3.53 0.135 0.137 0.139 D2-2 1.00 1.05 1.10 0.039 0.041 0.043 D2-3 1.00 1.05 1.10 0.039 0.041 0.043 D2-4 1.92 1.97 2.02 0.075 0.077 0.079 5.00 BSC 0.196 BSC D2-5 e 0.50 BSC 0.019 BSC E2-1 3.43 3.48 3.53 0.135 0.137 0.139 E 5.00 BSC 0.196 BSC E2-2 1.61 1.66 1.71 0.063 0.065 0.067 E2-3 1.43 1.48 1.53 0.056 0.058 0.060 D L N 0.35 0.40 0.45 0.013 0.015 0.017 32 32 3 Nd 8 8 3 Ne 8 8 3 E2-4 0.36 0.45 0.014 0.018 Notes 1. Use millimeters as the primary measurement. 2. Dimensioning and tolerances conform to ASME Y1 4.5M - 1994. 3. N is the number of terminals Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4. Dimensions applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max. 0.08 mm. 8. Applied only for terminals. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62768. S14-2048-Rev. B, 13-Oct-14 Document Number: 62768 25 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix PowerPAK® MLP55-32L CASE OUTLINE 0.08 C A A1 D A2 25 1 4 (5 mm x 5 mm) Pin #1 identification R0.200 E2 - 3 0.10 E 32L T/SLP D2 - 2 32 24 E2 - 1 CAB e 0.10 CB D2 - 1 0.360 8 17 B b 16 L C 0.36 Top View (Nd-1) Xe Ref. 0.10 CA A E2 - 2 2x 0.45 5 6 Pin 1 dot by marking 2x Side View D2 - 3 D2 - 4 (Nd-1) Xe Ref. D4 9 Bottom View MILLIMETERS INCHES DIM MIN. NOM. MAX. MIN. NOM. A 0.80 0.85 0.90 0.031 0.033 0.035 A1(8) 0.00 - 0.05 0.000 - 0.002 0.30 0.078 A2 b(4) 0.20 REF. 0.20 0.25 0.008 REF. 0.098 D 5.00 BSC 0.196 BSC e 0.50 BSC 0.019 BSC E 5.00 BSC L 0.35 0.40 MAX. 0.011 0.196 BSC 0.45 0.013 0.015 N(3) 32 32 Nd(3) 8 8 Ne(3) 8 0.017 8 D2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 D2 - 2 1.00 1.05 1.10 0.039 0.041 0.043 D2 - 3 1.00 1.05 1.10 0.039 0.041 0.043 D2 - 4 1.92 1.97 2.02 0.075 0.077 0.079 E2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 E2 - 2 1.61 1.66 1.71 0.063 0.065 0.067 E2 - 3 1.43 1.48 1.53 0.056 0.058 0.060 ECN: T-08957-Rev. A, 29-Dec-08 DWG: 5983 Notes 1. Use millimeters as the primary measurement. 2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994. 3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction. 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip. 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. 7. Package warpage max. 0.08 mm. 8. Applied only for terminals. Document Number: 64714 Revision: 29-Dec-08 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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