SEMTECH SC401B

SC401B
15A Integrated FET Regulator
with Programmable LDO
POWER MANAGEMENT
Features





Description
Power System
Input voltage — 3V to 17V
Bias voltage — 3V to 5.5V LDO or external
Up to 96% peak efficiency
Integrated bootstrap switch
Programmable LDO output — 200mA
Reference tolerance — 1% TJ= -40 to +125 °C
Programmable soft-start time
Logic Input/Output Control
Independent EN controls for LDO and switcher
Programmable VIN UVLO threshold
Power good output
Selectable PSAVE or FCM mode
Protection
Over-voltage and under-voltage
TC compensated RDS(ON) sensed current limit
Thermal Shutdown
Output Capacitor Types
High ESR — SP, POSCAP, OSCON
Ceramic capacitors
Package
Lead-free package — 5x5mm, 32-Pin MLPQ
RoHS/WEEE compliant and Halogen free
The SC401B is a stand-alone synchronous EcoSpeedTM buck
power supply which incorporates Semtech’s advanced
patented adaptive on-time control architecture. This provides excellent light-load efficiency and fast transient
response. It features integrated power MOSFETs, a bootstrap switch, and a programmable LDO in a 5x5mm
package. The device is highly efficient and uses minimal
PCB area. The SC401B has the same package and pin configuration as the entire SC40xB series for compatibility.
•
•
•
•
•
•
•
•
•
•
•
The SC401B supports using standard capacitor types such
as electrolytic or specialty polymer, in addition to ceramic,
at switching frequencies up to 1MHz. The programmable
frequency, synchronous operation, and selectable power
save provide high efficiency operation over a wide load
range.
•
•
•
Additional features include a programmable soft-start,
programmable cycle-by-cycle over-current limit protection, under-voltage and over-voltage protection, soft
shutdown, and selectable power save. The device also
provides separate enable inputs for the PWM controller
and LDO as well as a power good output for the PWM
controller.
•
•
•
•
Applications
The wide input range and programmable frequency make
the device extremely flexible and easy to use in a broad
range of applications.
Networking and telecommunication equipment
 Printers, DSL, and STB applications
 Embedded systems and power supply modules
 Point of load power supplies

Typical Application Circuit
ENABLE/PSAVE
ENABLE LDO
RTON
1µF
ILIM
ENL
LXS
TON
PGOOD
VOUT
10Ω
VEXT/LDO
EN/PSV
SC401B
VDD
L1
VOUT
CSOFT
BST
VIN
VIN
Rev. 2.1
PGOOD
LX
SS
CIN
RILIM
RFB1
LXBST
AGND
PGND
COUT
+
FB
CBST
© 2011 Semtech Corporation
RFB2
SC401B
4
FBL
5
VIN
6
SS
7
BST
8
LXS
ILIM
PGOOD
LX
AGND
EN/PSV
TON
26
25
AGND
PAD 1
LX
PAD 3
VIN
PAD 2
VIN
9
10
11
12
13
14
15
16
PGND
AGND
27
PGND
3
28
DL
VDD
29
Top View
LXBST
2
30
DH
VOUT
31
VIN
1
32
Ordering Information
VIN
FB
ENL
Pin Configuration
24
LX
23
LX
22
PGND
21
PGND
20
PGND
19
PGND
18
PGND
17
PGND
Device
Package
SC401BMLTRT(1)(2)
MLPQ-32 5X5
SC401BEVB
Evaluation Board
Notes:
1) Available in tape and reel only. A reel contains 3000 devices.
2) Lead-free, Halogen free, and RoHS/WEEE compliant
SC401B
MLPQ-32; 5x5, 32 LEAD
Marking Information
SC401B
yyww
xxxxxx
xxxxxx
yyww = Date Code
xxxxxx = Semtech Lot Number
xxxxxx = Semtech Lot Number
SC401B
Absolute Maximum Ratings
Recommended Operating Conditions
LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +20
Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 17
LX to PGND (V) (transient — 100ns max.) . . . . . . . -2 to +20
VDD to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5
VIN to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +20
VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 to 5.5
VIN to VDD (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4
Thermal Information
EN/PSV, PGOOD, ILIM, to GND (V). . . . . . -0.3 to +(VDD + 0.3)
SS, VOUT, FB, FBL, to GND (V) . . . . . . . . . . -0.3 to +(VDD+0.3)
Storage Temperature (°C). . . . . . . . . . . . . . . . . . . . . -60 to +150
VDD to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6
Maximum Junction Temperature (°C). . . . . . . . . . . . . . . 150
TON to PGND (V). . . . . . . . . . . . . . . . . . . . . . -0.3 to +(VDD - 1.5)
Operating Junction Temperature (°C). . . . . . -40 to +125
ENL (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN
Thermal resistance, junction to ambient (2) (°C/W)
DH, BST to LX (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
High-side MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DH, BST to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +25
Low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DL to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
PWM controller and LDO thermal resistance . . . . . . 50
AGND to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3
Peak IR Reflow Temperature (°C). . . . . . . . . . . . . . . . . . . . 260
ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless specified: VIN =12V, TA = +25°C for Typ, -40 to +85 °C for Min and Max, TJ < 125°C, VDD = +5V, Typical Application Circuit
Parameter
Conditions
Min
VIN > VDD
Typ
Max
Units
3
17
V
3
5.5
V
Input Supplies
Input Supply Voltage
VDD Voltage
Sensed at ENL pin, rising edge
2.40
2.60
2.95
Sensed at ENL pin, falling edge
2.23
2.40
2.57
VIN UVLO Threshold(1)
VIN UVLO Hysteresis
V
EN/PSV = High
0.25
V
Measured at VDD pin, rising edge
2.5
3.0
Measured at VDD pin, falling edge
2.4
2.9
VDD UVLO Threshold
V
VDD UVLO Hysteresis
VIN Supply Current
0.2
ENL , EN/PSV = 0V, VIN = 20V
10
Standby mode; ENL=VDD, EN/PSV = 0V
130
V
20
μA
SC401B
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
ENL , EN/PSV = 0V, no external 5V VDD
3
7
ENL , EN/PSV = 0V, external 5V VDD supply
190
300
EN/PSV = VDD (PSAVE), No load, VFB > 600mV
0.7
VDD = 5V, fSW = 250kHz, EN/PSV = floating , no load(2)
9
VDD = 3V, fSW = 250kHz, EN/PSV = floating , no load(2
5.5
Units
Input Supplies (continued)
μA
VDD Supply Current
FB On-Time Threshold
Frequency Range
mA
Static VIN and load, TJ = 0 to +125 °C
0.595
0.6
0.605
V
Static VIN and load, TJ = -40 to +125 °C
0.594
0.6
0.606
V
1000
kHz
Continuous mode operation
Bootstrap Switch Resistance
10
Ω
Timing
On-Time
Continuous mode operation,
VIN = 12V, VOUT = 5V, fSW= 300kHz, RTON = 133kΩ
999
Minimum On-Time (2)
1110
1220
80
VDD = 5V
250
VDD = 3.3V
370
ns
ns
Minimum Off-Time (2)
ns
Soft-Start
Soft-Start Current
Soft-Start Voltage(2)
When VOUT reaches regulation
3.0
µA
1.5
V
500
kΩ
Analog Inputs/Outputs
VOUT Input Resistance
Current Sense
Zero-Crossing Detector Threshold
LX - PGND
-3
0
+3
mV
Power Good
Power Good Threshold
Start-Up Delay Time
(between PWM enable and PGOOD high)
Upper limit, VFB > internal 600mV reference
+20
%
Lower limit, VFB < internal 600mV reference
-10
%
VDD = 5V, CSS = 10nF
12
VDD = 3.3V, CSS = 10nF
7
ms
SC401B
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
Power Good (continued)
Power Good start-up Delay Threshold on SS pin
SS voltage when PGOOD goes high
Fault (noise immunity) Delay Time(2)
64
%VDD
5
µs
Leakage
1
Power Good On-Resistance
10
µA
Ω
Fault Protection
Valley Current Limit (3)
VDD = 5V, RILIM = 7150 , TJ = 0 to +125 °C
13.5
VDD = 3.3V, RILIM = 7150
ILIM Source Current
ILIM Comparator Offset
With respect to AGND
-10
15
16.5
A
13.5
A
10
μA
0
+10
mV
Output Under-Voltage Fault
VFB with respect to internal 600mV reference,
8 consecutive clocks
-25
%
Smart Power Save Protection Threshold (2)
VFB with respect to internal 600mV reference
+10
%
Over-Voltage Protection Threshold
VFB with respect to internal 600mV reference
+20
%
5
μs
150
°C
Over-Voltage Fault Delay(2)
Over-Temperature Shutdown(2)
10°C hysteresis
Logic Inputs/Outputs
Logic Input High Voltage
ENL
Logic Input Low Voltage
ENL
1.0
V
0.4
V
2.2
5
V
EN/PSV Input for Forced Continuous Operation (2)
1
2
V
EN/PSV Input for Disabling Switcher
0
0.4
V
-10
+10
μA
18
μA
+1
μA
EN/PSV Input for PSAVE Operation (2)
EN/PSV Input Bias Current
ENL Input Bias Current
FBL, FB Input Bias Current
VDD = 5V
EN/PSV= VDD or AGND
ENL = VIN = 20V
FBL, FB = VDD or AGND
10
-1
SC401B
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
VLDO load = 5mA
0.728
0.75
0.773
V
Linear Regulator (LDO)
FBL Accuracy
LDO Current Limit
Short-circuit protection, VIN = 12V, VDD < 0.75V
65
Start-up and foldback, VIN = 12V,
0.75 < VDD < 90% of final VDD value
115
Operating current limit, VIN = 12V,
VDD > 90% of final VDD value
135
mA
200
VLDO to VOUT Switch-over Threshold (4)
-130
+130
mV
VLDO to VOUT Non-switch-over Threshold (4)
-500
+500
mV
VLDO to VOUT Switch-over Resistance
LDO Drop Out Voltage (5)
VOUT = +5V
2
Ω
From VIN to VDD, VDD = +5V, IVLDO = 100mA
1.2
V
Notes:
(1) VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
(2) Typical value measured on standard evaluation board.
(3) SC401B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout.
(4) The switch-over threshold is the maximum voltage differential between the VDD and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures
that VLDO will not switch-over to VOUT.
(5) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point.
SC401B
Detailed Application Circuit-1
Internal LDO Used as Bias
ENABLE/PSAVE
PGOOD
RILIM
ENABLE LDO
7.68KΩ
1µF
1µF
3.3nF
VIN
RLDO2
75KΩ
PAD 2
RBST
3.3 Ω
VIN
+12V
CBST
1µF
SC401B
LX
LX
PGND
PGND
PGND
PGND
PGND
PGND
VIN
VIN
DH
LXBST
DL
PGND
PGND
RLDO1
422KΩ
FB
VOUT
VDD
AGND
FBL
VIN
SS
BST
VIN
1
2
3
4
5
6
7
8
AGND
LX
24
23
22
21
20
19
18
17
PAD 3
9
10
11
12
13
14
15
16
PAD 1
ENL
TON
AGND
EN/PSV
LXS
ILIM
PGOOD
LX
32
31
30
29
28
27
26
25
RTON
130KΩ
CIN
2 x 10µF
(see note)
1.5V @ 15A, 300kHz
L1
1µH
CFF
100pF
COUT
2 x 220µF
7.5mΩ
RFB1
10KΩ
RFB2
6.65KΩ
+
VOUT
2.2µF
RGND
0
Key Components
Component
Value
Manufacturer
CIN (see note)
2 x 10µF/25V
Murata
GRM32DR71E106KA12L
www.murata.com
COUT
2 x 220µF/15mΩ
Sanyo
4TPE220MF
www.edc.sanyo.com
L1
1.0µH/3mΩ
Cyntec
Part Number
PIMB104T-1R0MS
Web
www.cyntec.com
NOTE: The quantity of 10µF input capacitors required varies with the application requirements.
SC401B
Detailed Application Circuit-2
External 3.3V - 5V Used as Bias
ENABLE/PSAVE
PGOOD
RILIM
7.68KΩ
1µF
3.3nF
VIN
1µF
PAD 2
RBST
3.3 Ω
VIN
+12V
CBST
1µF
SC401B
LX
LX
PGND
PGND
PGND
PGND
PGND
PGND
VIN
VIN
DH
LXBST
DL
PGND
PGND
10Ω
FB
VOUT
VDD
AGND
FBL
VIN
SS
BST
VIN
1
2
3
4
5
6
7
8
5V
AGND
LX
24
23
22
21
20
19
18
17
PAD 3
9
10
11
12
13
14
15
16
PAD 1
ENL
TON
AGND
EN/PSV
LXS
ILIM
PGOOD
LX
32
31
30
29
28
27
26
25
RTON
130KΩ
CIN
2 x 10µF
(see note)
1.5V @ 15A, 300kHz
L1
1µH
CFF
100pF
COUT
2 x 330µF
7.5mΩ
RFB1
10KΩ
+
VOUT
2.2µF
RGND
0
RFB2
6.65KΩ
Key Components
Component
Value
Manufacturer
Part Number
CIN (see note)
2 x 10µF/25V
Murata
GRM32DR71E106KA12L
www.murata.com
COUT
2 x 220µF/15mΩ
Sanyo
4TPE220MF
www.edc.sanyo.com
L1
1.0µH/3mΩ
Cyntec
PIMB104T-1R0MS
Web
www.cyntec.com
NOTE: The quantity of 10µF input capacitors required varies with the application requirements.
SC401B
Typical Characteristics
Characteristics in this section are based on using the Typical Application Circuit on page 8.
Efficiency/Power Loss — PSAVE vs. FCM
Efficiency/Power Loss vs. Load — PSAVE
VIN = 5V
95
Efficiency
90
70
2.0
Efficiency (%)
PLOSS
PLoss (W)
Efficiency (%)
3.0
75
VIN = 17V
65
VIN = 12V
60
1.0
0.0
2
3
4
5
6
7
80
0.1450
75
0.1125
70
0.0800
65
0.0475
FCM minus PSM
8
9
10
11
12
13
14
-0.0175
50
15
-0.0500
0
IOUT (A)
1
95
100
4.0
VIN = 17V
75
PLOSS
VIN = 17V
2.0
Efficiency (%)
3.0
65
VIN = 12V
1.0
8
9
10
11
12
13
14
15
0.3000
0.2350
FCM
0.2025
80
0.1700
75
0.1375
70
0.1050
65
0.0725
0.0400
FCM minus PSM
55
50
0.0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.0075
50
15
-0.0250
0
IOUT (A)
1
2
VIN = 12V
95
5.0
100
VIN = 5V
4.0
VIN = 17V
85
3.0
75
PLOSS
VIN = 17V
2.0
60
1.0
VIN = 5V
55
0.0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8
IOUT (A)
0.30
0.25
0.20
5V Bias
0.15
80
0.10
75
0.05
70
0.00
3.3V minus 5V
-0.05
60
-0.10
55
50
1
7
3.3V Bias
65
VIN = 12V
0
Efficiency (%)
80
65
6
90
85
70
5
VOUT = 1.5V, VIN = 12V
95
Efficiency
90
4
Efficiency/Power Loss — PSAVE
VDD = 5V, VOUT = 1.5V
PLOSS (W)
100
3
IOUT (A)
Efficiency/Power Loss vs. Load — FCM
Efficiency (%)
7
0.2675
60
VIN = 5V
55
6
90
Power Loss (W)
80
60
5
PSAVE
85
70
4
VDD = 5V, VOUT = 1.5V, VIN = 12V
95
Efficiency
85
Efficiency (%)
5.0
VIN = 5V
90
3
Efficiency/Power Loss — PSAVE vs. FCM
Efficiency/Power Loss vs. Load — PSAVE
VIN = 12V
2
IOUT (A)
VDD = 5V, VOUT = 1.5V
100
0.0150
55
50
1
0.1775
60
VIN = 5V
55
0
0.2100
FCM
85
85
80
0.2425
PSAVE
90
4.0
VIN = 17V
0.2750
PLOSS (W)
95
100
5.0
VIN = 12V
9
10
11
12
13
14
15
PLOSS (W)
100
VDD = 3.3V, VOUT = 1.5V, VIN = 12V
PLOSS (W)
VDD = 3.3V, VOUT = 1.5V
50
-0.15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IOUT (A)
SC401B
Typical Characteristics (continued)
Characteristics in this section are based on using the Typical Application Circuit on page 8.
Load Regulation — FCM
Load Regulation — FCM
VDD = 5V, VOUT = 1.5V
1.535
1.535
1.530
1.530
1.525
1.525
Vout (V)
VIN = 12V
Vout (V)
VDD = 3.3V, VOUT = 1.5V
1.520
VIN = 5V
1.515
1.515
1.510
1.510
1.505
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VIN = 12V
1.520
VIN = 5V
1.505
15
0
IOUT (A)
1
2
3
6
7
VDD = 5V, VOUT = 1.5V
1.535
9
10
11
12
13
14
15
13
14
15
VDD = 3.3V, VOUT = 1.5V
1.530
1.525
1.525
Vout (V)
VIN = 12V
1.520
VIN = 5V
1.515
VIN = 12V
1.520
VIN = 5V
1.515
1.510
1.510
1.505
1.505
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
IOUT (A)
7
8
9
10
11
12
IOUT (A)
Switching Frequency — PSAVE Mode vs. FCM
350
8
Load Regulation — PSAVE
1.530
Vout (V)
5
IOUT (A)
Load Regulation — PSAVE
1.535
4
Switching Frequency — PSAVE vs. FCM
VDD = 5V, VOUT = 1.5V, VIN = 12V
350
300
VDD = 3.3V, VOUT = 1.5V, VIN = 12V
300
250
Switching Frequency (kHz)
Switching Frequency (kHz)
FCM
200
PSAVE
150
100
50
250
200
150
100
50
0
0
1
2
3
4
5
6
7
8
IOUT (A)
9
10
11
12
13
14
15
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IOUT (A)
10
SC401B
Typical Characteristics (continued)
Characteristics in this section are based on using the Typical Application Circuit on page 8.
Load Regulation vs. Temperature — FCM
Load Regulation vs. Temperature — FCM
VDD = 5V, VOUT = 1.5V
1.535
1.535
1.530
1.530
1.525
VIN = 12V TA = 25°C
VIN = 12V TA = -40°C
Vout (V)
1.525
1.520
VIN = 12V TA = 85°C
VIN = 5V TA = 25°C
1.515
VIN = 12V TA = -40°C
1.520
VIN = 12V TA = 85°C
1.515
VIN = 5V TA = 25°C
VIN = 5V TA = -40°C
VIN = 5V TA = 85°C
VIN = 5V TA = -40°C
1.510
1.510
1.505
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VIN = 5V TA = 85°C
1.505
15
0
1
2
3
4
5
6
7
IOUT (A)
11
12
13
14
15
1.535
1.530
1.525
VIN = 12V TA = 25°C
VIN = 12V TA = -40°C
Vout (V)
1.525
Vout (V)
10
VDD = 3.3V, VOUT = 1.5V
1.530
1.520
VIN = 5V TA = 85°C
VIN = 12V TA = 85°C
VIN = 5V TA = 25°C
1.515
VIN = 12V TA = -40°C
VIN = 12V TA = 25°C
1.520
VIN = 12V TA = 85°C
1.515
VIN = 5V TA = 25°C
VIN = 5V TA = -40°C
VIN = 5V TA = -40°C
1.510
1.510
1.505
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VIN = 5V TA = 85°C
1.505
0
1
2
3
4
5
IOUT (A)
Efficiency Variation with VOUT— PSAVE
VOUT = 2.5V
100
VOUT = 3.3V
8
9
10
11
12
VOUT = 1.5V, VIN = 12V
VOUT = 1.5V
Efficiency (%)
85
0.07
LDO
Bias
80
0.06
75
0.05
70
0.04
65
0.03
60
80
0.02
LDO minus External
55
2
3
4
5
6
7
8
IOUT (A)
15
0.08
85
VOUT = 1V
1
14
0.09
External
Bias
90
0
13
0.10
95
95
90
7
Efficiency/Power Loss — PSAVE
100
VOUT = 5V
6
IOUT (A)
VDD = 5V, VIN = 12V, L = 2.2uH (4.6m Ω) for VOUT = 2.5V, 3.3V and 5V
Efficiency (%)
9
Load Regulation vs. Temperature — PSAVE
VDD = 5V, VOUT = 1.5V
1.535
8
IOUT (A)
Load Regulation vs. Temperature — PSAVE
75
VIN = 12V TA = 25°C
9
10
11
12
13
14
15
50
0.000
PLOSS (W)
Vout (V)
VDD = 3.3V, VOUT = 1.5V
0.001
0.010
0.100
1.000
10.000
0.01
0.00
100.000
IOUT (A)
11
SC401B
Typical Characteristics (continued)
Characteristics in this section are based on using the Typical Application Circuit on page 8.
Start-up — EN/PSV
Shutdown — EN/PSV
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 0A
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 5A
(5V/div)
(500mV/div)
(5V/div)
2.2ms
(500mV/div)
(1V/div)
(2V/div)
(5V/div)
(5V/div)
Time (1m������
s�����
/div)
Time (20�����
s�����
/div)
Start-up (Pre-Bias) — EN/PSV
Power Save Mode
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 0A
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 0A
(5V/div)
(500mV/div)
(50mV/div)
(2V/div)
(5V/div)
(5V/div)
Time (1 m������
s�����
/div)
Time (10m������
s�����
/div)
Over Current Protection — Under-Voltage Protection
Forced Continuous Mode
VDD = 5V, VIN = 12V, VOUT = 1.5V
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 15A
(5V/div)
(500mV/div)
20.9A
(5A/div)
(50mV/div)
15.5A
(5V/div)
(5V/div)
Time (100�����
s�����
/div)
Time (5�����
s�����
/div)
12
SC401B
Typical Characteristics (continued)
Characteristics in this section are based on using the Typical Application Circuit on page 8.
Rising Edge (Deadtime) — LX, DL
Falling Edge (Deadtime) — LX, DL
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 15A
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 15A
(1V/div)
(1V/div)
(1V/div)
13ns
(1V/div)
16ns
Time (10n������
s�����
/div)
Time (10n������
s�����
/div)
Transient Response — PSAVE Load Rising
Transient Response — PSAVE Load Falling
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 1A to 11A, di/dt = 1A/μ�s
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 11A to 1A, di/dt = 1A/μ�s
(50mV/div)
(50mV/div)
(5A/div)
(5A/div)
(5V/div)
(5V/div)
Time (10�����
s�����
/div)
Time (10�����
s�����
/div)
Transient Response — FCM
Over Temperature Shutdown — 159ºC
VIN = 12V, VOUT = 1.5V, IOUT = 0A, LDO mode
VDD = 5V, VIN = 12V, VOUT = 1.5V, IOUT = 5A to 15A, di/dt = 1A/μ�s
(2V/div)
(50mV/div)
70mV
(5A/div)
(5V/div)
(10V/div)
Time (20�����
s�����
/div)
Time (500�����
s�����
/div)
13
SC401B
Pin Descriptions
Pin #
Pin Name
Pin Function
1
FB
2
VOUT
Switcher output voltage sense pin — also the input to the internal switch-over between VOUT and VLDO.
The voltage at this pin must be less than or equal to the voltage at the VDD pin.
3
VDD
Bias supply for the IC — when using the internal LDO as a bias power supply, VDD is the LDO output. When
using an external power supply as the bias for the IC, the LDO output should be disabled.
4, 30, PAD 1
AGND
5
FBL
Feedback input for the internal LDO — connect to an external resistor divider from VDD to AGND — used to
program the LDO output.
6, 9-11,
PAD 2
VIN
Input supply voltage
7
SS
The soft start ramp will be programmed by an internal current source charging a capacitor on this pin.
8
BST
Bootstrap pin — connect a capacitor of at least 100nF from BST to LX to develop the floating supply for the
high-side gate drive.
12
DH
High-side gate drive
13
LXBST
23-25, PAD 3
LX
Switching (phase) node
14
DL
Low-side gate drive
15-22
PGND
26
PGOOD
27
ILIM
Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LXS.
28
LXS
LX sense — connects to RILIM.
29
EN/PSV
31
TON
On-time programming input — set the on-time by connecting through a resistor to AGND
32
ENL
Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic signal for logic control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.
Feedback input for switching regulator used to program the output voltage — connect to an external resistor divider from VOUT to AGND.
Analog ground
LX Boost — connect to the BST capacitor.
Power ground
Open-drain power good indicator — high impedance indicates power is good. An external pull-up
resistor is required.
Enable/power save input for the switching regulator — connect to AGND to disable the switching regulator,
connect to VDD to operate with power save mode and float to operate in forced continuous mode.
14
SC401B
Block Diagram
PGOOD
EN/PSV
VIN
29
A
26
VDD
VDD
AGND
D
Control & Status
Reference
VDD
VIN
Bootstrap
Switch
DL
SS
FB
Gate Drive
Control
On-- time
Generator
1
FB Comparator
TON
VDD
DL
31
Zero Cross Detector
VOUT
2
Valley Current Limit
3
DH
B
LX
13
LXBST
28
LXS
C
PGND
27
ILIM
14
DL
Lo-side
MOSFET
A
VIN
Y
B
LDO
VLDO Switchover MUX
FBL
12
Bypass Comparator
VDD
VDD
BST
Hi-side
MOSFET
Soft Start
7
8
5
32
ENL
A = connected to pins 6, 9-11, PAD 2
B = connected to pins 23-25, PAD 3
C = connected to pins 15-22
D = connect to pins 4, 30, PAD 1
15
SC401B
Applications Information
Synchronous Buck Converter
Psuedo-fixed Frequency Adaptive On-time Control
The SC401B is a step down synchronous DC-DC buck
converter with integrated power MOSFETs and a 200mA
capable programmable LDO. The device is capable of 15A
operation at very high efficiency. A space saving 5x5 (mm)
32-pin package is used. The programmable operating
frequency of up to 1MHz enables optimizing the configuration for PCB area and efficiency.
The PWM control method used by the SC401B is pseudofixed frequency, adaptive on-time, as shown in Figure 1.
The ripple voltage generated at the output capacitor ESR
is used as a PWM ramp signal. This ripple is used to trigger
the on-time of the controller.
The buck controller uses a pseudo-fixed frequency adaptive on-time control. This control method allows fast transient response which permits the use of smaller output
capacitors.
In addition to the following information, the user can
click on the applicable link to go to the SC401B online
C-SIM design and simulation tool, which will lead the
user through the design process.
TON
VIN
VLX
CIN
Q1
VFB
FB Threshold
VLX
VOUT
L
Q2
ESR
+
FB
COUT
Input Voltage Requirements
The SC401B requires two input supplies for normal operation: VIN and VDD. VIN operates over a wide range from 3V
to 17V. VDD requires a 3V to 5.5V supply input that can be
an external source or the internal LDO configured to
supply 3V to 5.5V from VIN.
Power Up Sequence
When the SC401B uses an external power source at the
VDD pin, the switching regulator initiates the start up when
VIN, VDD and EN/PSV are above their respective thresholds.
When EN/PSV is at a logic high, VDD needs to be applied
after VIN rises. Also, it is recommended to use a 10Ω resistor
between an external power source and the VDD pin. To
start up by using the EN/PSV pin when both VDD and VIN
are above their respective thresholds, apply EN/PSV to
enable the start-up process. For SC401B in self-biased
mode, refer to the LDO section for a full description.
Shutdown
The SC401B can be shut down by pulling either VDD or
EN/PSV below its threshold. When using an external
power source, it is recommended that the VDD voltage
ramps down before the VIN voltage. When VDD is active
and EN/PSV at low logic, the output voltage discharges
through an internal FET.
Figure 1 — PWM Control Method, VOUT Ripple
The adaptive on-time is determined by an internal oneshot timer. When the one-shot is triggered by the output
ripple, the device sends a single on-time pulse to the highside MOSFET. The pulse period is determined by VOUT and
VIN; the period is proportional to output voltage and
inversely proportional to input voltage. With this adaptive
on-time arrangement, the device automatically anticipates the on-time needed to regulate VOUT for the present
VIN condition and at the selected frequency.
The advantages of adaptive on-time control are:
•
•
•
•
•
Predictable operating frequency compared to
other variable frequency methods
Reduced component count by eliminating the
error amplifier and compensation components
Reduced component count by removing the
need to sense and control inductor current
Fast transient response — the response time is
controlled by a fast comparator instead of a typically slow error amplifier.
Reduced output capacitance due to fast transient response
16
SC401B
Applications Information (continued)
One-Shot Timer and Operating Frequency
The one-shot timer operates as shown in Figure 2. The FB
Comparator output goes high when VFB is less than the
internal 600mV reference. This feeds into the gate drive
and turns on the high-side MOSFET, and also starts the
one-shot timer. The one-shot timer uses an internal comparator and a capacitor. One comparator input is connected to V OUT, the other input is connected to the
capacitor. When the on-time begins, the internal capacitor charges from zero volts through a current which is
proportional to VIN. When the capacitor voltage reaches
VOUT, the on-time is completed and the high-side MOSFET
turns off.
FB
VREF
FB Comparator
Gate
Drives
+
VOUT
VIN
DH
One-Shot
Timer
RTON
DL
Q1
VLX
Q2
ESR
COUT
+
FB
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN.
Under steady-state conditions, the switching frequency
can be determined from the on-time by the following
equation.
VOUT
TON u VIN
The SC401B uses an external resistor to set the on-time
which indirectly sets the frequency. The on-time can be
programmed to provide an operating frequency up to
1MHz using a resistor between the TON pin and ground.
The resistor value is selected by the following equation.
k
25pF u fSW
The constant, k, equals 1 when VDD is greater than 3.6V. If
VDD is less than 3.6V and VIN is greater than (VDD -1.75) x 10,
k is shown by the following equation.
k
VDD 1.75 u 10
VIN
VIN _ MIN
15PA
VOUT Voltage Selection
The switcher output voltage is regulated by comparing
VOUT as seen through a resistor divider at the FB pin to the
internal 600mV reference voltage, see Figure 3.
VOUT
To FB pin
R1
R2
Figure 3 — Output Voltage Selection
VOUT
L
Figure 2 — On-Time Generation
R TON
R TON _ MAX
VIN
On-time = K x RTON x (VOUT/VIN)
fSW
The maximum RTON value allowed is shown by the following equation.
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is offset by the output ripple according to the
following equation.
VOUT
§ R · §V
·
0.6 u ¨¨1 1 ¸¸ ¨ RIPPLE ¸
R
2
©
¹
2 ¹
©
When a large capacitor is placed in parallel with R1 (C TOP)
VOUT is shown by the following equation.
VOUT
§ R · §V
·
0.6 u ¨¨1 1 ¸¸ ¨ RIPPLE ¸ u
R
2
©
¹
2 ¹
©
1 (R1ZCTOP )2
§ R u R1
·
1 ¨¨ 2
ZCTOP ¸¸
R
R
1
© 2
¹
2
Enable and Power Save Inputs
The EN/PSV input is used to enable or disable the switching regulator. When EN/PSV is low (grounded), the switching regulator is off and in its lowest power state. When off,
the output of the switching regulator soft-discharges the
output into a 15Ω internal resistor via the VOUT pin. When
EN/PSV is allowed to float, the pin voltage will float to 33%
of the voltage at VDD. The switching regulator turns on
with power save disabled and all switching is in forced
continuous mode.
When EN/PSV is high (above 44% of the voltage at VDD),
the switching regulator turns on with power save enabled.
17
SC401B
Applications Information (continued)
The SC401B power save operation maintains a minimum
switching frequency of 25kHz, for applications with stringent audio requirements.
Forced Continuous Mode Operation
The SC401B operates the switcher in FCM (Forced
Continuous Mode) by floating the EN/PSV pin (see Figure
4). In this mode one of the power MOSFETs is always on,
with no intentional dead time other than to avoid crossconduction. This feature results in uniform frequency
across the full load range with the trade-off being poor
efficiency at light loads due to the high-frequency switching of the MOSFETs. DH is gate signal to drive upper
MOSFET. DL is lower gate signal to drive lower MOSFET.
FB Ripple
Voltage (VFB)
FB threshold
current crosses zero. At this time both MOSFETs remain off
until V FB drops to the 600mV threshold. Because the
MOSFETs are off, the load is supplied by the output
capacitor.
If the inductor current does not reach zero on any switching cycle, the controller immediately exits power-save and
returns to forced continuous mode.
Figure 5 shows power-save operation at light loads.
FB Ripple
Voltage
(VFB)
DH on-time is triggered when
VFB reaches the FB Threshold.
DH
Zero (0A)
On-time (TON)
DH
On-time
(TON)
FB threshold
Inductor
Current
DC Load Current
Inductor
Current
Dead time varies
according to load
DH On-time is triggered when
VFB reaches the FB Threshold.
DL
DL drives high when on-time is completed.
DL remains high until inductor current reaches zero.
Figure 5 — Power Save Operation
DL
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
Figure 4 — Forced Continuous Mode Operation
Power Save Operation
The SC401B provides power-save operation at light loads
with no minimum operating frequency. With power-save
enabled, the internal zero crossing comparator monitors
the inductor current via the voltage across the low-side
MOSFET during the off-time. If the inductor current falls to
zero for 8 consecutive switching cycles, the controller
enters power-save operation. It will turn off the low-side
MOSFET on each subsequent cycle provided that the
Smart Power Save Protection
Active loads may leak current from a higher voltage into
the switcher output. Under light load conditions with
power save enabled, this can force VOUT to slowly rise and
reach the over-voltage threshold, resulting in a hard shutdown. Smart power save prevents this condition. When
the FB voltage exceeds 10% above nominal, the device
immediately disables power save, and DL drives high to
turn on the low-side MOSFET. This draws current from
VOUT through the inductor and causes VOUT to fall. When VFB
drops back to the 600mV trip point, a normal TON switching cycle begins. This method prevents a hard OVP shutdown and also cycles energy from VOUT back to VIN. It also
minimizes operating power by avoiding forced conduc18
SC401B
Applications Information (continued)
SmartDriveTM
For each DH pulse the DH driver initially turns on the highside MOSFET at a lower speed, allowing a softer, smooth
turn-off of the low-side diode. Once the diode is off and
the LX voltage has risen 0.5V above PGND, the SmartDrive
circuit automatically drives the high-side MOSFET on at a
rapid rate. This technique reduces switching losses while
maintaining high efficiency and also avoids the need for
snubbers or series resistors in the gate drive.
VOUT drifts up to due to leakage
current flowing into COUT
Smart Power Save
Threshold
VOUT discharges via inductor
and low-side MOSFET
DH and DL off
High-side
Drive (DH)
Single DH on-time pulse
after DL turn-off
ILOAD
ILIM
Figure 7 — Valley Current Limit
Setting the valley current limit to 15A results in a peak
inductor current of 15A plus peak ripple current. In this
situation, the average (load) current through the inductor
is 15A plus one-half the peak-to-peak ripple current.
The internal 10μA current source is temperature compensated at 4100ppm in order to provide tracking with the
RDSON.
Low-side
Drive (DL)
DL turns on when Smart
PSAVE threshold is reached
IPEAK
Time
Normal VOUT ripple
FB
threshold
current in the low-side MOSFET reduces enough to bring
the ILIM voltage back up to zero. This method regulates
the inductor valley current at the level shown by ILIM in
Figure 7.
Inductor Current
tion mode operation. Figure 6 shows typical waveforms
for the Smart Power Save feature.
Normal DL pulse after DH
on-time pulse
DL turns off when FB
threshold is reached
Figure 6 — Smart Power Save
Current Limit Protection
The device features programmable current limiting, which
is accomplished by using the RDSON of the lower MOSFET
for current sensing. The current limit is set by RILIM resistor.
The RILIM resistor connects from the ILIM pin to the LXS pin
which is also the drain of the low-side MOSFET. When the
low-side MOSFET is on, an internal ~10μA current flows
from the ILIM pin and through the RILIM resistor, creating a
voltage drop across the resistor. While the low-side
MOSFET is on, the inductor current flows through it and
creates a voltage across the RDSON. The voltage across the
MOSFET is negative with respect to ground. If this MOSFET
voltage drop exceeds the voltage across RILIM, the voltage
at the ILIM pin will be negative and current limit will activate. The current limit then keeps the low-side MOSFET on
and will not allow another high-side on-time, until the
The RILIM value is calculated by the following equation.
RILIM = 495 x ILIM x [0.0647 x (5V - VDD) +1]
When selecting a value for RILIM be sure not to exceed the
absolute maximum voltage value for the ILIM pin. Note
that because the low-side MOSFET with low RDSON is used
for current sensing, the PCB layout, solder connections,
and PCB connection to the LX node must be done carefully to obtain good results. RILIM should be connected
directly to LXS (pin 28).
Soft-Start of PWM Regulator
SC401B has a programmable soft-start time that is controlled by an external capacitor at the SS pin. After the
controller meets both UVLO and EN/PSV thresholds, the
controller has an internal current source of 3µA flowing
through the SS pin to charge the capacitor. During the
19
SC401B
Applications Information (continued)
start up process (Figure 8), 40% of the voltage at the SS
pin is used as the reference for the FB comparator. The
PWM comparator issues an on-time pulse when the
voltage at the FB pin is less than 40% of the SS pin. As a
result, the output voltage follows the SS voltage. The
output voltage reaches and maintains regulation when
the soft start voltage is > 1.5V. The time between the first
LX pulse and VOUT reaching regulation is the soft-start time
(tSS). The calculation for the soft-start time is shown by the
following equation.
t SS
CSS u
1 .5 V
3PA
The voltage at the SS pin continues to ramp up and eventually equals 64% of VDD. After the soft start completes, the
FB pin voltage is compared to an internal reference of 0.6V.
The delay time between the VOUT regulation point and
PGOOD going high is shown by the following equation.
tPGOOD -DELAY
CSS u (0.64 u VDD 1.5 V )
3PA
voltage level. Pre-bias startup is achieved by turning off
the lower gate when the inductor current falls below zero.
This method prevents the output voltage from
discharging.
Power Good Output
The PGOOD (power good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the
FB pin is 10% below the nominal voltage, PGOOD is pulled
low. It is held low until the output voltage returns above
-8% of nominal.
PGOOD will transition low if the VFB pin exceeds +20% of
nominal, which is also the over-voltage shutdown threshold. PGOOD also pulls low if the EN/PSV pin is low when
VDD is present.
Output Over-Voltage Protection
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 600mV + 20%
(720mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off, until the EN/PSV input
is toggled or VDD is cycled. There is a 5μs delay built into
the OVP detector to prevent false transitions. PGOOD is
also low after an OVP event.
Output Under-Voltage Protection
When VFB falls 25% below its nominal voltage (falls to
450mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tristate the MOSFETs. The controller stays off until EN/PSV is
toggled or VDD is cycled.
VDD UVLO, and POR
Figure 8 — Soft-start Timing Diagram
Pre-Bias Startup
The SC401B can start up normally even when there is an
existing output voltage present. The soft start time is still
the same as normal start up (when the output voltage
starts from zero). The output voltage starts to ramp up
when 40% of the voltage at SS pin meets the existing FB
UVLO (Under-Voltage Lock-Out) circuitry inhibits switching
and tri-states the DH/DL drivers until VDD rises above 3V.
An internal POR (Power-On Reset) occurs when VDD
exceeds 3V, which resets the fault latch and a soft-start
counter cycle begins which prepares for soft-start. The
SC401B then begins a soft-start cycle. The PWM will shut
off if VDD falls below 2.4V.
20
SC401B
Applications Information (continued)
LDO Regulator
SC401B has an option to bias the switcher by using an
internal LDO from VIN. The LDO output is connected to
VDD internally. The output of the LDO is programmable
by using external resistors from the VDD pin to AGND (see
Figure 9). The feedback pin (FBL) for the LDO is regulated
to 750mV.
VDD
RLDO1
To FBL pin
RLDO2
Figure 9 — LDO Output Voltage Selection
The LDO output voltage is set by the following equation.
VLDO
The ENL pin also acts as the switcher under-voltage lockout
for the VIN supply. When SC401B is self-biased from the LDO
and runs from the VIN power source only, the VIN UVLO
feature can be used to prevent false UV faults for the PWM
output by programming with a resistor divider at the VIN,
ENL and AGND pins. When SC401B has an external bias
voltage at VDD and the ENL pin is used to program the VIN
UVLO feature, the voltage at FBL needs to be higher than
750mV to force the LDO off.
Timing is important when driving ENL with logic and not
implementing VIN UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM
output turning off. If ENL goes below the VIN UVLO
threshold and stays above 1V, then the switcher will turn
off but the LDO will remain on.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
·
§
R
750mV u ¨¨1 LDO1 ¸¸
R
LDO 2 ¹
©
A minimum capacitance of 1μF referenced to AGND is
normally required at the output of the LDO for stability.
1. ENL pin
2. VIN input voltage
Note that if the LDO voltage is set lower than 4.5V, the
minimum output capacitance for the LDO is 10uF.
When the ENL pin is high and VIN is above the UVLO point,
the LDO will begin start-up. During the initial phase, when
the VDD voltage (which is the LDO output voltage) is less
than 0.75V, the LDO initiates a current-limited start-up
(typically 65mA) to charge the output capacitors while
protecting from a short circuit event. When VDD is greater
than 0.75V but still less than 90% of its final value (as
sensed at the FBL pin), the LDO current limit is increased
to ~115mA. When VDD has reached 90% of the final value
(as sensed at the FBL pin), the LDO current limit is increased
to ~200mA and the LDO output is quickly driven to the
nominal value by the internal LDO regulator. It is recommended that during LDO start-up to hold the PWM
switching off until the LDO has reached 90% of the final
value. This prevents overloading the current-limited LDO
output during the LDO start-up.
LDO ENL Functions
The ENL input is used to enable/disable the internal LDO.
When ENL is a logic low, the LDO is off. When ENL is above
the VIN UVLO threshold, the LDO is enabled and the
switcher is also enabled if the EN/PSV and VDD are above
their threshold. The table below summarizes the function
of ENL and EN/PSV pins.
EN/PSV
ENL
LDO
Switcher
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Low, < 0.4V
Low, < 0.4V
1.0V < High < 2.6V
1.0V < High < 2.6V
High, > 2.6V
High, > 2.6V
OFF
OFF
ON
ON
ON
ON
OFF
ON
OFF
OFF
OFF
ON
21
SC401B
Applications Information (continued)
Due to the initial current limitations on the LDO during
power up (Figure 10), any external load attached to the
VDD pin must be limited to less than the start up current
before the LDO has reached 90% of its final regulation
value.
VVLDO Final
Voltage regulating
with ~ 200mA
current limit
90% of
VVLDO Final
Switch-over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that
are inherent to its construction, as shown in Figure 11. If
the voltage at the VOUT pin is higher than VDD, then the
respective diode will turn on and the current will flow
through this diode. This has the potential of damaging
the device. Therefore, VOUT must be less than VDD to
prevent damaging the device.
Switchover
control
Constant current
startup @ ~ 115mA
0.7V
Switchover
MOSFET
VOUT
LDO
Short-circuit Protection @ ~ 65mA
Figure 10 — LDO Start-Up
Parasitic diode
LDO Switch-Over Operation
The SC401B includes a switch-over function for the LDO.
The switch-over function is designed to increase efficiency
by using the more efficient DC-DC converter to power the
LDO output, avoiding the less efficient LDO regulator
when possible. The switch-over function connects the
VDD pin directly to the VOUT pin using an internal switch.
When the switch-over is complete the LDO is turned off,
which results in a power savings and maximizes efficiency.
If the LDO output is used to bias the SC401B, then after
switch-over the device is self-powered from the switching
regulator with the LDO turned off.
The switch-over starts 32 switching cycles after PGOOD
output goes high. The voltages at the VDD and VOUT pins
are then compared; if the two voltages are within ±300mV
of each other, the VDD pin connects to the VOUT pin using
an internal switch, and the LDO is turned off. To avoid
unwanted switch-over, the minimum difference between
the voltages for VOUT and VDD should be ±500mV.
It is not recommended to use the switch-over feature for
an output voltage less than VDD UVLO threshold since the
SC401B is not operational below that threshold.
VDD
Figure 11— Switch-over MOSFET Parasitic Diodes
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor
ripple current must be specified.
The maximum input voltage (VINMAX) is the highest specified input voltage. The minimum input voltage ( VINMIN) is
determined by the lowest input voltage after evaluating
the voltage drops due to connectors, fuses, switches, and
PCB traces.
The following parameters define the design.
•
•
•
•
Nominal output voltage (VOUT )
Static or DC output tolerance
Transient response
Maximum load current (IOUT )
22
SC401B
Applications Information (continued)
There are two values of load current to evaluate — continuous load current and peak load current. Continuous
load current relates to thermal stresses which drive the
selection of the inductor and input capacitors. Peak load
current determines instantaneous component stresses
and filtering requirements such as inductor saturation,
output capacitors, and design of the current limit circuit.
The following values are used in this design.
•
•
•
•
•
VIN = 12V + 10%
VOUT = 1.5V + 4%
VDD = 5V
fSW = 300kHz
Load = 15A maximum
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the
power conversion efficiency.
The desired switching frequency is 300kHz which results
from using components selected for optimum size and
cost.
A resistor (RTON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
R TON
T ON
k
25pF u fSW
V OUT
V INMAX u f SW
Use the value associated with maximum VIN for TON.
TON = 379 ns at 13.2VIN, 1.5VOUT, 300kHz
Substituting for RTON results in the following solution.
RTON = 133.3kΩ, use RTON = 130kΩ
efficiency. Higher inductor values will reduce the ripple
current/voltage and for a given DC resistance are more
efficient. However, larger inductance translates directly
into larger packages and higher cost. Cost, size, output
ripple, and efficiency are all used in the selection process.
The ripple current will also set the boundary for PSAVE
operation. The switching will typically enter PSAVE mode
when the load current decreases to 1/2 of the ripple
current. For example, if ripple current is 4A then PSAVE
operation will typically start for loads less than 2A. If ripple
current is set at 40% of maximum load current, then PSAVE
will start for loads less than 20% of maximum current.
The inductor value is typically selected to provide a ripple
current that is between 25% to 50% of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
During the on-time, voltage across the inductor is
(VIN - VOUT ). The equation for determining inductance is
shown next.
L
( VIN VOUT ) u TON
IRIPPLE
Example
In this example, the inductor ripple current is set equal to
30% of the maximum load current. Therefore ripple
current will be 30% x 15A or 4.5A. To find the minimum
inductance needed, use the VIN and TON values that correspond to VINMAX.
L
(13.2 1.5) u 379ns
4. 5 A
0.99PH
A slightly larger value of 1µH is selected. This will decrease
the maximum IRIPPLE to 4.43A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
Inductor Selection
In order to determine the inductance, the ripple current
must first be defined. Low inductor values result in smaller
size but create higher ripple current which can reduce
23
SC401B
Applications Information (continued)
The ripple current under minimum VIN conditions is also
checked using the following equations.
25pF u RTON u VOUT
VINMIN
TON _ VINMIN
IRIPPLE
451ns
( VIN VOUT ) u TON
L
IRIPPLE _ VINMIN
(10.8 1.5) u 451ns
4.19 A
1PH
Capacitor Selection
The output capacitors are chosen based upon required
ESR and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal
to the valley of the output ripple plus 1/2 of the peak-topeak ripple. A change in the output ripple voltage will
lead to a change in DC voltage at the output.
The design goal for output voltage ripple is 3% of 1.5V or
45mV. The maximum ESR value allowed is shown by the
following equations.
ESRMAX
VRIPPLE
IRIPPLEMAX
COUTMIN = 316µF
Peak inductor current is shown by the next equation.
ILPK = IMAX + 1/2 x IRIPPLEMAX
ILPK = 10 + 1/2 x 4.43 = 12.215A
Rate of change of Load Current
The output capacitance is usually chosen to meet transient requirements. A worst-case load release, from
maximum load to no load at the exact moment when
inductor current is at the peak, determines the required
capacitance. If the load release is instantaneous (load
changes from maximum to zero in < 1µs), the output
capacitor must absorb all the inductor’s stored energy.
This will cause a peak voltage on the capacitor according
to the following equation.
1
§
·2
L¨ IOUT u IRIPPLEMAX ¸
2
©
¹
2
2
The following can be used to calculate the needed capacitance for a given dILOAD/dt.
VPEAK VOUT 2
1.65 1.5
During the load release time, the voltage cross the inductor is approximately -VOUT. This causes a down-slope or
falling di/dt in the inductor. If the load di/dt is not much
faster than the di/dt of the inductor, then the inductor
current will tend to track the falling load current. This will
reduce the excess inductive energy that must be absorbed
by the output capacitor, therefore a smaller capacitance
can be used.
45mV
4.43 A
ESRMAX = 10.2 mΩ
COUTMIN
COUTMIN
1
§
·2
1PH¨10 u 4.43 ¸
2
©
¹
2
Assuming a peak voltage VPEAK of 1.65V (150mV rise upon
load release), and a 10A load release, the required capacitance is shown by the next equation.
dlLOAD
dt
IMAX = maximum load release = 10A
Lu
COUT
ILPK u
ILPK
I
MAX u dt
VOUT dlLOAD
2VPK VOUT Example
dlLOAD
dt
2 .5 A
1Ps
This would cause the output current to move from 10A to
0A in 4µs, giving the minimum output capacitance
requirement shown in the following equation.
COUT
12.215 u
1PH u
12.215 10
u 1Ps
1 .5
2 .5
21.65 1.5 COUT = 169 µF
24
SC401B
Applications Information (continued)
Note that COUT is much smaller in this example, 169µF
compared to 316µF based on a worst-case load release. To
meet the two design criteria of minimum 316µF and
maximum 10.2mΩ ESR, select one capacitor of 330µF and
9mΩ ESR.
Electrolytic capacitors have parasitic inductance or equivalent series inductance (ESL). This ESL increases the peak
to peak magnitude of the output voltage ripple. Therefore,
it is recommended that an additional small ceramic
capacitor be placed in parallel with COUT in order to filter
high frequency switching noise. As a result of the combination of the electrolytic capacitor’s ESL and the ceramic
capacitor, the output votlage ripple can take a resonant
form instead of the ideal triangle shape. If the ESL value is
high, it can cause cycle by cycle variation in the converter
switching frequency. The capacitor manufacturers usually
include the impedance vs frequency curve in their datasheets. For example, EEF-SX0E331ER from Panasonic or
4TPE220MF from Sanyo has typically 1.5nH at 10MHz.
Stability Considerations
Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
250ns minimum off-time has expired. In extreme cases
the noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect operation. This form of instability can usually be avoided by
providing the FB pin with a smooth, clean ripple signal
that is at least 10mVp-p, which may dictate the need to
increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout as discussed in the
Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a
small (~ 10pF) capacitor across the upper feedback resistor, as shown in Figure 12. This capacitor should be left
unpopulated until it can be confirmed that double-pulsing
exists. Adding the CTOP capacitor will couple more ripple
into FB to help eliminate the problem. An optional connection on the PCB should be available for this capacitor.
CTOP
VOUT
To FB pin
R1
R2
Figure 12 — Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and discharging during the switching cycle. For most applications the minimum ESR ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching frequency. The formula for minimum ESR is shown by the
following equation.
ESR MIN
3
2 u S u C OUT u f sw
Using Ceramic Output Capacitors
When the system is using high ESR value capacitors, the
feedback voltage ripple lags the phase node voltage by 90
degrees. Therefore, the converter is easily stabilized.
25
SC401B
Applications Information (continued)
When the system is using ceramic output capacitors, the
ESR value is normally too small to meet the above ESR criteria. As a result, the feedback voltage ripple is 180
degrees from the phase node and behaves in an unstable
manner. In this application it is necessary to add a small
virtual ESR network that is composed of two capacitors
and one resistor, as shown in Figure 13.
VL
Vc L u
CL
RL
R1
COUT
R1 // R2 u S u C C
R1 // R2 u S u C C 1
Figure 15 shows the magnitude of the ripple contribution
due to the output voltage ripple at the FB pin.
L
CC
+- D x VIN
VFBc L
DCR
L
RL
It is shown by the following equation.
DCR
VOUT
VOUT
VL
CL
CC
CC
R1
R1
COUT
R2
FB
pin
R2
FB
pin
COUT
R2
FB
pin
Figure 15 — FB Voltage by Output Voltage
Figure 13 — Virtual ESR Ramp Circuit
It is shown by the following equation.
The ripple voltage at FB is a superposition of two voltage
sources: the voltage across C L and the output ripple
voltage. They are defined in the following equations.
IL u DCR(s u L / DCR 1)
S u RLCL 1
Vc L
'VOUT
Figure 14 shows the magnitude of the ripple contribution
due to CL at the FB pin.
L
+-
D x VIN
DCR
VL
CL
'VOUT u
R2
1
R1 //
R2
S u CC
The purpose of this network is to couple the inductor
current ripple information into the feedback voltage such
that the feedback voltage has 90 degrees phase lag to the
switching node similar to the case of using standard high
ESR capacitors. This is illustrated in Figure 16.
'IL
8C u fSW
RL
VFB'VOUT
VOUT
FB contribution by
output voltage ripple
FB contribution
by CL
FB
pin
CC
R1
R2
LX
Combined FB
IL
Figure 16 — FB voltage in Phasor Diagram
Figure 14 — FB Voltage by CL Voltage
26
SC401B
Applications Information (continued)
The magnitude of the feedback ripple voltage, which is
dominated by the contribution from CL , is controlled by
the values of R1, R2 and CC . If the corner frequency of (R1//
R2) x CC is too high, the ripple magnitude at the FB pin will
be smaller, which can lead to double-pulsing. Conversely,
if the corner frequency of (R1// R2) x CC is too low, the ripple
magnitude at FB pin will be higher. Since the SC401B
regulates to the valley of the ripple voltage at the FB pin,
a high ripple magnitude is undesirable as it significantly
impacts the output voltage regulation. As a result, it is
desirable to select a corner frequency for (R1// R2) x CC to
achieve enough, but not excessive, ripple magnitude and
phase margin. The component values for R 1, R2, and CC
should be calculated using the following procedure.
Select CL (typical 10nF) and RL to match with L and DCR
time constant using the following equation.
RL
L
DCR u CL
Select CC by using the following equation.
CC |
1
3
u
R1 // R 2 2 u S u fsw
The resistor values (R1 and R2) in the voltage divider circuit
set the VOUT for the switcher. The typical value for CC is
from 10pF to 1nF.
Dropout Performance
The output voltage adjustment range for continuous conduction operation is limited by the fixed 250ns (typical)
minimum off-time of the one-shot. When working with
low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times.
The duty-factor limitation is shown by the next equation.
DUTY
TON(MIN)
TON(MIN) TOFF(MAX )
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static conditions it trips when the feedback pin is 600mV, 1%.
The on-time pulse from the SC401B in the design example
is calculated to give a pseudo-fixed frequency of 300kHz.
Some frequency variation with line and load is expected.
This variation changes the output ripple voltage. Because
adaptive on-time converters regulate to the valley of the
output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the output ripple is 50mV with
VIN = 6 volts, then the measured DC output will be 25mV
above the comparator trip point. If the ripple increases to
80mV with VIN = 17V, then the measured DC output will be
40mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple.
The use of 1% feedback resistors may result in up to 1%
error. If tighter DC accuracy is required, 0.1% resistors
should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor effect on the DC output voltage. The output ESR
also affects the output ripple and thus has a minor effect
on the DC output voltage.
Switching Frequency Variation
The switching frequency varies with load current as a
result of the power losses in the MOSFETs and DCR of the
inductor. For a conventional PWM constant-frequency
converter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. An adaptive on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing
energy from VIN as losses increase). The on-time is essentially constant for a given VOUT/VIN combination, to offset
the losses the off-time will tend to reduce slightly as load
increases. The net effect is that switching frequency
increases slightly with increasing load.
27
SC401B
Applications Information (continued)
PCB Layout Guidelines
IC Decoupling Capacitors
A 1 μF capacitor must be located as close as possible to the IC and directly connected to pins 3
(VDD) and 4 (AGND).
Another 1 μF capacitor must be located as close
as possible to the IC and directly connected to
pins 3 (VDD) and PGND plane.
•
The optimum layout for the SC401B is shown in Figure 17.
This layout shows an integrated FET buck regulator with a
maximum current of 15A. The total PCB area is approximately 25 x 29 mm with single side components.
•
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
•
IC Decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
CSS
BST, ILIM, and LX
CIN and COUT placement and Current Loops
•
•
All components shown Top Side
VDD Decoupling Capacitor
IC with vias for
LX, AGND, VIN
RTON
AGND plane on
inner layer
CBST
Vout sense trace
on inner layer
L
VDD
RFB2
RFB1
CTOP
RILIM
Pin 1 marking
RGND
Css
•
•
•
•
•
•
•
PGND Plane
PGND requires its own copper plane with no
other signal traces routed on it.
Copper planes, multiple vias and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the IC.
The PGND copper area between the input
capacitors, output capacitors and PGND pins
must be as tight and compact as possible to
reduce the area of the PCB that is exposed to
noise due to current flow on this node.
CIN
CIN
COUT
PGND on inner
or bottom layer
Cer.
RGND — AGND connects to VIN plane on
top and/or
PGND close to IC
bottom layer
SP or
POSCAP
LX plane on top and
bottom layer
VOUT Plane on top
and bottom layer
PGND on top
layer
Figure 17 — PCB Layout
28
SC401B
Applications Information (continued)
AGND Island
AGND should have its own island of copper with
no other signal traces routed on this layer that
connects the AGND pins and pad of the IC to the
analog control components.
All of the components for the analog control circuitry should be located so that the connections
to AGND are done by wide copper traces or vias
down to AGND.
Connect PGND to AGND with a short trace or 0Ω
resistor. This connection should be as close to
the IC as possible.
•
•
•
•
•
•
FB, VOUT, and Other Analog Control Signals
The connection from the V OUT power to the
analog control circuitry must be routed from the
output capacitors and located on a quiet layer.
The traces between Vout and the analog control
circuitry (VOUT, and FB pins) must be wide, short
and routed away from noise sources, such as
BST, LX, VIN, and PGND between the input
capacitors, output capacitors, and the IC.
The feedback components for the switcher and
the LDO need to be as close to the FB and FBL
pins of the IC as possible to reduce the possibility of noise corrupting these analog signals.
•
•
CSOFT should be close to the IC and kept away
from the boost capacitor. Connect the AGND
end of CSOFT to the AGND plane at pin 4.
The LX node between the IC and the inductor
should be wide enough to handle the inductor
current and short enough to eliminate the possibility of LX noise corrupting other signals.
Multiple vias should be used on the LX PAD to
provide good thermals and connection to an
internal or bottom layer LX plane.
Capacitors and Current Loops
Figure 17 shows the placement of input/output
capacitors and inductor. This placement shows
the smallest current loops between the input/
output capacitors, the SC401B and the inductor
to reduce the IR drop across the copper.
•
•
BST, ILIM, TON, SS and LX
The connections for the boost capacitor
between the BST and LXBST must be short, wide
and directly connected.
ILIM and TON nodes must be as short as possible
to ensure the best accuracy in current limit and
on time.
RILIM should be close to the IC and connected
between LXS (pin 28) and ILIM (pin 27) only.
RTON should be close to the IC and connected
between TON (pin 31) and AGND (pin 30).
•
•
•
•
29
SC401B
Outline Drawing — MLPQ-5x5-32
DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
.031
.039 0.80
1.00
A
.002 0.00
0.05
A1 .000
(.008)
(0.20)
A2
b
.007 .010 .012 0.18 0.25 0.30
D
.193 .197 .201 4.90 5.00 5.10
D1 .076 .078 .080 1.92 1.97 2.02
E
.193 .197 .201 4.90 5.00 5.10
E1 .135 .137 .139 3.43 3.48 3.53
e
.020 BSC
0.50 BSC
L
.012 .016 .020 0.30 0.40 0.50
32
32
N
aaa
.003
0.08
bbb
.004
0.10
B
D
A
PIN 1
INDICATOR
(LASER MARK)
E
A2
A
aaa
SEATING
PLANE
C
C
A1
3.48
D1
0.76
1.05
LxN
1.49
E1
3.61
1.66
2
1
0.76
N
R0.20
PIN 1
IDENTIFICATION
bxN
e
bbb
C A
B
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
30
SC401B
Land Pattern — MLPQ-5x5-32
3.48
K1
K
DIMENSIONS
1.74
(C)
H2
1.74
H
3.61
G
Z
H1
Y
X
P
DIM
INCHES
MILLIMETERS
C
(.195)
(4.95)
G
.165
4.20
H
.137
3.48
H1
.059
1.49
H2
.065
1.66
K
.078
1.97
K1
.041
1.05
P
.020
0.50
X
.012
0.30
Y
.030
0.75
Z
.224
5.70
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS.
31
SC401B
© Semtech 2011
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright
owner. The information presented in this document does not form part of any quotation or contract, is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation
resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress
including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the
specified range.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFESUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer
purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold
Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages
and attorney fees which could arise.
Notice: All referenced brands, product names, service names and trademarks are the property of their respective
owners.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
32