SEMTECH SC424EVB

SC414/SC424
6A Integrated FET Regulator
with 5V LDO
POWER MANAGEMENT
Features
Description
„
The SC414/SC424 is a stand-alone synchronous buck regulated power supply. It features integrated power MOSFETs,
a bootstrap switch, and a 5V LDO in a space-saving MLPQ4x4mm 28-pin package. The device is highly efficient and
uses minimal PCB area. It uses pseudo-fixed frequency
adaptive on-time operation to provide fast transient
response.
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
Input voltage — 3V to 28V
Internal power MOSFETs — 6A
Integrated bootstrap switch
Smart power-save protection
Integrated 5V, 150mA LDO with bypass capability
TC compensated RDS(ON) sensed current limit
Pseudo-fixed frequency adaptive on-time control
Designed for use with ceramic capacitors
Programmable VIN UVLO threshold
Independent enable for switcher and LDO
Selectable ultrasonic power-save (SC414)
Selectable power-save (SC424)
Internal soft-start and soft-shutdown at output
Internal reference — 1% tolerance
Over-voltage and under-voltage fault protection
Power good output
SmartDriveTM
Lead-free 4x4mm, 28 Pin MLPQ package
Fully WEEE and RoHS compliant, and halogen free
Applications
„
„
„
„
„
„
Notebook, desktop, tablet, and server computers
Networking and telecommunication equipment
Printers, DSL, and STB applications
Embedded applications
Power supply modules
Point of load power supplies
The SC414/SC424 supports using standard capacitor types
such as electrolytic or special polymer, in addition to
ceramic, at switching frequencies up to 1MHz. The programmable frequency, synchronous operation, and selectable power-save provide high efficiency operation over a
wide load range.
Additional features include cycle-by-cycle current limit,
soft-start, under and over-voltage protection, programmable over-current protection, soft shutdown, and selectable power-save. The device also provides separate enable
inputs for the PWM controller and LDO as well as a power
good output for the PWM controller.
The input voltage can range from 3V to 28V. The wide
input voltage range, programmable frequency, and 5V
LDO make the device extremely flexible and easy to use in
a broad range of applications. It can be used for single cell
or multi-cell battery systems in addition to traditional DC
power supply applications.
The 5V LDO or an external 3.3V to 5V supply can be used
to provide the bias voltage for the SC414/SC424. When
the SC414/SC424 is used as a 5V output switching regulator, the 5V LDO can be used as an initial bias supply for the
device. Once the switch regulator output is in the switch
over range, the LDO will be bypassed by the switcher
output for optimum efficiency.
September 11, 2009
© 2009 Semtech Corporation
1
SC414/SC424
Typical Application Circuit
ENABLE LDO
ENABLE PSAVE
V5V
RTON
154KΩ
5
6
7
ILIM
LXS
AGND
PGOOD
LX
PGND
SC414/SC424
VOUT
PGND
VIN
PGND
VLDO
PGND
BST
LX
VIN
C3
100nF
AGND
CBST
1μF
8
9
10
11
12
13
PGND
4
AGND
PGND
1μF
VOUT
PGOOD
22
23
LX
LXBST
3
C2
1μF
24
V5V
VIN
2
25
FB
VIN
1
VIN
V5V
TON
ENL
VIN
FB
26
EN/PSV
27
28
PAD 2
C1
RPGOOD
10KΩ
RILIM
9.09KΩ
LX
PAD 1
21
20
19
18
17
16
15
PAD 3
14
VIN
+12V
CIN
10μF
RGND
0
CIN
10μF
VOUT
L1
1.5μH
VOUT
FB
COUT
220μF
RFB1
10KΩ
+
C4
10nF
1V @ 6A, 250kHz
RFB2
30KΩ
Key Components
Component
Value
Manufacturer
Part Number
Web
CIN
10μF/25V
Murata
GRM32DR71E106KA12L
www.murata.com
COUT
220μF/15mΩ/6.3V
Panasonic
EEFUE0J221R
www.panasonic.com
L1
1.5μH/9A
Vishay
IHLP2525CZER1R5M01
www.vishay.com
All other small signal components (resistors and capacitors) are standard SMT devices.
2
SC414/SC424
4
VIN
5
VLDO
6
BST
7
LXS
PGOOD
EN/PSV
ILIM
TON
AGND
23
22
AGND
PAD 1
LX
PAD 3
VIN
PAD 2
VIN
8
9
10
11
12
13
14
PGND
VOUT
24
PGND
3
25
Top View
VIN
AGND
26
LXBST
2
27
VIN
V5V
28
Ordering Information
VIN
FB
1
ENL
Pin Configuration
21
LX
20
LX
19
PGND
18
PGND
17
PGND
16
PGND
15
LX
Device
Package
SC414MLTRT(1)(2)
MLPQ-28 4x4
SC424MLTRT(1)(2)
MLPQ-28 4x4
SC414EVB
Evaluation Board
SC424EVB
Evaluation Board
Notes:
1) Available in tape and reel only. A reel contains 3000 devices.
2) Lead-free packaging only. Device is WEEE and RoHS compliant,
and halogen free.
SC414 and SC424
MLPQ-28; 4x4, 28 LEAD
Marking Information
SC414
yyww
xxxxx
xxxxx
SC424
yyww
xxxxx
xxxxx
yyww = Date Code
xxxxx = Semtech Lot Number
yyww = Date Code
xxxxx = Semtech Lot Number
3
SC414/SC424
Absolute Maximum Ratings
Recommended Operating Conditions
LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30
Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 28
LX to PGND (V) (transient — 100ns max.) . . . . . . -2 to +30
V5V to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5
VIN to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30
VOUT to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 to 5.5
EN/PSV, PGOOD, ILIM, to GND (V) . . . . . . -0.3 to +(V5V + 0.3)
Thermal Information
VOUT, VLDO, FB, to GND (V) . . . . . . . . . . . -0.3 to +(V5V + 0.3)
V5V to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6
Storage Temperature (°C) . . . . . . . . . . . . . . . . . . . . -60 to +150
TON to PGND (V) . . . . . . . . . . . . . . . . . . . . . -0.3 to +(V5V - 1.5)
Maximum Junction Temperature (°C) . . . . . . . . . . . . . . . . 150
ENL (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN
Operating Junction Temperature (°C) . . . . . . . .-40 to +125
BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
Thermal resistance, junction to ambient (2) (°C/W)
BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35
High-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
AGND to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3
Low-side MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
PWM controller and LDO thermal resistance . . . . . 40
Peak IR Reflow Temperature (°C) . . . . . . . . . . . . . . . . . . . . 260
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless specified: VIN =12V, TA = +25°C for Typical, -40 to +85 °C for Min. and Max., TJ < 125°C, V5V = +5V, Typical Application Circuit
Parameter
Conditions
Min
Typ
Max
Sensed at ENL pin, rising edge
2.40
2.60
2.95
Sensed at ENL pin, falling edge
2.235
2.40
2.565
Units
Input Supplies
VIN UVLO Threshold(1)
(not available for V5V < 4.5V)
VIN UVLO Hysteresis
V
EN/PSV = High
0.2
V
Measured at V5V pin, rising edge
2.50
2.9
3.0
Measured at V5V pin, falling edge
2.40
2.7
2.90
V5V UVLO Threshold
V
V5V UVLO Hysteresis
0.2
ENL, EN/PSV = 0V, VIN = 28V
8.5
Standby mode; ENL=V5V, EN/PSV = 0V
130
VIN Supply Current
V
20
μA
4
SC414/SC424
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
ENL, EN/PSV = 0V , V5V = 5V
3
7
ENL, EN/PSV = 0V , V5V = 3V
2
SC414, EN/PSV = V5V, no load (fSW = 25kHz),
VFB > 750mV(2)
1
SC424, EN/PSV = V5V, no load, VFB > 750mV(2)
0.4
Units
Input Supplies (continued)
μA
V5V Supply Current
(2)
V5V = 5V, fSW = 250kHz, EN/PSV = floating, no load
mA
4
V5V = 3V, fSW = 250kHz, EN/PSV = floating, no load(2)
2.5
Static VIN and load, 0 to +85 °C, V5V = 3V or 5V
0.744
Static VIN and load, -40 to +85 °C, V5V = 3V or 5V
0.7425
0.750
0.756
V
0.7575
V
FB Comparator Threshold
Continuous mode operation
1000
Frequency Range
kHz
Minimum fSW , (SC414 only), EN/PSV = V5V, no load
25
Bootstrap Switch Resistance
10
Ω
Timing
On-Time
Continuous mode operation,
VIN = 15V, VOUT = 3V, RTON = 300kΩ
1350
1500
1650
ns
V5V < 4.5V(3)
Minimum On-Time (2)
80
V5V = 5V
320
V5V = 3V
390
ns
Minimum Off-Time (2)
ns
Soft-Start
Soft-Start Ramp Time (2)
1.7
ms
500
kΩ
Analog Inputs/Outputs
VOUT Input Resistance
Current Sense
Zero-Crossing Detector Threshold
LX - PGND, V5V = 3V or 5V
-3
0
+3
mV
5
SC414/SC424
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
Power Good
Upper limit, VFB > internal 750mV reference
+20
%
Lower limit, VFB < internal 750mV reference
-10
%
V5V = 3V
2
V5V = 5V
4
Power Good Threshold
Start-Up Delay Time (Time between EN going
high and PGOOD going high)
ms
Fault (noise immunity) Delay Time(2)
5
Leakage
μs
1
Power Good On-Resistance
10
μA
Ω
Fault Protection
Valley Current Limit
V5V = 5V, RILIM = 5k Ω
Valley Current Limit
V5V = 3V, RILIM = 5k Ω
3
ILIM Source Current
ILIM Comparator Offset
With respect to AGND
-8
4
5
A
3.4
A
8
μA
0
+8
mV
Output Under-Voltage Fault
VFB with respect to internal 750mV reference,
8 consecutive clock cycles
-25
%
Smart Power-save Protection Threshold (2)
VFB with respect to internal 750mV reference
+10
%
Over-Voltage Protection Threshold
VFB with respect to internal 750mV reference
+20
%
5
μs
150
°C
Over-Voltage Fault Delay(2)
Over-Temperature Shutdown(2)
10°C hysteresis
Logic Inputs/Outputs
Logic Input High Voltage
ENL
Logic Input Low Voltage
ENL
1
V
0.4
V
EN/PSV Input for PSAVE Operation (2)
% of V5V
45
100
%
EN/PSV Input for Forced Continuous Operation (2)
% of V5V
1V
42
%
0
0.4
V
-10
+10
μA
18
μA
+1
μA
EN/PSV Input for Disabling Switcher (2)
EN/PSV Input Bias Current
EN/PSV= V5V or AGND
ENL Input Bias Current
VIN = 28V
FB Input Bias Current
FB = V5V or AGND
11
-1
6
SC414/SC424
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
VLDO load = 10mA
4.9
5.0
5.1
V
Linear Regulator — LDO (not available for V5V < 5V)
VLDO Accuracy
Start-up and foldback, VIN = 12V
85
mA
LDO Current Limit
Operating current limit, VIN = 12V
135
200
VLDO to VOUT Switch-over Threshold (4)
-140
+140
mV
VLDO to VOUT Non-switch-over Threshold (4)
-450
+450
mV
VLDO to VOUT Switch-over Resistance
LDO Drop Out Voltage (5)
VOUT = +5V
2
Ω
From VIN to VVLDO, VVLDO = +5V, IVLDO = 100mA
1.2
V
Notes:
(1) VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
(2) Guaranteed by design.
(3) For V5V less than 4.5V, the On-Time may be limited by the V5V supply voltage and by VIN. See the TON Limitations and V5V Supply Voltage
section in the applications Information.
(4) The switch-over threshold is the maximum voltage differential between the VLDO and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures that
VLDO will not switch-over to VOUT.
(5) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point. Thermal resistance, junction
to ambient — guaranteed by design (°C/W)
7
SC414/SC424
Typical Characteristics
Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424).
Efficiency vs. Load — Forced Continuous Mode
100
VOUT vs. Load — Forced Continuous Mode
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
1.05
1.03
Output Voltage (V)
Efficiency (%)
80
60
40
20
0
1.01
0.99
0.97
0.001
0.01
0.1
IOUT (A)
1
10
0.95
0.001
0.1
IOUT (A)
1
10
Efficiency vs. Load — Powersave Mode (SC414)
Efficiency vs. Load — Powersave Mode (SC414)
100
0.01
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
Externally biased, VIN = 12V, VOUT = 1V
100
3V Bias
80
80
Efficiency (%)
Efficiency (%)
5V Bias
60
40
20
0.01
0.1
IOUT (A)
1
0
0.001
10
Efficiency vs. Load — Powersave Mode (SC424)
0.1
IOUT (A)
1
10
100
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
80
5V Bias
Efficiency (%)
3V Bias
60
40
20
0
0.001
0.01
Efficiency vs. Load — Powersave Mode (SC424)
Externally biased, VIN = 12V, VOUT = 1V
80
Efficiency (%)
40
20
0
0.001
100
60
60
40
20
0.01
0.1
IOUT (A)
1
10
0
0.001
0.01
0.1
IOUT (A)
1
10
8
SC414/SC424
Typical Characteristics (continued)
Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424).
Frequency vs. Load — Forced Continuous Mode
400
VRIPPLE vs. Load — Forced Continuous Mode
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
100
80
300
VRIPPLE (mVP_P)
Frequency (kHz)
350
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
250
200
60
40
20
150
100
0.001
0.01
0.1
IOUT (A)
1
0
0.001
10
1.05
1.03
1.03
1.01
1.01
VOUT(V)
VOUT (V)
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
0.99
0.99
0.97
0.97
0.95
0.001
0.01
0.1
IOUT (A)
1
10
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
0.95
0.001
100
0.01
0.1
IOUT (A)
1
10
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
80
0A
1.5A
VRIPPLE (mVP_P)
Output Voltage (V)
10
VOUT vs. Line — Forced Continuous Mode
1.03
1.01
0.99
3A
6A
6A
3A
60
40
20
0.97
0.95
1
Internally biased at VLDO = 5V, VIN = 12V, VOUT = 1V
VOUT vs. Line — Forced Continuous Mode
1.05
0.1
IOUT (A)
VOUT vs. Load — Powersave Mode (SC424)
VOUT vs. Load — Powersave Mode (SC414)
1.05
0.01
0A
1.5A
0
5
7
9
11
13
15
Input Voltage (V)
17
19
21
5
7
9
11
13
15
Input Voltage (V)
17
19
21
9
SC414/SC424
Typical Characteristics (continued)
Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424).
Powersave Mode — No Load (SC424)
Ultrasonic Powersave Mode — No Load (SC414)
VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
(50mV/div)
(50mV/div)
(5V/div)
(5V/div)
Time (10ms/div)
Time (10μs/div)
Forced Continuous Mode — No Load
Self-Biased Start-Up — Power Good True
VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = ENL = 5V, EN/PSV= float
VIN = 0V to 12V step, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
(500mV/div)
(50mV/div)
(2V/div)
(10V/div)
(5V/div)
(5V/div)
Time (2μs/div)
Time (10ms/div)
Enabled Loaded Output — Power Good True
Output Over-current Response — Normal Operation
VIN = 12V, VOUT = 1V, IOUT = 1A, VLDO = V5V = ENL = 5V. EN/PSV= 5V
VIN = 12V, VOUT = 1V, VLDO = V5V = ENL = 5V, EN/PSV= floating; IOUT ramped to trip point
(500mV/div)
(5A/div)
(500mV/div)
(5V/div)
(10V/div)
(5V/div)
(5V/div)
Time (1ms/div)
Time (100μs/div)
10
SC414/SC424
Typical Characteristics (continued)
Characteristics in this section are based on using the Typical Application Circuit on page 2 (SC414/SC424).
Transient Response — Load Rising (SC414)
VIN = 12V, VOUT = 1V, IOUT = 200mA to 6A, VLDO = V5V = EN/PSV= ENL = 5V
(50mV/div)
Transient Response — Load Falling (SC414)
VIN = 12V, VOUT = 1V, IOUT = 6A to 0A, VLDO = V5V = EN/PSV= ENL = 5V
(50mV/div)
(5A/div)
(5A/div)
(5V/div)
(5V/div)
Time (10μs/div)
Time (10μs/div)
Transient Response — Load Rising (SC424)
VIN = 12V, VOUT = 1V, IOUT = 0A to 6A, VLDO = V5V = EN/PSV= ENL = 5V
Transient Response — Load Falling (SC424)
VIN = 12V, VOUT = 1V, IOUT = 6A to 0A, VLDO = V5V = EN/PSV= ENL = 5V
(50mV/div)
(50mV/div)
(10V/div)
(10V/div)
(5A/div)
(5A/div)
(5V/div)
(5V/div)
Time (10μs/div)
Shorted Output Response — Normal Operation
Time (10μs/div)
Shorted Output Response — Power-UP Operation
VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
VIN = 12V, VOUT = 1V, IOUT = 0A, VLDO = V5V = EN/PSV= ENL = 5V
(500mV/div)
(500mV/div)
(5A/div)
(5A/div)
(10V/div)
(10V/div)
(5V/div)
(5V/div)
Time (40μs/div)
Time (1ms/div)
11
SC414/SC424
Pin Descriptions
Pin #
Pin Name
Pin Function
1
FB
Feedback input for switching regulator used to program the output voltage — connect to an external resistor divider from VOUT to AGND.
2
V5V
Bias input for internal analog circuits and gate drives — connect to external 3V or 5V supply or bias connection to VLDO.
3, 26, PAD 1
AGND
Analog ground
4
VOUT
Switcher output voltage sense pin, and also the input to the internal switch-over between VOUT and VLDO.
5, 8-11
PAD 2
VIN
6
VLDO
7
BST
12
LXBST
15,20, 21,
PAD 3
LX
13, 14, 16-19
PGND
22
PGOOD
23
ILIM
Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LXS.
24
LXS
LX sense — connects to RILIM resistor
Input supply voltage
5V LDO output
Bootstrap pin — connect a capacitor from BST to LXBST to develop the floating supply for the high-side gate
drive.
LX Boost — connect to the BST capacitor.
Switching (phase) node
Power ground
Open-drain power good indicator — high impedance indicates power is good. An external pull-up
resistor is required.
Enable/power save input for the switching regulator — connect to AGND to disable the switching regulator. Float to operate in forced continuous mode (power save disabled). For SC414, connect to V5V to operate
with ultrasonic power save mode enabled. For SC424, connect to V5V to operate with power save mode
enabled with no minimum frequency.
25
EN/PSV
27
TON
On-time programming input — set the on-time by connecting through a resistor to AGND
28
ENL
Enable input for the LDO — connect ENL to AGND to disable the LDO. Drive with logic to +3V for logic control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.
12
SC414/SC424
Block Diagram
V5V
2
VIN
EN/PSV
PGOOD
22
A
25
V5V
VIN
V5V
Bootstrap
Switch
AGND
D
Control & Status
Reference
7
BST
B
LX
12
LXBST
24
LXS
C
PGND
3
ILIM
DL
Hi-side
MOSFET
Soft Start
FB
Gate Drive
Control
On-- time
Generator
1
V5V
FB Comparator
TON
DL
27
Lo-side
MOSFET
Zero Cross Detector
VOUT
4
Bypass Comparator
Valley Current Limit
A
VLDO
6
VIN
Y
B
LDO
VLDO Switchover MUX
28
ENL
A = connected to pins 5, 8-11, PAD 2
B = connected to pins 15, 20, 21, PAD 3
C = connected to pins 13, 14, 16-19
D = connect to pins 3, 26, PAD 1
13
SC414/SC424
Applications Information
Synchronous Buck Converter
The SC414/SC424 is a step down synchronous DC-DC buck
converter with integrated power MOSFETs and a 5V LDO.
The device is capable of 6A operation at very high efficiency. A space saving 4x4 (mm) 28-pin package is used.
The programmable operating frequency range of 200kHz
to 1MHz enables optimizing the configuration for PCB
area and efficiency.
The buck controller uses a pseudo-fixed frequency adaptive on-time control. This control method allows fast transient response which permits the use of smaller output
capacitors.
The adaptive on-time is determined by an internal oneshot timer. When the one-shot is triggered by the output
ripple, the device sends a single on-time pulse to the highside MOSFET. The pulse period is determined by VOUT and
VIN. The period is proportional to output voltage and
inversely proportional to input voltage. With this adaptive
on-time configuration, the device automatically anticipates the on-time needed to regulate VOUT for the present
VIN condition and at the selected frequency.
The advantages of adaptive on-time control are:
•
•
Input Voltage Requirements
The SC414/SC424 requires two input supplies for normal
operation: VIN and V5V. VIN operates over the wide range
from 3V to 28V. V5V requires a 3.3 or 5V supply input that
can be an external source or the internal LDO configured
to supply 5V. If the LDO is enabled, V5V voltage must be
> 5V.
•
•
•
Psuedo-fixed Frequency Adaptive On-time Control
The PWM control method used by the SC414/SC424 is
pseudo-fixed frequency, adaptive on-time, as shown in
Figure 1. The ripple voltage generated at the output
capacitor (ESR) is used as a PWM ramp signal. This ripple is
used to trigger the on-time of the controller.
TON
VIN
VLX
CIN
Q1
VFB
VLX
VOUT
L
Q2
FB Threshold
One-Shot Timer and Operating Frequency
One-shot timer operation is shown in Figure 2. The FB
Comparator output goes high when VFB is less than the
internal 750mV reference. This feeds into the gate drive
and turns on the high-side MOSFET, and starts the oneshot timer. The one-shot timer uses an internal comparator and a capacitor. One comparator input is connected to
VOUT, the other input is connected to the capacitor. When
the on-time begins, the internal capacitor charges from
zero volts through a current which is proportional to VIN.
When the capacitor voltage reaches VOUT, the on-time is
completed and the high-side MOSFET turns off.
ESR
FB Comparator
FB
+
Predictable operating frequency compared to
other variable frequency methods.
Reduced component count by eliminating the
error amplifier and compensation components.
Reduced component count by removing the
need to sense and control inductor current.
Fast transient response — the response time is
controlled by a fast comparator instead of a typically slow error amplifier.
Reduced output capacitance due to fast transient response
FB
750mV
RTON
Figure 1 — PWM Control Method, VOUT Ripple
VIN
+
COUT
VOUT
VIN
Gate
Drives
One-Shot
Timer
DH
Q1
VLX
DL
Q2
VOUT
L
ESR
COUT
FB
+
On-time = K x RTON x (VOUT/VIN)
Figure 2 — On-Time Generation
14
SC414/SC424
Applications Information (continued)
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN.
Under steady-state conditions, the switching frequency
can be determined from the on-time by the following
equation.
fSW
VOUT
TON u VIN
The SC414/SC424 uses an external resistor to set the ontime which indirectly sets the frequency. The on-time can
be programmed to provide an operating frequency from
200kHz to 1MHz using a resistor between the TON pin and
ground. The resistor value is selected by the following
equation.
RTON
RTON
Note that when VIN > (V5V - 1.6V) x 10 , the actual on-time
is fixed and does not vary with VIN. When operating in this
condition, the switching frequency will vary inversely with
VIN rather than approximating a fixed frequency.
VOUT Voltage Selection
The switcher output voltage is regulated by comparing
VOUT as seen through a resistor divider at the FB pin to the
internal 750mV reference voltage (see Figure 3).
VOUT
R2
The maximum RTON value allowed is shown by the following equation.
RTON _ MAX
Immediately after the on-time, the DL (drive signal for the
low side FET) output drives high to turn on the low-side
MOSFET. DL has a minimum high time of ~320ns, after
which DL continues to stay high until one of the following
occurs:
•
•
VFB falls below the 750mV reference
The Zero Cross Detector senses that the voltage
on the LX node is below ground. Power Save is
activated when a zero crossing is detected.
TON limitations and V5V Supply Voltage
For V5V below 4.5V, the TON accuracy may be limited by
the input voltage.
The original RTON equation is accurate if VIN satisfies the
below relation over the entire VIN range:
VIN < (V5V - 1.6V) x 10
If VIN exceeds (V5V - 1.6V) x 10, for all or part of the VIN
range, the RTON equation is not accurate. In all cases
where VIN > (V5V - 1.6V) x 10, the RTON equation must be
modified as follows.
To FB pin
R1
1
V
400: u IN
25pF u fSW
VOUT
VIN _ MIN
10 u 1.5PA
1
(V5V 1.6V) u 10
400: u
25pF u fSW
VOUT
Figure 3 — Output Voltage Selection
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is offset by the output ripple according to the
following equation.
VOUT
§ R · §V
·
0.75 u ¨¨1 1 ¸¸ ¨ RIPPLE ¸
R
2
©
¹
2 ¹
©
When a large capacitor is placed in parallel with R1 (C TOP)
VOUT is shown by the following equation.
VOUT
§ R · §V
·
0.75 u ¨¨1 1 ¸¸ ¨ RIPPLE ¸ u
© R2 ¹ © 2 ¹
1 (R1ZCTOP )2
§ R u R1
·
1 ¨¨ 2
ZCTOP ¸¸
© R 2 R1
¹
2
Where ω is the angular switching frequency.
Enable and Power-save Inputs
The EN/PSV and ENL inputs are used to enable or disable
the switching regulator and the LDO. When EN/PSV is low
(grounded), the switching regulator is off and in its lowest
power state. When off, the output of the switching regulator soft-discharges the output into a 10Ω internal resistor
via the VOUT pin. When EN/PSV is allowed to float, the pin
voltage will float to 33% of the voltage at V5V. The switching regulator turns on with power-save disabled and all
switching is in forced continuous mode. For V5V < 4.5V, it
15
SC414/SC424
Applications Information (continued)
is recommended to force 33% of the V5V voltage on the
EN/PSV pin to operate in forced continuous mode.
FB Ripple
Voltage (VFB)
When EN/PSV is high (above 45% of the voltage at V5V)
for SC414, the switching regulator turns on with ultrasonic
power-save enabled. The SC414 ultrasonic power-save
operation maintains a minimum switching frequency of
25kH z, for applications with stringent audio
requirements.
Inductor
Current
When EN/PSV is high (above 45% of the voltage at V5V)
for SC424, the switching regulator turns on with powersave enabled. The SC424 power-save operation is designed
to maximize efficiency at light loads with no minimum
frequency limits. This makes the SC424 an excellent choice
for portable and battery-operated systems.
The ENL input is used to control the internal LDO. This
input provides a second function by acting as a VIN ULVO
sensor for the switching regulator. When ENL is low
(grounded), the LDO is off. When ENL is a logic high but
below the VIN UVLO threshold (2.6V typical), then the LDO
is on and the switcher is off. When ENL is above the VIN
UVLO threshold, the LDO is enabled and the switcher is
also enabled if the EN/PSV pin is not grounded.
Forced Continuous Mode Operation
The SC414/SC424 operates the switcher in Forced
Continuous Mode (FCM) by floating the EN/PSV pin (see
Figure 4). In this mode of operation, the MOSFETs are
turned on alternately to each other with a short dead time
between them to avoid cross conduction. This feature
results in uniform frequency across the full load range
with the trade-off being poor efficiency at light loads due
to the high-frequency switching of the MOSFETs.
For V5V < 4.5V, it is recommended to force 33% of the V5V
voltage on the EN/PSV pin to operate in forced continuous
mode.
FB threshold
(750mV)
DC Load Current
On-time
(TON)
DH on-time is triggered when
VFB reaches the FB Threshold.
DH
DL
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
Figure 4 — Forced Continuous Mode Operation
Ultrasonic Power-save Operation (SC414)
The SC414 provides ultrasonic power-save operation at
light loads, with the minimum operating frequency fixed
at slightly under 25kHz. This is accomplished by using an
internal timer that monitors the time between consecutive high-side gate pulses. If the time exceeds 40μs, DL
drives high to turn the low-side MOSFET on. This draws
current from VOUT through the inductor, forcing both VOUT
and VFB to fall. When VFB drops to the 750mV threshold, the
next DH (the drive signal for the high side FET) on-time is
triggered. After the on-time is completed the high-side
MOSFET is turned off and the low-side MOSFET turns on.
The low-side MOSFET remains on until the inductor
current ramps down to zero, at which point the low-side
MOSFET is turned off.
16
SC414/SC424
Applications Information (continued)
Because the on-times are forced to occur at intervals no
greater than 40μs, the frequency will not fall far below
25kHz. Figure 5 shows ultrasonic power-save operation.
FB Ripple
Voltage
(VFB)
Dead time varies
according to load
FB threshold
(750mV)
minimum fSW ~ 25kHz
Inductor
Current
FB Ripple
Voltage (VFB)
Zero (0A)
FB threshold
(750mV)
On-time (TON)
(0A)
Inductor
Current
DH On-time is triggered when
VFB reaches the FB Threshold.
DH
On-time
(TON)
DH On-time is triggered when
VFB reaches the FB Threshold
DH
DL
DL drives high when on-time is completed.
DL remains high until inductor current reaches zero.
40μs time-out
Figure 6 — Power-save Operation
DL
After the 40μsec time-out, DL drives high if VFB
has not reached the FB threshold.
Figure 5 — Ultrasonic Power-save Operation
Power-save Mode Operation (SC424)
The SC424 provides power-save operation at light loads
with no minimum operating frequency. With power-save
enabled, the internal zero crossing comparator monitors
the inductor current via the voltage across the low-side
MOSFET during the off-time. If the inductor current falls to
zero for 8 consecutive switching cycles, the controller
enters power-save operation. It will turn off the low-side
MOSFET on each subsequent cycle provided that the
current crosses zero. At this time both MOSFETs remain
off until VFB drops to the 750mV threshold. Because the
MOSFETs are off, the load is supplied by the output capacitor. If the inductor current does not reach zero on any
switching cycle, the controller immediately exits powersave and returns to forced continuous mode. Figure 6
shows power-save operation at light loads.
Smart Power-save Protection
Active loads may leak current from a higher voltage into
the switcher output. Under light load conditions with
power-save enabled, this can force VOUT to slowly rise and
reach the over-voltage threshold, resulting in a hard shutdown. Smart power-save prevents this condition. When
the FB voltage exceeds 10% above nominal (exceeds
825mV), the device immediately disables power-save, and
DL drives high to turn on the low-side MOSFET. This draws
current from VOUT through the inductor and causes VOUT to
fall. When VFB drops back to the 750mV trip point, a normal
TON switching cycle begins. This method prevents a hard
OVP shutdown and also cycles energy from VOUT back to
VIN. It also minimizes operating power by avoiding forced
conduction mode operation. Figure 7 shows typical waveforms for the Smart Power-save feature.
SmartDriveTM
For each DH pulse, the DH driver initially turns on the
high-side MOSFET at a slower speed, allowing a softer,
smooth turn-off of the low-side diode. Once the DH node
is high and the LX voltage has risen 1V above PGND, the
SmartDrive circuit automatically drives the high-side
MOSFET on at a rapid rate. This technique reduces ringing
while maintaining high efficiency and also avoids the
need for snubbers or series resistors in the gate drive.
17
SC414/SC424
VOUT drifts up to due to leakage
current flowing into COUT
Smart Power Save
Threshold (825mV)
VOUT discharges via inductor
and low-side MOSFET
Normal VOUT ripple
FB
threshold
DH and DL off
High-side
Drive (DH)
Inductor Current
Applications Information (continued)
IPEAK
ILOAD
ILIM
Time
Single DH on-time pulse
after DL turn-off
Figure 8 — Valley Current Limit
Low-side
Drive (DL)
DL turns on when Smart
PSAVE threshold is reached
Normal DL pulse after DH
on-time pulse
DL turns off when FB
threshold is reached
Figure 7 — Smart Power-save
Current Limit Protection
The device features programmable current limiting, which
is accomplished by using the RDSON of the lower MOSFET
for current sensing. The current limit is set by RILIM resistor.
The RILIM resistor connects from the ILIM pin to the LXS pin
which is also the drain of the low-side MOSFET. When the
low-side MOSFET is on, an internal ~8μA current flows
from the ILIM pin and through the RILIM resistor, creating a
voltage drop across the resistor. While the low-side
MOSFET is on, the inductor current flows through it and
creates a voltage across the RDSON. The voltage across the
MOSFET is negative with respect to ground. If this MOSFET
voltage drop exceeds the voltage across RILIM, the voltage
at the ILIM pin will be negative and current limit will activate. The current limit then keeps the low-side MOSFET on
and will not allow another high-side on-time, until the
current in the low-side MOSFET reduces enough to bring
the ILIM voltage to zero. This method regulates the inductor valley current at the level shown by ILIM in Figure 8.
Setting the valley current limit to 6A results in a peak
inductor current of 6A plus peak ripple current. In this situation, the average (load) current through the inductor is
6A plus one-half the peak-to-peak ripple current.
The internal 8μA current source is temperature compensated at 4100ppm in order to provide tracking with the
RDSON.
The RILIM value is calculated by the following equation.
RILIM = 1250 x ILIM x [0.088 x (5V - V5V) + 1]
When selecting a value for RILIM do not exceed the absolute
maximum voltage value for the ILIM pin. Note that because
the low-side MOSFET with low RDSON is used for current
sensing, the PCB layout, solder connections, and PCB connection to the LX node must be done carefully to obtain
good results. RILIM should be connected directly to LXS
(pin 24).
Soft-Start of PWM Regulator
Soft-start is achieved in the PWM regulator by using an
internal voltage ramp as the reference for the FB comparator. The voltage ramp is generated using an internal
charge pump which drives the reference from zero to
750mV in ~1.8mV increments, using an internal ~500kHz
oscillator. When the ramp voltage reaches 750mV, the
ramp is ignored and the FB comparator switches over to a
fixed 750mV threshold. During soft-start the output
voltage tracks the internal ramp, which limits the start-up
inrush current and provides a controlled soft-start profile
for a wide range of applications. Typical soft-start ramp
time is 1.7ms.
18
SC414/SC424
Applications Information (continued)
During soft-start the regulator turns off the low-side
MOSFET on any cycle if the inductor current falls to zero.
This prevents negative inductor current, allowing the
device to start into a pre-biased output. This soft start
operation is implemented even if FCM is selected. FCM
operation is allowed only after PGOOD is high.
Power Good Output
The power good (PGOOD) output is an open-drain output
which requires a pull-up resistor. When the output voltage
is 10% below the nominal voltage, PGOOD is pulled low. It
is held low until the output voltage returns to the nominal
voltage. PGOOD is held low during start-up and will not
be allowed to transition high until soft-start is completed
(when VFB reaches 750mV) and typically 4ms has passed.
PGOOD will transition low if the VFB pin exceeds +20% of
nominal, which is also the over-voltage shutdown threshold (900mV). PGOOD also pulls low if the EN/PSV pin is
low when V5V is present.
then begins a soft-start cycle. The PWM will shut off if V5V
falls below 2.7V.
LDO Regulator
The device features an integrated LDO regulator with a
fixed output voltage of 5V. There is also an enable pin
(ENL) for the LDO that provides independent control. The
LDO voltage can also be used to provide the bias voltage
for the switching regulator.
A minimum capacitance of 1μF referenced to AGND is
normally required at the output of the LDO for stability. If
the LDO is providing bias power to the device, then a
minimum 0.1μF capacitor referenced to AGND is required,
along with a minimum 1μF capacitor referenced to PGND
to filter the gate drive pulses. Refer to the layout guidelines section.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
Output Over-Voltage Protection
Over-Voltage Protection (OVP) becomes active as soon as
the device is enabled. The threshold is set at 750mV + 20%
(900mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off, until the EN/PSV input
is toggled or V5V is cycled. There is a 5μs delay built into
the OVP detector to prevent false transitions. PGOOD is
also low after an OVP event.
Output Under-Voltage Protection
When VFB falls to 75% of its nominal voltage (falls to
562.5mV) for eight consecutive clock cycles, the switcher
is shut off and the DH and DL drives are pulled low to turn
off the MOSFETs. The controller stays off until EN/PSV is
toggled or V5V is cycled.
1. ENL pin
2. VLDO output
3. VIN input voltage
When the ENL pin is high, the LDO will begin start-up, see
Figure 10. During the initial phase, when the LDO output
voltage is near zero, the LDO initiates a current-limited
start-up (typically 85mA) to charge the output capacitor.
When VLDO has reached 90% of the final value, the LDO
current limit is increased to ~200mA and the LDO output
is quickly driven to the nominal value by the internal LDO
regulator.
VVLDO Final
90% of VVLDO Final
Voltage regulating with
~200mA current limit
V5V UVLO, and POR
Under-Voltage Lock-Out (UVLO) circuitry inhibits switching and tri-states the DH/DL drivers until V5V rises above
2.9V. An internal Power-On Reset (POR) occurs when V5V
exceeds 2.9V, which resets the fault latch and soft-start
counter to begin the soft-start cycle. The SC414/SC424
Constant current startup
Figure 10 — LDO Start-Up
19
SC414/SC424
Applications Information (continued)
LDO Switch-Over Operation
Switch-over MOSFET Parasitic Diodes
The SC414/SC424 includes a switch-over function for the
LDO. The switch-over function is designed to increase
efficiency by using the more efficient DC-DC converter to
power the LDO output, avoiding the less efficient LDO
regulator when possible. The switch-over function connects the VLDO pin directly to the VOUT pin using an
internal switch. When the switch-over is complete the
LDO is turned off, which results in a power savings and
maximizes efficiency. If the LDO output is used to bias the
SC414/SC424, then after switch-over the device is selfpowered from the switching regulator with the LDO
turned off.
The switch-over MOSFET contains parasitic diodes that
are inherent to its construction, as shown in Figure 11.
The switch-over logic waits for 32 switching cycles before
it starts the switch-over. There are two methods that
determine the switch-over of VLDO to VOUT.
In the first method, the LDO is already in regulation and
the DC-DC converter is later enabled. As soon as the
PGOOD output goes high, the 32 cycle counter is started.
The voltages at the VLDO and VOUT pins are then compared; if the two voltages are within ±300mV (typically) of
each other, within 32 cylces, the VLDO pin connects to the
VOUT pin using an internal switch, and the LDO is turned
off.
Switchover
control
Switchover
MOSFET
VOUT
VLDO
Parasitic diode
Parasitic diode
V5V
Figure 11— Switch-over MOSFET Parasitic Diodes
There are some important design rules that must be followed to prevent forward bias of these diodes. The following two conditions need to be satisfied in order for the
parasitic diodes to stay off.
•
•
V5V ≥ VLDO
V5V ≥ VOUT
If either VLDO or VOUT is higher than V5V, then the respective
diode will turn on and the SC414/SC424 operating current
will flow through this diode. This has the potential of
damaging the device.
In the second method, the DC-DC converter is already
running and the LDO is enabled. In this case the 32 cycles
are started as soon as the LDO reaches 90% of its final
value. At this time, the VLDO and VOUT pins are compared,
and if within ±300mV (typically) the switch-over occurs
and the LDO is turned off.
The ENL pin also acts as the switcher under-voltage
lockout for the VIN supply. The VIN UVLO voltage is programmable via a resistor divider at the VIN, ENL, and AGND
pins.
Switch-over Limitations on VOUT and VLDO
ENL is the enable/disable signal for the LDO. In order to
implement the VIN UVLO there is also a timing requirement
that needs to be satisfied.
Because the internal switch-over circuit always compares
the VOUT and VLDO pins at start-up, there are voltage
limitations on permissible combinations of these pins.
Consider the situation where VOUT is programmed to 4.7V.
After start-up, the device would connect VOUT to VLDO
and disable the LDO, since the two voltage are within the
±300mV switch-over window. To avoid unwanted switchover, the minimum difference between the voltages for
VOUT and VLDO should be ±500mV.
ENL pin and VIN UVLO
If the ENL pin transitions low within 2 switching cycles and
is < 1V, then the LDO will turn off but the switcher remains
on. If ENL goes below the VIN UVLO threshold and stays
above 1V, then the switcher will turn off but the LDO
remains on.
The VIN UVLO function has a typical threshold of 2.6V on
the VIN rising edge. The falling edge threshold is 2.4V.
20
SC414/SC424
Applications Information (continued)
Note that it is possible to operate the switcher with the
LDO disabled, but the ENL pin must be below the logic
low threshold (0.4V maximum). The table below summarizes the function of the ENL and EN pins, with respect to
the rising edge of ENL.
signal. If PGOOD is high, then the switcher is already
running and the LDO will run through the start-up cycle
without affecting the switcher. If PGOOD is low, then the
LDO will not allow any PWM switching until the LDO
output has reached 90% of it’s final value.
EN
ENL
LDO status
Switcher status
Using the On-chip LDO to Bias the SC414/SC424
low
high
low
high
low
high
low, < 0.4V
low, < 0.4V
high, < 2.6V
high, < 2.6V
high, > 2.6V
high, > 2.6V
off
off
on
on
on
on
off
on
off
off
off
on
The following steps must be followed when using the
internal LDO to bias the device.
•
•
•
Figure 12 below shows the ENL voltage thresholds and
their effect on LDO and Switcher operation.
ENL voltage
LDO on
Switcher on if EN = high
2.6V
2.4V
ENL low
threshold
(min 0.4V)
AGND
VIN UVLO hysteresis
LDO on
Switcher off by VIN UVLO
LDO off
Switcher on if EN = high
Figure 12 — ENL Thresholds
ENL Logic Control of PWM Operation
When the ENL input is driven above 2.6V, it is impossible to
determine if the LDO output is going to be used to power
the device or not. In self-powered operation where the
LDO will power the device, it is necessary during the LDO
start-up to hold the PWM switching off until the LDO has
reached 90% of the final value. This prevents overloading
the current-limited LDO output during the LDO start-up.
However, if the switcher was previously operating (with
EN/PSV high but ENL at ground, and V5V supplied externally), then it is undesirable to shut down the switcher. To
prevent this, when the ENL input is above 2.6V (above the
VIN UVLO threshold), the internal logic checks the PGOOD
Connect V5V to VLDO before enabling the LDO.
Any external load on VLDO should not exceed
40mA until the LDO voltage has reached 90% of
final value.
Do not connect the EN pin directly to the V5V or
any other supply voltage if Vout is greater than
or equal to 4.5V
Many applications connect the EN pin to V5V and control
the on/off of the LDO and PWM simultaneously with the
ENL pin. This allows one signal to control both the bias
and power output of the SC414. When VOUT > 4.5V this
configuration can cause problems due to the parasitic
diodes in the LDO switchover circuitry. After the Vout >
4.5V PWM output is up and running the switchover diodes
can hold up V5V > UVLO even if the ENL pin is grounded,
turning off the LDO. Operating in this way can potentially
damage the part.
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor
ripple current must be specified.
The maximum input voltage (VINMAX) is the highest specified input voltage. The minimum input voltage ( VINMIN) is
determined by the lowest input voltage after evaluating
the voltage drops due to connectors, fuses, switches, and
PCB traces.
The following parameters define the design.
•
•
•
•
Nominal output voltage (VOUT )
Static or DC output tolerance
Transient response
Maximum load current (IOUT )
21
SC414/SC424
Applications Information (continued)
There are two values of load current to evaluate — continuous load current and peak load current. Continuous
load current relates to thermal stresses which drive the
selection of the inductor and input capacitors. Peak load
current determines instantaneous component stresses and
filtering requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
The following values are used in this design.
•
•
•
•
VIN = 12V + 10%
VOUT = 1V + 4%
fSW = 250kHz
Load = 6A maximum
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the
power conversion efficiency.
The desired switching frequency is 250kHz which results
from using components selected for optimum size and
cost .
A resistor (RTON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
RTON
1
V
400: u IN
25pF u fSW
VOUT
To select RTON, use the maximum value for VIN, and for TON
use the value associated with maximum VIN.
T ON
V OUT
V INMAX u f SW
TON = 303 ns at 13.2VIN, 1VOUT, 250kHz
Substituting for RTON results in the following solution.
RTON = 130.9kΩ, use RTON = 130kΩ
Inductor Selection
In order to determine the inductance, the ripple current
must first be defined. Low inductor values result in smaller
size but create higher ripple current which can reduce
efficiency. Higher inductor values will reduce the ripple
current/voltage and for a given DC resistance are more
efficient. However, larger inductance translates directly
into larger packages and higher cost. Cost, size, output
ripple, and efficiency are all used in the selection process.
The ripple current will also set the boundary for powersave operation. The switching will typically enter powersave mode when the load current decreases to 1/2 of the
ripple current. For example, if ripple current is 4A then
Power-save operation will typically start for loads less than
2A. If ripple current is set at 40% of maximum load current,
then power-save will start for loads less than 20% of
maximum current.
The inductor value is typically selected to provide a ripple
current that is between 25% to 50% of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
During the DH on-time, voltage across the inductor is
(VIN - VOUT ). The equation for determining inductance is
shown next.
L
( VIN VOUT ) u TON
IRIPPLE
Example
In this example, the inductor ripple current is set equal to
50% of the maximum load current. Therefore ripple
current will be 50% x 6A or 3A. To find the minimum
inductance needed, use the VIN and TON values that correspond to VINMAX.
L
(13.2V 1V ) u 318ns
3A
1.26PH
A slightly larger value of 1.5μH is selected. This will
decrease the maximum IRIPPLE to 2.53A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
TON _ VINMIN
25pF u R TON u VOUT
10ns
VINMIN
311ns
22
SC414/SC424
Applications Information (continued)
IRIPPLE
Assuming a peak voltage VPEAK of 1.150 (100mV rise upon
load release), and a 6A load release, the required capacitance is shown by the next equation.
( VIN VOUT ) u TON
L
IRIPPLE _ VINMIN
(10.8 1V ) u 311ns
1.5PH
2.03 A
Capacitor Selection
The output capacitors are chosen based on required ESR
and capacitance. The maximum ESR requirement is controlled by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. Change in the output ripple voltage will lead to a
change in DC voltage at the output.
The design goal is for the output voltage regulation to be
±4% under static conditions. The internal 750mV reference tolerance is 1%. Assuming a 1% tolerance from the
FB resistor divider, this allows 2% tolerance due to VOUT
ripple. Since this 2% error comes from 1/2 of the ripple
voltage, the allowable ripple is 4%, or 40mV for a 1V
output.
The maximum ripple current of 2.53A creates a ripple
voltage across the ESR. The maximum ESR value allowed
is shown by the following equations.
ESRMAX
VRIPPLE
IRIPPLEMAX
40mV
2.53 A
2
1.05 V 1V 2
COUTMIN = 772μF
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 750mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately
-VOUT. This causes a down-slope or falling di/dt in the
inductor. If the load di/dt is not much faster than the
-di/dt in the inductor, then the inductor current will tend
to track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor, therefore a smaller capacitance can be used.
The following can be used to calculate the needed capacitance for a given dILOAD/dt. Peak inductor current is shown
by the next equation.
ILPK = IMAX + 1/2 x IRIPPLEMAX
ILPK = 6A + 1/2 x 2.53A = 7.26A
ESRMAX = 15.8 mΩ
Rate of change of Load Current
The output capacitance is chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor
current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes
from maximum to zero in < 1μs), the output capacitor
must absorb all the inductor’s stored energy. This will
cause a peak voltage on the capacitor according to the
following equation.
COUTMIN
COUTMIN
1
§
·2
1.5PH¨ 6 A u 2.53 A ¸
2
©
¹
dlLOAD
dt
IMAX = maximum load release = 6A
Lu
COUT
ILPK u
ILPK
I
MAX u dt
VOUT dlLOAD
2VPK VOUT Example
dlLOAD
dt
1.25 A
1Ps
1
§
·2
L¨ IOUT u IRIPPLEMAX ¸
2
©
¹
2
VPEAK VOUT 2
23
SC414/SC424
Applications Information (continued)
This causes the output current to move from 6A to 0A in
4.8μs, giving the minimum output capacitance requirement shown in the following equation.
COUT
7.26 A u
COUT
443PF
CTOP
7.26 A
6A
u 1Ps
1V
1.25 A
21.05 V 1V VOUT
1.5PH u
Note that COUT is much smaller in this example, 443μF
compared to 772μF based on a worst-case load release. To
meet the two design criteria of minimum 443μF and
maximum 15mΩ ESR, select two capacitors rated at 220μF
and 15mΩ ESR or less.
It is recommended that an additional small capacitor be
placed in parallel with COUT in order to filter high frequency
switching noise.
To FB pin
R1
R2
Figure 13 — Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
Stability Considerations
Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or
ESR loop instability.
One simple way to solve this problem is to add trace resistance in the high current output path. A side effect of
adding trace resistance is a decrease in load regulation.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
minimum off-time has expired. In extreme cases the noise
can cause three or more successive on-times. Doublepulsing will result in higher ripple voltage at the output,
but in most applications it will not affect operation. This
form of instability can usually be avoided by providing the
FB pin with a smooth, clean ripple signal that is at least
10mVp-p, which may dictate the need to increase the ESR
of the output capacitors. It is also imperative to provide a
proper PCB layout as discussed in the Layout Guidelines
section.
ESR Requirements
Another way to eliminate doubling-pulsing is to add a
small (~ 10pF) capacitor across the upper feedback resistor, as shown in Figure 13. This capacitor should be left
unpopulated unless it can be confirmed that doublepulsing exists. Adding the CTOP capacitor will couple more
ripple into FB to help eliminate the problem. An optional
connection on the PCB should be available for this
capacitor.
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and discharging during the switching cycle. For most applications, the total output ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching frequency. The formula for minimum ESR is shown by the
following equation.
ESR MIN
3
2 u S u C OUT u f sw
24
SC414/SC424
Applications Information (continued)
Using Ceramic Output Capacitors
When applications use ceramic output capacitors, the ESR
is normally too small to meet the previously stated ESR
criteria. In these applications it is necessary to add a small
virtual ESR network composed of two capacitors and one
resistor, as shown in Figure 14. This network creates a
ramp voltage across CL, analogous to the ramp voltage
generated across the ESR of a standard capacitor. This
ramp is then capacitively coupled into the FB pin via
capacitor CC.
L
Highside
Lowside
RL
CL
The on-time pulse from the SC414/SC424 in the design
example is calculated to give a pseudo-fixed frequency of
250kHz. Some frequency variation with line and load is
expected. This variation changes the output ripple
voltage. Because constant on-time converters regulate to
the valley of the output ripple, ½ of the output ripple
appears as a DC regulation error. For example, if the
output ripple is 50mV with VIN = 6 volts, then the measured
DC output will be 25mV above the comparator trip point.
If the ripple increases to 80mV with VIN = 25V, then the
measured DC output will be 40mV above the comparator
trip. The best way to minimize this effect is to minimize
the output ripple.
R1
CC
COUT
FB
pin
R2
Figure 14 — Virtual ESR Ramp Current
Output Voltage Dropout
The output voltage adjustable range for continuous-conduction operation is limited by the fixed 320ns (typical)
minimum off-time. When working with low input voltages, the duty-factor limit must be calculated using worstcase values for on and off times.
The duty-factor limitation is shown by the next equation.
DUTY
comparator offset is trimmed so that under static conditions it trips when the feedback pin is 750mV, 1%.
TON(MIN)
TON(MIN) TOFF(MIN)
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy — VOUT Controller
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at
full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps
are reduced as seen at the load.
The use of 1% feedback resistors may result in up to an
additional 1% error. If tighter DC accuracy is required,
resistors with lower tolerances should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor effect on the DC output voltage. The output ESR
also affects the output ripple and thus has a minor effect
on the DC output voltage.
Switching Frequency Variations
The switching frequency will vary depending on line and
load conditions. The line variations are a result of fixed
propagation delays in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
VIN increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net effect is
that frequency tends to falls slightly with increasing input
voltage.
25
SC414/SC424
Applications Information (continued)
The switching frequency also varies with load current as a
result of the power losses in the MOSFETs and the inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. A constant on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing
energy from VIN as losses increase). The on-time is essentially constant for a given VOUT and VIN combination, to
offset the losses the off-time will tend to reduce slightly as
load increases. The net effect is that switching frequency
increases slightly with increasing load.
lator with a maximum current of 6A. The total PCB area is
approximately 20 x 25 mm.
PCB Layout Guidelines
IC Decoupling Capacitors
A 0.1 μF capacitor must be located as close as
possible to the IC and directly connected to pins
2 (V5V) and 3 (AGND).
The optimum layout for the SC414/SC424 is shown in
Figure 15. This layout shows an integrated FET buck regu-
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
•
•
•
•
•
•
IC Decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
BST, ILIM, and LX
Capacitors and Current Loops
•
RES_GND — AGND connects
to PGND close to SC414/SC424
AGND plane on
inner layer
RILIM
All components
shown Top Side
RFB1
Pin 1 marking
SC414/SC424 with
vias for LX, AGND,
VIN
RFB2
CFF
PGND
CBST
CIN
VIN plane on inner
or bottom layer
COUT
VOUT Plane
on Top layer
L
PGND on inner
or bottom layer
LX plane on inner
or bottom layer
Note: This figure is not
to scale
Figure 15 — PCB Layout
26
SC414/SC424
Applications Information (continued)
•
All other decoupling capacitors must be located
as close as possible to the IC.
PGND Plane
PGND requires its own copper plane with no
other signal traces routed on it.
Copper planes, multiple vias, and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the IC.
The PGND copper area between the input
capacitors, output capacitors, and PGND pins
must be as small as and as compact as possible
to reduce the area of the PCB that is exposed to
noise due to current flow on this node.
Connect PGND to AGND with a short trace or
0Ω resistor. This connection should be as close
to the IC as possible.
•
•
•
•
•
•
AGND Island
AGND should have its own island of copper with
no other signal traces routed on this layer that
connects the AGND pins and pad of the IC to the
analog control components.
All of the components for the analog control circuitry should be located so that the connections
to AGND are done by wide copper traces or vias
down to AGND.
Connect PGND to AGND with a short trace or 0Ω
resistor. This connection should be as close to
the IC as possible.
•
•
•
FB, VOUT, and Other Analog Control Signals
The connection from the V OUT power to the
analog control circuitry must be routed from the
output capacitors and located on a quiet layer.
The traces between VOUT and the analog control
circuitry (VOUT, and FB pins) must be short and
routed away from noise sources, such as BST, LX,
VIN, and PGND between the input capacitors,
output capacitors, and the IC.
ILIM and TON nodes must be as short as possible
to ensure the best accuracy in current limit and
on time.
•
•
RILIM should be close to the IC and connected to
LXS with a Kelvin trace to pin 24 on the IC. This
will be a sufficient connection and will prevent
the need to connect the resistor further into the
LX plane.
The feedback components for the switcher need
to be as close to the FB pin of the IC as possible
to reduce the possibility of noise corrupting
these analog signals.
BST, ILIM and LX
LX and BST are very noisy nodes and must be
carefully routed to minimized the PCB area that
is exposed to these signals.
The connections for the boost capacitor
between the IC and LX must be short and directly
connected to the LXBST (pin 12).
The connections for the current limit resistor
between the ILIM pin and LX must be as short as
possible and directly connected to pin 24 (LXS).
The LX node between the IC and the inductor
should be wide enough to handle the inductor
current and short enough to eliminate the possibility of LX noise corrupting other signals.
Multiple vias should be used to provide a good
connection to LX between the IC and the
inductor.
•
•
•
•
•
Capacitors and Current Loops
The current loops between the input capacitors,
the IC, the inductor, and the output capacitors
must be as close as possible to each other to
reduce IR drop across the copper.
All bypass and output capacitors must be connected as close as possible to the respective pin
on the IC.
•
•
•
27
SC414/SC424
Outline Drawing — MLPQ-4x4-28
A
B
D
DIMENSIONS
DIM
PIN 1
INDICATOR
(LASER MARK)
E
A1
A2
A
aaa
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
MILLIMETERS
MIN
0.80
0.00
0.17
3.90
0.96
3.90
2.48
NOM
-
MAX
1.00
0.05
-
(0.20)
0.23 0.29
4.00 4.10
1.06
1.16
4.00 4.10
2.58 2.68
0.45 BSC
0.30 0.40 0.50
28
0.08
0.10
SEATING
PLANE
C
C
2.58
1.29
D1
LxN
e
0.73±0.10
1.29
E1
1.45±0.10
2
1
E/2
N
R 0.20
PIN 1
IDENTIFICATION
bxN
D1
bbb
C
A
B
D/2
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
28
SC414/SC424
Land Pattern — MLPQ-4x4-28
1.29
K
X
DIMENSIONS
1.29
H2
(C)
H
G
Z
H1
Y
P
DIM
MILLIMETERS
C
(3.95)
G
3.20
H
2.58
H1
0.73
H2
1.45
K
1.06
P
0.45
X
0.30
Y
0.75
Z
4.70
K
2.58
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3.
SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
29