Preliminary AN1022 Interfacing GSI Sync SRAMs to a Freescale MPC5554 microcontroller Introduction Interface This application note will discuss interfacing a Freescale MPC5554 microcontroller with GSI Syncronous Burst SRAMs. Figure 1 shows the basic connection between an MPC5554 and a GSI SRAM. The FT pin controls whether the SRAM operates in Pipeline mode or Flow Through mode. This pin needs to be tied to VSS if the MPC is operating in a zero wait state Read Mode which is also referred to as Flow Through mode in the SRAM datasheet. The FT pin will need to be tied to VDD if the MPC is operating in a one wait state Read Mode, which is also refered to as Pipline mode in the SRAM datasheet. Compatibility The Freescale MPC5554 is capable of interfacing with SRAMs that operate in either Flow Through or Pipeline mode, which is selectable by the addition of wait states in the MPC5554 read timing. The SRAMs must operate in a Late Write mode, where the data and byte writes are supplied one cycle after the write command is loaded. All of GSI’s Synchronous Burst SRAMs are compatible with the Freescale MPC5554. The MPC5554 microcontroller uses a Late Write protocol when perfroming L2 cache writes. This requires the design to use the ADSP pin to configure the SRAM to utilize a Late Write protocol. Figure 1: Connection diagram Freescale MPC5554 GSI Syncronous SRAM ADDR[8:31] VDD for Pipeline mode A BDIP ADV TS FT ADSP CLKOUT CK RDWR BW VSS for Flow Through mode GW E1 CSx WE[0:3] BA–BD DATA[0:31] DQ[0:31] Rev: 1.00 6/2005 E2 E3 LBO G OE VDD ADSC 1/5 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. VSS © 2005, GSI Technology Preliminary AN1022 Timing Analysis For all of the following timing diagrams, the GSI pin names are displayed on the left next to the MPC pin names. Figure 2 is a timing diagram for L2 cache write. As seen in Figure 2, the addresses and ADSP signals are supplied on the first rising edge of clock for the beginnning of the write cycle and the write enable, byte writes, and data signals are supplied on the following rising edge of clock. Figure 2: L2 cache write SRAM MPC5554 CK A CLKout ADDR[8:31] BW A RDWR 00 TSIZ[0:1] ADV ADSP DQ BDIP TS Data[0:31] A TA E1 CSx BA–BD WE Rev: 1.00 6/2005 A 2/5 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary AN1022 Figure 3 illustrates a flow through read which is also referenced as a zero wait state read. When the SRAM operates in Flow Through mode, the read command is clocked in and data is referenced to the same rising edge of clock. Figure 3: Flow Through Mode or Zero Wait State Read SRAM MPC5554 CK A BW CLKout ADDR[8:31] A RDWR 00 TSIZ[0:1] ADV BDIP ADSP TS DQ Data[0:31] A TA E1 CSx G OE Rev: 1.00 6/2005 3/5 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary AN1022 Figure 4 illustrates a flow through read cycle followed by a write cycle. One thing to notice is the required deslect cycle that is added between the read cycle and the write cycle. The deselect cycle is nessecary to allow the SRAM to get off the bus and the MPC to begin driving. If this cycle is omitted, there will be bus contention and it is possible that the MPC will not latch in correct data. Figure 4: Flow Through Read Deselect Write Read A Deselect Write B Deselect SRAM MPC5554 CK A BW CLKout ADDR[8:31] A B RDWR 00 TSIZ[0:1] ADV ADSP DQ BDIP TS Data[0:31] A B TA E1 CSx G OE BA–BD WE Rev: 1.00 6/2005 B 4/5 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology Preliminary AN1022 Figure 5 illustrates a pipeline read which is also referneced as a one wait state read. The read address is supplied on the rising edge of clock. On the next rising edge of the clock, data is driven out from the SRAM. The data is referenced to the second rising edge of clock. Figure 5: Pipeline Read or One Wait State Read SRAM MPC5554 CK A CLKout ADDR[8:31] BW A RDWR 00 TSIZ[0:1] ADV BDIP ADSP DQ TS Data[0:31] A TA E1 CSx G OE Summary The Freescale MPC5554 Microcontroller will interface with GSI Synchronous Burst SRAMs that are configured to operate in either Pipeline or Flow Through mode. The timing diagrams in this document bridged the gap between those provided in the Freescale documentation referencing the microcontroller signal names and GSI Synchronous Burst SRAM signal names. A designer using this document as a guide should be able to properly configure the interface to work with GSI Synchronous BurstRAM devices. If further questions still exist, please feel free to contact GSI Application Engineers at [email protected]. Rev: 1.00 6/2005 5/5 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2005, GSI Technology