VSP2000 ® VSP2 000 CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS TM FEATURES DESCRIPTION ● CCD SIGNAL PROCESSING Correlated Double Sampling Black Level Clamping 0 to +34dB Gain Ranging High SNR: 53dB The VSP2000 is a complete digital camera IC, providing signal conditioning and 10-bit analog-to-digital conversion for the output of a CCD array. The primary CCD channel provides correlated double sampling to extract the video information from the pixels, 0dB to +34dB gain range with analog control for varying illumination conditions, and black level clamping for an accurate black reference. The stable gain control is linear in dB. Additionally, the black level is quickly recovered after gain changes. The VSP2000 is available in a 48-lead LQFP package and operates from a single +3V supply. ● 10-BIT A/D CONVERSION Up to 18MHz Conversion Rate No Missing Codes ● PORTABLE OPERATION Low Voltage: Down to 2.7V Low Power: 150mW at 2.7V APPLICATIONS ● VIDEO CAMERAS ● DIGITAL STILL CAMERAS ● PC CAMERAS ● SECURITY CAMERAS REFCK DATCK OB AGC1 AGC2 ADCK C Black Level Auto-Zero A/D Timing Control CCD D T/H +28dB Clamp T/H CCD R VCA +6dB 10-Bit 18MHz A/D Output Latch 10-Bit Digital Output T/H REF Dummy Pixel Auto-Zero DUMC International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1997 Burr-Brown Corporation 1 PDS-1432A VSP2000 Printed in U.S.A. April, 1998 SPECIFICATIONS At TA = +25°C, AVDD = AVDD2 = +3.0V, DVDD = DVDD1 = DRVDD = +3.0V, unless otherwise specified. VSP2000 PARAMETER DIGITAL INPUT Logic Family Logic Levels CONDITIONS MIN Logic HI Logic LO Logic HI, VIN = +VDD Logic LO, VIN = 0V +VDD /2 0 TYP MAX UNITS +VDD +0.4 10 10 V V µA µA % +VDD +0.4 V V CMOS Logic Currents A/D Clock Duty Cycle 50 DIGITAL OUTPUT Logic Family Logic Levels TRANSFER CHARACTERISTICS Resolution Differential Non-Linearity Integral Non-Linearity No Missing Codes Signal Settling Time CMOS Logic HI, CI = 10pF Logic LO, CI = 10pF +VDD –0.5 0 10 ±0.4 ±2.0 Guaranteed Black to Full Scale Change to 1/4 LSB into ADS Conversion Rate Data Latency Signal-to-Noise Ratio(1) Black Clamp Level CDS Data Settling Time to +0.1% for FS Change with RS = 40 Input Capacitance Input Time Constant Data Full Scale Input From Leading Edge of DATCK DATCK Low After AC Coupling Cap VCA CHARACTERISTICS Gain Control Voltage Range Gain at Max Control Voltage Gain Control Linearity Gain Control Settling Time Transfer Function 0.3 32 +2.7 3V Supply 3V Supply 2.7V Supply Power Down Mode TEMPERATURE RANGE Specified Range Thermal Resistance, θJA 48-Lead LQFP ns 18 5.5 53 MHz Clocks dB 32 LSB 11 ns 20 300 pF ps mV 3.3 1 kΩ V 600 INPUT CLAMP Clamp on Resistance Clamp Level POWER SUPPLY Rated Voltage Current, Quiescent Power Dissipation 110 500kHz Grounded Input Cap, VCA Gain Max Ambient Bit LSB LSB 2.4 V dB dB µs dB / V +3.3 V mA mW mW mW +85 °C 34 ±1.0 10 18 +3.0 60 180 150 24 –25 100 °C/W NOTE: (1) SNR = 20log (Full Scale Voltage /rms Noise). The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® VSP2000 2 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS +VS ....................................................................................................... +6V Analog Input ......................................................... (0 –0.3V) to (+VS +0.3V) Logic Input ........................................................... (0 –0.3V) to (+VS +0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. PACKAGE/ORDERING INFORMATION PRODUCT VSP2000 PACKAGE PACKAGE DRAWING NUMBER(1) TEMPERATURE RANGE 48-Lead LQFP 340 –40°C to +85°C ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. REFP REFN AVSS5 AVSS4 AVDD5 AVDD4 AVDD DVSS AVDD3 AVDD2 CM 2.4V PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 DVSS1 1 36 INT BIAS1 B10 (LSB) 2 35 AVSS B9 3 34 INT BIAS2 B8 4 33 AVDD1 B7 5 32 LCM B6 6 31 AVSS3 VSP2000 B5 7 B4 8 30 AGC2 29 AGC1 B3 9 28 AVSS2 B2 10 27 CCD R B1 (MSB) 11 26 CCD D 18 19 DVSS3 ADCK DVDD1 PD PB 20 21 22 23 24 C 17 DUMC 16 DATCK 15 REFCK 14 OB 13 DVSS2 25 AVSS1 DRVSS DRVDD 12 PIN DESCRIPTIONS PIN DESIGNATOR DESCRIPTION PIN DESIGNATOR DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DVSS1 B10 (LSB) B9 B8 B7 B6 B5 B4 B3 B2 B1 (MSB) DRVDD DRVSS DVSS2 DVSS3 ADCK DVDD1 PD PB OB REFCK DATCK DUMC C AVSS1 CCD D Digital Ground LSB of ADS Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 MSB of ADS Digital +Supply of ADS Output Digital Ground for ADS Output Digital Ground Digital Ground ADS Clock, Data Output on Falling Edge Digital +Supply L = Normal Operation, H = Reduced Power L = –FS + 32 LSB, H = Normal at CCD Mode Optical Black Clamp Pulse, Active LOW Neg Pulse, Trailing Edge Samples Reset Neg Pulse, Trailing Edge Samples Data Dummy Clamp, Active LOW Capacitor for Optical Feedback Analog Ground CCD Signal Input 27 28 29 30 31 32 33 34 CCD R AVSS2 AGC1 AGC2 AVSS3 LCM AVDD1 INT BIAS 2 35 36 AVSS INT BIAS 1 37 38 39 40 41 42 43 44 45 46 47 48 2.4V CM AVDD2 AVDD3 DVSS AVDD AVDD4 AVDD5 AVSS4 AVSS5 REFN REFP Capacitor for Dummy Feedback Loop Analog Ground Sets Gain of CCD Channel, 1kΩ Resistor Sets Gain of CCD Channel, 16kΩ Resistor Analog Ground Attenuator Common-Mode Bypass Analog +Supply Internal Bias, should be connected to GND with 0.1µF Capacitor Analog Ground Internal Bias, should be connected to GND with 0.1µF Capacitor Attenuator Ladder Bypass ADS Common-Mode Voltage Analog +Supply Analog +Supply Digital Ground Analog +Supply Analog +Supply Analog +Supply Analog Ground Analog Ground ADS –Reference, Bypass to Ground ADS +Reference, Bypass to Ground ® 3 VSP2000 TIMING DIAGRAMS 9.5MHz 0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns 106 RESET 56 HI CCD OUT REFCK 26 132 44 80 DATCK 26 151 96 79 132 ADCK 19 OB DUMC 159 24 127 81 OUTPUT DATA 167 93 DATA VALID DATA VALID 14MHz 0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns RESET 39 HI CCD OUT REFCK 21 37 DATCK 54 69 56 21 91 161 ADCK 28 OB 69 168 208 DUMC 33 –7 OUTPUT DATA 60.6 136 68.6 DATA VALID ® VSP2000 176 DATA VALID 4 TIMING DIAGRAMS (CONT) 18MHz 0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns RESET 27.7 55.5 HI CCD OUT REFCK 18 32 DATCK 46 60 18 ADCK OB 24 64 DUMC 50 OUTPUT DATA 58 DATA VALID DATA VALID DATA VALID ADCK OUTPUT TIMING t0 REFCK t2 t1 DATCK t3 A/D CLOCK (Internal) t4 t5 A/D DATA OUT (Internal) t6 ADCK t7 OUTPUT DATA SYMBOL PARAMETER MIN t0 t1 t2 t3 t4 t5 t6 t7 ADCK Clock Period REFCK Pulse Width DATCK Pulse Width DATCK Delay A/D Clock Delay (Internal) A/D Data Out Delay (Internal) ADCK Delay Output Data Delay 55.6 27 26 1.5 –25 7.1 TYP 14 14 28 28 2.0 0 8.3 MAX UNITS 29 30 2.5 25 9.5 ns ns ns ns ns ns ns ns NOTE: Timing Specifications = TMIN to TMAX with DRVDD = 3.0V, ADVDD = 3.0V, DVDD = 3.0V. 18MHz timing shown for reference. ® 5 VSP2000 TYPICAL PERFORMANCE CURVES At TA = +25°C, AVDD = AVDD2 = +3.0V, DVDD = DVDD1 = DRVDD1 = +3.0V, unless otherwise specified. VCA CHARACTERISTICS QUIESCENT CURRENT vs POWER SUPPLY 40 100 35 Quiescent Current (mA) 30 Gain (dB) 25 20 15 10 5 0 80 60 40 20 –5 0 –10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 2.7 AGC Input (V) ® VSP2000 3.0 Power Supply Voltage (V) 6 3.3 CORRELATED DOUBLE SAMPLER (CDS) THEORY OF OPERATION The CDS removes low frequency noise from the output of the image sensor. Refer to Figure 2 which shows a block diagram of the CDS. The output from the CCD array is sampled during the reference interval as well as during the data interval. Noise that is present at the input and is of a period greater than the pixel interval will be eliminated by subtraction. The VSP2000 is an integrated circuit that contains many of the key features associated with the processing of analog signals in a video camera or digital still camera. Figure 1 shows a simplified block diagram of the VSP2000. The output from the CCD array is first sent to a correlated double sampler (CDS), a voltage-controlled attenuator with a logarithmic control characteristic, and an output amplifier prior to being applied to the input of a 10-bit analog-todigital converter. The VSP2000 employs a three track/hold correlated double sampler architecture. Track/Hold 2 is sampled during the reference interval by the REFCK signal. Track/Hold 3 is resampled at the same time that the data Track/Hold 1 is sampled by the DATCK signal. This is done to remove large transients from Track/Hold 2 that results from a portion of the reset transient being present during the acquisition time of this track and hold. The output of Track/Hold 2 is buffered by a voltage follower. Two calibration cycles are employed to reduce the offset variation of the VSP2000. During the dummy pixel time, an input auto-zero circuit is activated that eliminates the offset of the correlated double sampler. During the optical black timing interval, another auto-zero circuit is employed to eliminate the offset associated with the output amplifier and the remaining offset from the CDS. Black Level Auto-Zero Loop Dummy Feedback Loop DUMC ADCK OB CDS CCD Input 10-Bit 18MHz A/D VCA Digital Output Output Amplifier Clamp Gain Control REFCK DATCK FIGURE 1. Simplified Block Diagram of VSP2000. Data Sampling Channel CCD Input T/H1 To VCA Reference Sampling Channel T/H3 T/H2 1V DUMC REFCK DATCK FIGURE 2. Block Diagram of Correlated Double Sampler. ® 7 VSP2000 DIFFERENCE AMPLIFIER The effective time constant of this loop is given by: The correlated double sampler function is completed when the output of the data and reference channel are sent to the difference amplifier where the signals are subtracted. In addition to providing the difference function, the difference amplifier amplifies the signal by a factor of 2 which helps to improve the overall signal-to-noise ratio. The difference amplifier also generates a differential signal to drive the voltage-controlled attenuator. T= where R is 10kΩ, C is an external capacitor connected to pin 27 (CCD R), A is the gain of the error amplifier with a value of 50, and D is the duty cycle of the time that the dummy pixel auto-zero loop is in operation. The duty cycle (D) must be considered as the loop operates in a sampled mode. Operation of the dummy auto-zero loop is activated by the DUMC signal that happens once during each horizontal line interval. INPUT CLAMP The output from the CCD array is capacitively coupled to the VSP2000. To prevent shifts in the DC level from taking place due to varying input duty cycles, the input capacitor is clamped during the dummy pixel interval by the REFCK signal. A P-channel transistor is used for this input clamp switch to be able to allow a 2V negative change at the input that would bring the signal below ground by 1. Under typical conditions, the bias at the input to the VSP2000 is at 1V. TIMING The REFCK and DATCK signals are used to operate the CDS as previously explained. These same two signals are also used by internal timing circuitry to create the necessary timing signals for the A/D. The output from the A/D is read out to external circuitry by the ADCK signal. DUMC is used to activate the dummy pixel auto-zero loop and OB is used to activate the black level auto-zero loop. The input digital timing signals REFCK, DATCK, DUMC and OB are capable of being driven from either 3V or 5V logic levels. DUMMY PIXEL AUTO-ZERO LOOP The output from the data and reference channel is processed by the previously mentioned difference amplifier. The differential output from the difference amplifier is sent to both the voltage-controlled logarithmic attenuator and to an error amplifier. The error amplifier amplifies and feeds a signal to the difference amplifier to drive the offset measured at the output of the difference amplifier to zero. A block diagram of this circuit is shown in Figure 3. This error amplifier serves the purpose of reducing the offset of the CDS to avoid a large offset from being amplified by the output amplifier. VOLTAGE-CONTROLLED ATTENUATOR To maximize the dynamic range of the VSP2000, a voltagecontrolled attenuator is included with a control range from 0dB to –34dB. The gain control has a logarithmic relationship between the control voltage and the attenuation. The attenuator processes a differential signal from the difference amplifier to improve linearity and to reject both power supply and common-mode noise. The output from the attenuator is amplified by 28dB prior to being applied to the A/D. A typical gain control characteristic of the VSP2000 is shown in the typical performance curve, “VCA Characteristics”. AGC1 is a coarse gain control and AGC2 is a fine gain control. Figure 4 shows how the gain control signals are applied. To VCA CCD Input RC AD CDS 1kΩ A To Internal Gain Control Circuits Error Amplifier R CCD R AGC1 16kΩ C FIGURE 4. Gain Control Resistors. DUMCK FIGURE 3. Block Diagram of Dummy Pixel Loop. ® VSP2000 8 AGC2 BLACK LEVEL AUTO-ZERO LOOP A/D CONVERTER The black level auto-zero loop amplifies the difference between the output of the output amplifier and a reference signal during the dummy pixel interval. This difference signal is amplified and fed back into the output amplifier to correct the offset. In doing so, the output level of the entire CCD channel can be controlled to be approximately –FS + 32LSBs under zero signal conditions. The black level autozero loop is activated by the OB timing signal. The A/D converter utilizes a pipline architecture. The fully differential topology and digital error correction guarantee 10-bit resolution. The A/D converter circuitry includes a reference circuit that provides bias voltages for the entire system. Figure 5 shows a block diagram of the black level auto-zero loop. The loop time constant is given by: The VSP2000 has several supply pins, one of which is dedicated to supply only the digital output driver (pin 17, DVDD1). The remaining supply pins are not, as is often the case, divided into analog and digital supply pins since they are internally connected on the chip. For this reason, it is recommended that the VSP2000 be treated as an analog component and to power if from the analog supply only. Digital supply lines often carry high levels of wide band noise which can couple back into the VSP2000 and limit performance. T= DECOUPLING AND GROUNDING CONSIDERATIONS C (GM) (D) where C is the external filter capacitance applied to pin 24 (C), GM is .001Ω and D is the duty cycle of the time that the black level auto-zero loop is in operation. The duty cycle (D) must be considered as the loop operates in a sampled mode. Operation of the black level auto-zero loop is activated by the OB signal that happens once during each horizontal line interval. From VCA Figure 6 shows the recommended decoupling scheme for the VSP2000. In most cases, 0.1µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual pin. Therefore, they should be located as close as possible to the pins. In addition, one larger capacitor (1µF to 22µF) should be placed on the PC board in proximity of the VSP2000. To ADS 32LSB GM DEMONSTRATION BOARD Error Amplifier A demonstration board, DEM-VSP2000, is available to assist in the inital evaluation of the circuit performance using the VSP2000. The schematic and board layout of the DEM-VSP2000 are shown in Figure 6 and Figures 7a through 7d, respectively. C C OB FIGURE 5. Black Level Auto-Zero Loop. ® 9 VSP2000 R7 270Ω P2 1kΩ R6 270Ω P1 1kΩ JP8 R5 130Ω C14 0.1µF R4 130Ω C13 0.1µF C7 0.1µF TP1 C4 0.1µF TP3 JP3 C6 0.1µF 1 2 FIGURE 6. Evaluation Board Layout Detail. VCC R1 50Ω 2 1 TP2 1 R3 10kΩ TP7 JP5 24 23 22 21 20 19 18 17 16 15 14 13 TP5 TP6 R2 10kΩ 36 INT BIAS1 35 AVSS 34 INT BIAS2 33 AVDD1 32 LCM 31 AVSS3 30 AGC2 29 AGC1 VSP2000 C8 0.1µF C11 0.1µF C10 0.1µF 37 38 39 40 41 42 43 44 45 46 47 48 C9 0.1µF 1 4 B8 DVSS1 5 B7 2 6 B6 3 7 B5 B9 8 B4 B10 (LSB) 9 B3 B2 10 27 CCD R 28 AVSS2 DRVDD 12 B1 (MSB) 11 26 CCD D U3 25 AVSS1 1 2 VCC C5 0.1µF C12 0.1µF TP4 JP4 DUMC CM 2 DATCK AVDD2 C 2.4V C3 0.1µF JP2 OB DVSS 1 PD 2 PB AVDD 10 AVDD4 BNC1 CCD D JP1 BNC6 PB DVDD1 AVDD5 BNC5 OB ADCK AVSS4 BNC4 RCK DVSS3 AVSS5 BNC3 DCK REFCK AVDD3 DRVSS BNC2 DUMC DVSS2 REFN VSP2000 REFP ® C15 0.1µF C16 10µF CN1 1 VCC 2 1 1 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 R8 1kΩ JP6 5 4 3 2 2 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 OB2 VDD IDT74FCT541 GND A8 A7 A6 A5 A4 A3 A2 A1 OB1 U3 C2 0.1µF IDT74FCT541 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 OB2 VDD C1 0.1µF U2 GND A8 A7 A6 A5 A4 A3 A2 A1 OB1 JP7 11 12 13 14 15 16 17 18 19 20 11 12 13 14 15 16 17 18 19 20 C17 10µF 6 8 5 7 22 24 26 23 25 39 37 35 33 31 29 40 38 36 34 32 30 28 20 21 27 18 19 16 17 14 15 12 13 11 10 4 3 9 2 1 Header 20x2 CN2 BNC7 ADCCK FIGURE 7a. Evaluation Board Silkscreen (top). FIGURE 7b. Evaluation Board Layout. ® 11 VSP2000 FPO FIGURE 7c. Top Layer. FIGURE 7d. Bottom Layer. ® VSP2000 12