GS84018/32/36AGT/B*-180/166/150/100 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipelined mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 119-bump BGA package (NRND) • RoHS-compliant 100-lead TQFP and 119-bump BGA packages me nd ed for Ne w Applications The GS84018/32/36A is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS84018/32/36A is available in a JEDEC standard 100-lead TQFP or 119-Bump BGA package. No t Re co m Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated Rev: 1.21 5/2014 Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the BGA). Holding the FT mode pin/bump low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register. SCD Pipelined Reads The GS84018/32/36A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. De sig Functional Description internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. ct Features 180 MHz–100 MHz 3.3 V VDD 3.3 V and 2.5 V I/O n— Di sco nt inu ed Pr od u TQFP, BGA Commercial Temp Industrial Temp Byte Write and Global Write Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS84018/32/36A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit. Parameter Synopsis –180 –166 –150 –100 10 ns tCycle 5.5 ns 6.0 ns 6.6 ns Pipeline 3.0 ns 3.5 ns 3.8 ns 4.5 ns tKQ 3-1-1-1 IDD 335 mA 310 mA 280 mA 190 mA tKQ 8 ns 8.5 ns 10 ns 12 ns Flow 10 ns 12 ns 15 ns Through tCycle 9 ns 2-1-1-1 IDD 210 mA 190 mA 165 mA 135 mA 1/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 No t De sig Ne w Re co LBO m A VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC me nd ed for VDDQ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A NC NC NC n— Di sco nt inu ed Pr od u ct A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS84018A 100-Pin TQFP Pinout (Package T) Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.21 5/2014 2/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 n— Di sco nt inu ed Pr od u ct A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS84032A 100-Pin TQFP Pinout (Package T) Ne w me nd ed for NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A Re co LBO m A No t VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 De sig NC DQC DQC VDDQ Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.21 5/2014 3/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 n— Di sco nt inu ed Pr od u ct A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS84036A 100-Pin TQFP Pinout (Package T) Ne w me nd ed for DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A Re co LBO m A No t VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 De sig DQPC DQC DQC VDDQ Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.21 5/2014 4/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 TQFP Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs BA In Byte Write signal for data inputs DQA; active low BB In Byte Write signal for data inputs DQB; active low BC In Byte Write signal for data inputs DQC; active low BD In Byte Write signal for data inputs DQD; active low BW I Byte Write—Writes all enabled bytes; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I G I ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low DQA I/O Byte A Data Input and Output pins DQB I/O DQ I/O DQD I/O DQPA I/O DQPB I/O DQPC I/O DQPD I/O ZZ I FT I LBO I VDD I VSS I n— Di sco nt inu ed Pr od u ct Symbol Chip Enable; active high Output Enable; active low De sig Byte B Data Input and Output pins Byte C Data Input and Output pins me nd ed for Ne w Byte D Data Input and Output pins 9th Data I/O Pin; Byte C Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground I Output driver power supply - No Connect No t NC 9th Data I/O Pin; Byte B 9th Data I/O Pin; Byte D Re co m VDDQ 9th Data I/O Pin; Byte A Rev: 1.21 5/2014 5/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 GS84018A Pad Out—119-Bump BGA—Top View (Package B) 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC E2 A ADSC A E3 NC C NC A A VDD A A NC D DQB NC VSS NC VSS DQPA NC E NC DQB VSS E1 VSS NC DQA F VDDQ NC VSS G VSS DQA VDDQ G NC DQB BB ADV NC NC DQA H DQB NC VSS GW VSS DQA NC J VDDQ VDD VDD NC VDD VDDQ K NC L DQB n— Di sco nt inu ed Pr od u De sig Ne w VSS CK VSS NC DQA NC NC NC BA DQA NC VDDQ DQB VSS BW VSS NC VDDQ DQB NC VSS A1 VSS DQA NC NC DQPB VSS A0 VSS NC DQA R NC A LBO VDD FT A NC T NC A A NC A A ZZ VDDQ NC NC NC NC NC VDDQ N No t Re co m P me nd ed for DQB M U Rev: 1.21 5/2014 NC ct 1 6/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 GS84032A Pad Out—119-Bump BGA—Top View (Package B) 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC E2 A ADSC A E3 NC C NC A A VDD A A NC D DQC NC VSS NC VSS NC DQB E DQC DQC VSS E1 VSS DQB DQB F VDDQ DQC VSS G VSS DQB VDDQ G DQC DQC BC ADV BB DQB DQB H DQC DQC VSS GW VSS DQB DQB J VDDQ VDD VDD NC VDD VDDQ K DQD L DQD n— Di sco nt inu ed Pr od u De sig Ne w VSS CK VSS DQA DQA DQD BD NC BA DQA DQA VDDQ DQD VSS BW VSS DQA VDDQ DQD DQD VSS A1 VSS DQA DQA DQD NC VSS A0 VSS NC DQA R NC A LBO VDD FT A NC T NC NC A A A NC ZZ VDDQ NC NC NC NC NC VDDQ N No t Re co m P me nd ed for DQD M U Rev: 1.21 5/2014 NC ct 1 7/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 GS84036A Pad Out—119-Bump BGA—Top View (Package B) 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC E2 A ADSC A E3 NC C NC A A VDD A A NC D DQC DQPC VSS NC VSS DQPB DQB E DQC DQC VSS E1 VSS DQB DQB F VDDQ DQC VSS G VSS DQB VDDQ G DQC2 DQC BC ADV BB DQB DQB2 H DQC DQC VSS GW VSS DQB DQB J VDDQ VDD VDD NC VDD VDDQ K DQD L DQD n— Di sco nt inu ed Pr od u De sig Ne w VSS CK VSS DQA DQA DQD BD NC BA DQA DQA VDDQ DQD VSS BW VSS DQA VDDQ DQD DQD VSS A1 VSS DQA DQA DQD DQPD VSS A0 VSS DQPA DQA R NC A LBO VDD FT A NC T NC NC A A A NC ZZ VDDQ NC NC NC NC NC VDDQ N No t Re co m P me nd ed for DQD M U Rev: 1.21 5/2014 NC ct 1 8/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 BGA Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs A I Address Inputs BA In Byte Write signal for data inputs DQA; active low BB In Byte Write signal for data inputs DQB; active low BC In Byte Write signal for data inputs DQC; active low BD In Byte Write signal for data inputs DQD; active low CK I Clock Input Signal; active high BW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I G I ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low DQA I/O Byte A Data Input and Output pins DQB I/O Byte B Data Input and Output pins DQ I/O DQD I/O DQPA I/O DQPB I/O DQPC I/O DQPD I/O ZZ I FT I LBO I VDD I VSS I n— Di sco nt inu ed Pr od u ct Symbol Chip Enable; active high De sig Output Enable; active low Byte C Data Input and Output pins me nd ed for Ne w Byte D Data Input and Output pins 9th Data I/O Pin; Byte C Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground I Output driver power supply - No Connect No t NC 9th Data I/O Pin; Byte B 9th Data I/O Pin; Byte D Re co m VDDQ 9th Data I/O Pin; Byte A Rev: 1.21 5/2014 9/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 GS84018/32/36A Block Diagram Register D Q A0 A0 D0 Q0 A1 ct A0–An A1 n— Di sco nt inu ed Pr od u D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q Register GW BW BA D Q Register D D 36 Q BB 36 D Ne w D Q Register BD Q Register D De sig Q BC Q Register D Register 4 Register me nd ed for D Q Register E1 E3 E2 D Q Register FT G 1 Power Down No t ZZ Q Re co m D DQxn–DQxn Control Note: Only x36 version shown for simplicity. Rev: 1.21 5/2014 10/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Mode Pin Functions Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H Interleaved Burst L Flow Through ct Pin Name H or NC Pipeline n— Di sco nt inu ed Pr od u Mode Name L or NC Active H Standby, IDD = ISB Note: There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 Ne w A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. No t Re co m me nd ed for Note: The burst counter wraps to initial state on the 5th clock. De sig A[1:0] Rev: 1.21 5/2014 11/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Byte Write Truth Table GW BW BA BB BC BD Notes Read H H X X X X 1 Write No Bytes H L H H H Write byte a H L L Write byte b H L H Write byte c H L H Write byte d H L H Write all bytes H L L ct Function n— Di sco nt inu ed Pr od u H 1 H H H 2, 3 L H H 2, 3 H L H 2, 3, 4 H H L 2, 3, 4 L L L 2, 3, 4 No t Re co m me nd ed for Ne w De sig Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.21 5/2014 12/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Synchronous Truth Table Address Used State Diagram Key E1 E2 E3 ADSP ADSC ADV W DQ3 Deselect Cycle, Power Down None X L X H X L X X High-Z Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X H Read Cycle, Begin Burst External R L Read Cycle, Begin Burst External R L Write Cycle, Begin Burst External W L Read Cycle, Continue Burst Next CR X Read Cycle, Continue Burst Next CR H Write Cycle, Continue Burst Next CW X Write Cycle, Continue Burst Next CW H Read Cycle, Suspend Burst Current X Read Cycle, Suspend Burst Current Write Cycle, Suspend Burst Current Write Cycle, Suspend Burst Current n— Di sco nt inu ed Pr od u ct Operation X X L X X High-Z X H L X X X High-Z L X L X X X High-Z X X X L X X High-Z H L L X X X Q H L H L X F Q H L H L X T D X X H H L F Q X X X H L F Q X X H H L T D X X X H L T D X X H H H F Q H X X X H H F Q X X X H H H T D X X X H H T D Ne w De sig L H No t Re co m me nd ed for Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.21 5/2014 13/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Simplified State Diagram ct X W R R R First Write CR De sig CW Ne w W First Read X CR R R X Burst Write me nd ed for Simple Burst Synchronous Operation Simple Synchronous Operation W X n— Di sco nt inu ed Pr od u Deselect Burst Read X CR CW CR No t Re co m Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.21 5/2014 14/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Simplified State Diagram with G ct X W R W X n— Di sco nt inu ed Pr od u Deselect R R First Write CR First Read CW X CR W Burst Write me nd ed for X Ne w De sig CW W R CR CW R W Burst Read X CW CR No t Re co m Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.21 5/2014 15/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Absolute Maximum Ratings (All voltages reference to VSS) Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to 4.6 VI/O Voltage on I/O Pins VIN Voltage on Other Input Pins IIN Input Current on Any Pin IOUT Output Current on Any I/O Pin PD Package Power Dissipation TSTG Storage Temperature TBIAS Temperature Under Bias n— Di sco nt inu ed Pr od u ct Symbol V –0.5 to VDDQ +0.5 ( 4.6 V max.) V –0.5 to VDD +0.5 ( 4.6 V max.) V +/–20 mA +/–20 mA 1.5 W –55 to 125 o –55 to 125 o C C De sig Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage VDD 3.3 3.6 V VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V me nd ed for 3.0 3.3 V VDDQ I/O Supply Voltage Ne w Parameter Notes No t Re co m Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.21 5/2014 16/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Logic Levels Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 2.0 — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.8 V 1 VDDQ3 I/O Input High Voltage VIHQ3 2.0 — VDDQ + 0.3 V 1,3 VDDQ3 I/O Input Low Voltage VILQ3 –0.3 — 0.8 V 1,3 VDDQ2 I/O Input High Voltage VIHQ2 0.6*VDD — VDDQ + 0.3 V 1,3 VDDQ2 I/O Input Low Voltage VILQ2 –0.3 — 0.3*VDD V 1,3 n— Di sco nt inu ed Pr od u ct Parameter Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Symbol Ambient Temperature (Commercial Range Versions) TA Ambient Temperature (Industrial Range Versions) TA Min. Typ. Max. Unit Notes 0 25 70 C 2 –40 25 85 C 2 De sig Parameter me nd ed for Ne w Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Undershoot Measurement and Timing 50% tKC VDD + 2.0 V Re co m VIH Overshoot Measurement and Timing VSS 50% VSS – 2.0 V 50% VDD 50% tKC No t VIL Rev: 1.21 5/2014 17/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 pF Ne w De sig Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. n— Di sco nt inu ed Pr od u Note: These parameters are sample tested. ct Parameter Output Load 1 me nd ed for DQ 50 30pF* No t Re co m VDDQ/2 * Distributed Test Jig Capacitance Rev: 1.21 5/2014 18/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 DC Electrical Characteristics Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IIN1 VDD VIN VIH 0 V VIN VIH Output Leakage Current IOL Output High Voltage VOH2 Output High Voltage VOH3 Output Low Voltage VOL ct Parameter 1 uA 100 uA Output Disable, VOUT = 0 to VDD –1 uA 1 uA IOH = –8 mA, VDDQ = 2.375 V 1.7 V — IOH = –8 mA, VDDQ = 3.135 V 2.4 V — IOL = 8 mA — 0.4 V n— Di sco nt inu ed Pr od u –1 uA –1 uA Operating Currents -166 -150 -100 –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C Unit IDD Pipeline 335 345 310 320 280 290 190 200 mA IDD Flow Through 210 220 190 200 165 175 135 145 mA ISB Pipeline 20 30 20 30 20 30 20 30 mA 30 20 30 20 30 20 30 mA Parameter Test Conditions Symbol Operating Current Device Selected; All other inputs VIH or VIL Output open Standby Current ZZ VDD – 0.2 V Deselect Current Device Deselected; All other inputs VIH or VIL 20 me nd ed for ISB Flow Through Ne w 0 to 70°C De sig -180 55 65 50 60 50 60 40 50 mA IDD Flow Through 40 50 40 50 35 45 35 45 mA No t Re co m IDD Pipeline Rev: 1.21 5/2014 19/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 AC Electrical Characteristics Clock Cycle Time -180 -166 -150 -100 Max Min Max Min Max tKC 5.5 — 6.0 — 6.7 — Clock to Output Valid tKQ — 3.0 — 3.5 Clock to Output Invalid tKQX 1.5 — 1.5 Clock to Output in Low-Z 1 tLZ 1.5 — Clock Cycle Time tKC 9.0 Clock to Output Valid tKQ Clock to Output Invalid Min n— Di sco nt inu ed Pr od u ct Min Max Unit 10 — ns 3.8 — 4.5 ns — — 1.5 — 1.5 — ns 1.5 — 1.5 — 1.5 — ns — 10.0 — 12.0 — 15.0 — ns — 8.0 — 8.5 — 10.0 — 12.0 ns tKQX 3.0 — 3.0 — 3.0 — 3.0 — ns Clock to Output in Low-Z tLZ1 3.0 — 3.0 — 3.0 — 3.0 — ns Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — ns Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in High-Z tHZ1 1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns G to Output Valid tOE 3.2 — 3.5 — 3.8 — 5 ns G to output in Low-Z tOLZ 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 3.2 — 3.5 — 3.8 — 5 ns Setup time tS 1.5 — 1.5 — 1.5 — 2.0 — ns Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — ns 20 — 20 — 20 — 20 — ns ZZ recovery De sig — 1 Ne w Flow Through Symbol me nd ed for Pipeline Parameter tZZR No t Re co m Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.21 5/2014 20/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Pipeline Mode Timing Cont Cont Deselect Write B Single Read Read C+1 Read C+2 Read C+3 Cont Single Write tKL tKH tKC CK ADSP tS tH Deselect Burst Read ADSC initiated read ADSC tS tH ADV tS tH A0–An Read C ct Read A n— Di sco nt inu ed Pr od u Begin A B tS GW tS C tH De sig BW tH tS tS tH E1 tH E2 tS tH E3 Re co m G me nd ed for tS E1 masks ADSP E2 and E3 only sampled with ADSP and ADSC tOE tS tOHZ Q(A) tKQ tH D(B) tKQX tLZ tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) No t DQa–DQd Deselected with E1 Ne w Ba–Bd Rev: 1.21 5/2014 21/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Flow Through Mode Timing Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect tKL tKC ct tKH n— Di sco nt inu ed Pr od u CK ADSP Fixed High tS tH tS tH initiated read ADSC ADSC tS tH ADV tS tH A0–An A B C tS tH tS tH BW Ba–Bd tS E1 tS tH E2 tS tH E3 E2 and E3 only sampled with ADSC Re co m G tH tS tOE tOHZ Q(A) D(B) tKQ tLZ tHZ tKQX Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) No t DQa–DQd Deselected with E1 me nd ed for tH Ne w tS tH De sig GW Rev: 1.21 5/2014 22/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Sleep Mode Timing Diagram tKH tKC tKL CK ADSP ADSC n— Di sco nt inu ed Pr od u ct Setup Hold tZZR tZZS ZZ Application Tips tZZH No t Re co m me nd ed for Ne w De sig Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. Rev: 1.21 5/2014 23/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity Lead Angle ct A1 n— Di sco nt inu ed Pr od u Description e b A1 0.10 A2 — 7 E1 E No t Re co m me nd ed for Ne w Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. De sig Y 0 D D1 Symbol Pin 1 TQFP Package Drawing (Package GT) L c L1 Min. Nom. Max Rev: 1.21 5/2014 24/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Package Dimensions—119-Bump FPBGA (Package B, Variation 2) TOP VIEW 2 3 4 5 6 7 7 6 5 4 3 2 1 20.32 De sig 22±0.10 1.27 A B C D E F G H J K L M N P R T U ct 1 BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x) n— Di sco nt inu ed Pr od u A1 A B C D E F G H J K L M N P R T U 1.27 7.62 A 0.20(4x) 14±0.10 SEATING PLANE No t Re co m C 0.50~0.70 1.86.±0.13 me nd ed for 0.15 C Ne w B Rev: 1.21 5/2014 25/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Ordering Information for GSI Synchronous Burst RAMs TA3 180/8 C RoHS-compliant TQFP 166/8.5 C RoHS-compliant TQFP 150/10 C RoHS-compliant TQFP 100/12 C RoHS-compliant TQFP 180/8 C RoHS-compliant TQFP 166/8.5 C RoHS-compliant TQFP 150/10 C RoHS-compliant TQFP 100/12 C RoHS-compliant TQFP 180/8 C RoHS-compliant TQFP 166/8.5 C RoHS-compliant TQFP 150/10 C RoHS-compliant TQFP 100/12 C RoHS-compliant TQFP 180/8 I RoHS-compliant TQFP 166/8.5 I Pipeline/Flow Through RoHS-compliant TQFP 150/10 I GS84018AGT-100I Pipeline/Flow Through RoHS-compliant TQFP 100/12 I 128K x 32 GS84032AGT-180I Pipeline/Flow Through RoHS-compliant TQFP 180/8 I 128K x 32 GS84032AGT-166I Pipeline/Flow Through RoHS-compliant TQFP 166/8.5 I 128K x 32 GS84032AGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/10 I 128K x 32 GS84032AGT-100I Pipeline/Flow Through RoHS-compliant TQFP 100/12 I 128K x 36 GS84036AGT-180I Pipeline/Flow Through RoHS-compliant TQFP 180/8 I 128K x 36 GS84036AGT-166I Pipeline/Flow Through RoHS-compliant TQFP 166/8.5 I 128K x 36 GS84036AGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/10 I 128K x 36 GS84036AGT-100I Pipeline/Flow Through RoHS-compliant TQFP 100/12 I 256K x 18 GS84018AB-180 Pipeline/Flow Through 119 BGA (var. 1) 180/8 C 256K x 18 GS84018AB-166 Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 C 256K x 18 GS84018AB-150 Pipeline/Flow Through 119 BGA (var. 1) 150/10 C 256K x 18 GS84018AB-100 Pipeline/Flow Through 119 BGA (var. 1) 100/12 C 128K x 32 GS84032AB-180 Pipeline/Flow Through 119 BGA (var. 1) 180/8 C Type Package 256K x 18 GS84018AGT-180 Pipeline/Flow Through RoHS-compliant TQFP 256K x 18 GS84018AGT-166 Pipeline/Flow Through 256K x 18 GS84018AGT-150 Pipeline/Flow Through 256K x 18 GS84018AGT-100 Pipeline/Flow Through 128K x 32 GS84032AGT-180 Pipeline/Flow Through 128K x 32 GS84032AGT-166 Pipeline/Flow Through 128K x 32 GS84032AGT-150 Pipeline/Flow Through 128K x 32 GS84032AGT-100 Pipeline/Flow Through 128K x 36 GS84036AGT-180 Pipeline/Flow Through 128K x 36 GS84036AGT-166 Pipeline/Flow Through 128K x 36 GS84036AGT-150 Pipeline/Flow Through 128K x 36 GS84036AGT-100 Pipeline/Flow Through 256K x 18 GS84018AGT-180I Pipeline/Flow Through 256K x 18 GS84018AGT-166I Pipeline/Flow Through 256K x 18 GS84018AGT-150I 256K x 18 De sig Ne w me nd ed for No t Re co m n— Di sco nt inu ed Pr od u Part Number1 ct Speed2 (MHz/ns) Org 128K x 32 GS84032AB-166 Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 C Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AGT-180T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. C = Commercial Temperature Range. I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.21 5/2014 26/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Ordering Information for GSI Synchronous Burst RAMs (Continued) Part Number1 Type Package Speed2 (MHz/ns) TA3 128K x 32 GS84032AB-150 Pipeline/Flow Through 119 BGA (var. 1) 150/10 C 128K x 32 GS84032AB-100 Pipeline/Flow Through 119 BGA (var. 1) 100/12 C 128K x 36 GS84036AB-180 Pipeline/Flow Through 119 BGA (var. 1) 180/8 C 128K x 36 GS84036AB-166 Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 C 128K x 36 GS84036AB-150 Pipeline/Flow Through 119 BGA (var. 1) 150/10 C 128K x 36 GS84036AB-100 Pipeline/Flow Through 119 BGA (var. 1) 100/12 C 256K x 18 GS84018AB-180I Pipeline/Flow Through 119 BGA (var. 1) 180/8 I 256K x 18 GS84018AB-166I Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 I 256K x 18 GS84018AB-150I Pipeline/Flow Through 119 BGA (var. 1) 150/10 I 256K x 18 GS84018AB-100I Pipeline/Flow Through 119 BGA (var. 1) 100/12 I 128K x 32 GS84032AB-180I Pipeline/Flow Through 119 BGA (var. 1) 180/8 I 128K x 32 GS84032AB-166I Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 I 128K x 32 GS84032AB-150I Pipeline/Flow Through 119 BGA (var. 1) 150/10 I 128K x 32 GS84032AB-100I Pipeline/Flow Through 119 BGA (var. 1) 100/12 I 128K x 36 GS84036AB-180I Pipeline/Flow Through 119 BGA (var. 1) 180/8 I 128K x 36 GS84036AB-166I Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 I 128K x 36 GS84036AB-150I Pipeline/Flow Through 119 BGA (var. 1) 150/10 I 128K x 36 GS84036AB-100I Pipeline/Flow Through 119 BGA (var. 1) 100/12 I 256K x 18 GS84018AGB-180 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 C 256K x 18 GS84018AGB-166 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 C 256K x 18 GS84018AGB-150 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 C 256K x 18 GS84018AGB-100 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 C 128K x 32 GS84032AGB-180 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 C 128K x 32 GS84032AGB-166 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 C 128K x 32 GS84032AGB-150 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 C 128K x 32 GS84032AGB-100 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 C 128K x 36 GS84036AGB-180 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 C 128K x 36 GS84036AGB-166 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 C 128K x 36 GS84036AGB-150 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 C 128K x 36 GS84036AGB-100 Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 C n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for Re co m ct Org No t 256K x 18 GS84018AGB-180I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AGT-180T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. C = Commercial Temperature Range. I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.21 5/2014 27/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 Ordering Information for GSI Synchronous Burst RAMs (Continued) Part Number1 Type Package Speed2 (MHz/ns) TA3 256K x 18 GS84018AGB-166I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 I 256K x 18 GS84018AGB-150I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 I 256K x 18 GS84018AGB-100I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 I 128K x 32 GS84032AGB-180I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 I 128K x 32 GS84032AGB-166I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 I 128K x 32 GS84032AGB-150I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 I 128K x 32 GS84032AGB-100I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 I 128K x 36 GS84036AGB-180I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 180/8 I 128K x 36 GS84036AGB-166I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 166/8.5 I 128K x 36 GS84036AGB-150I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 150/10 I n— Di sco nt inu ed Pr od u ct Org No t Re co m me nd ed for Ne w De sig 128K x 36 GS84036AGB-100I Pipeline/Flow Through RoHS-compliant 119 BGA (var. 1) 100/12 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032AGT-180T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. C = Commercial Temperature Range. I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.21 5/2014 28/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 9Mb Sync SRAM Datasheet Revision History Types of Changes Page /Revisions;Reason Format or Content GS84018/32/36 Rev 1.02c 5/1999; GS84018/32/36A 1.00First Release 8/1999D Format/Typos • Document/Continued changing to new format. ct New n— Di sco nt inu ed Pr od u Rev. Code: Old; • First Datasheet for this part. Content Format/Typos GS84018/32/36A1.00 8/ 1999;GS84018/32/36A1.01 9/ 1999E • Took “E” out of 840HE...in Core and Interface Voltages. • Pin outs/New small caps format. • Timing Diagrams/New format. • Block Diagrams/New small caps format. • Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to DQB3. • Pin Description/Rearranged Address Inputs to match order on TQFP Pinout. • TQFP Package Diagram/Corrected Dimension D Max from 20.1 to 22.1. Content • Fixed Ordering information and speed bins. • Took out Fine Pitch BGA Package. Package change in progress. GS84018/32/36A1.0210-11/ 1999;GS84018/32/36A1.032/ 2000G Format • New GSI Logo • Took “Pin” out of heading for consistency. GS84018/32/36A1.032/2000G; 84018A_r1_04 Content 84018A_r1_04; 84018A_r1_05 Content 84018A_r1_05; 84018A_r1_06 Content Re co m 84018A_r1_07; 84018A_r1_08 Ne w • Corrected all part order numbers me nd ed for 84018A_r1_06; 84018A_r1_07 De sig GS84018/32/36A1.01 9/ 1999E;GS84018/32/36A1.02 • Updated pin descriptions table • Updated BGA pin description table to meet JEDEC standard Content/Format • Added “non-A” speed bins to Operating Currents table, AC Electrical Characteristics table, and Ordering Information table • Updated format to fit Technical Documentation standards Content/Format • Updated font • Corrected IDD for 150 MHz and 100 MHz on page 1 and page 18 Content • Updated table on page 1 • Updated Operating Currents table on page 18 • Updated Electrical Characteristics table on page 19 84018A_r1_09, 84018A_r1_10 Content • Reduced IDD by 20 mA in table on page 1 and Operating Currents table 84018A_r1_10; 84018A_r1_11 Content • Corrected incorrect package type in ordering information table 84018A_r1_11; 84018A_r1_12 Content • Removed 200 MHz references from entire datasheet 84018A_r1_12; 84018A_r1_13 Content • Updated format • Added 190 MHz speed bin No t 84018A_r1_08; 84018A_r1_09 Rev: 1.21 5/2014 29/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS84018/32/36AGT/B*-180/166/150/100 9Mb Sync SRAM Datasheet Revision History Rev. Code: Old; New Types of Changes Page /Revisions;Reason Format or Content Content/Format • Updated entire format • Corrected current numbers to match NBT parts • Removed Preliminary banner 84018A_r1_14; 840xxA_r1_15 Content/Format • Added Pb-free TQFP information • Added variation number to 119 BGA information 84018A_r1_15; 840xxA_r1_16 Content • Added Ambient Temperature note (#3) on page 17 84018A_r1_16; 840xxA_r1_17 Content • Removed note #2 from Recommended Operating Temperatures table on page 17 • (Rev. 1.17a): Changed Pb-free to RoHS-compliant, added 119 BGA RoHS part, corrected incorrect temperature designator in ordering information table 84018A_r1_17; 840xxA_r1_18 Content • Added note to TQFP pinouts (pg. 2, 3, 4) • Updated Power Supply Voltage Ranges table (pg. 16) • Updated Logic Level tables (pg. 17) 840xxA_r1_18; 840xxA_r1_19 Content • Removed 190 MHz speed bin • Rev1.19a: updated coplanarity for 119 BGA mechanical, removed status column from Ordering Information table. 840xxA_r1_19; 840xxA_r1_20 Content n— Di sco nt inu ed Pr od u ct 84018A_r1_13; 840xxA_r1_14 No t Re co m me nd ed for Ne w De sig • Removed 5/6 RoHS TQFP package references due to EOL Rev: 1.21 5/2014 30/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology