Circuit - Davicom Semiconductor Inc.

5
4
EEDIO
EECS
EECK
X1
X2
RESET
P4S0
P4S1
STRAP_DIS
CFG4
DGND
PHY_MDC
TXC5
TXE5
INTR
TXD42
TXD43
RXC5
EECK
EECS
EEDIO
TXD40
TXD41
RXD41
RXDV4
RXD40
P4S0
COL4[2]
TXE4[2]
RXC4
STRAP_DIS
TXC4
CRS4
RXD43
RXD42
R1
T1
P4_TX-
4.7K
182R/1%
182R/1%
83R/1%
83R/1%
0R
0R
P4_RXP4_RX+
*NOTE
R3
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
FDXLED3
FDXLED2
FDXLED1
FDXLED0
[2] V_P
[2] NC3
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
4.7K
[2] NC4
RESET
X1
X2
C
[2] VCNTL
C6
P2_SPD_LED
P1_SPD_LED
P0_SPD_LED
WOL_EN
P4_FDX_LED
TEST1
DVDD33
P3_FDX_LED
P2_FDX_LED
P1_FDX_LED
P0_FDX_LED
V_P
GPIO0
DVDD18
GPIO1
DGND
PWRST#
X1
X2
AVDD18
AGND
VCNTL
VREF
AGND
BGRES
AVDD33
R25
RXNC
RX+
MCT
NC
TXNC
TX+
8
7
6
5
4
3
2
1
16
15
14
13
12
11
10
9
D
R6
SMI_CK
R2
SMI_MDIO R7
INTR
R11
DGND
P5_TXD[0]
P4_CFG
P5_TXD[1]
P5_TXD[2]
P5_TXD[3]
P5_COL(P5_SCLK)
P5_CRS(P5_RXCTL)
P5_RXD[3]
P5_RXD[2]
P5_RXD[1]
P5_RXD[0]
P5_RXDV(OSC125M)
P4_LNK_LED
DGND
DVDD33
P3_LNK_LED
P2_LNK_LED
DVDD18
DGND
SMI_CK
P1_LNK_LED
P0_LNK_LED
TEST3
SMI_MDIO
PHY_MDIO
U1
DM8806_QFP128
6.8K/1%
49.9/1% 49.9/1%
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
33R
33R
33R
TXD50
CFG4
TXD51
TXD52
TXD53
COL5
CRS5
RXD53
RXD52
RXD51
RXD50
RXDV5
C2
0.1uF
1
2
3
4
DGND
AGND
C3
0.1uF
*NOTE
3V3_FIBER
R13
1M
R14
127/1%
C4
R15
127/1%
R16
127/1%
0.1UF
R17
69/1%
LNKLED4 [2]
AGND
P4_RX+
P4_RX-
R19
R20
0R
0R
P4_TXP4_TX+
R21
R22
0R
0R
JP3
R18
69/1%
1
2
3
4
5
6
7
8
9
LNKLED3 [2]
LNKLED2 [2]
L1
F.B/120/S0805
L2
F.B/120/S0805
L3
F.B/120/S0805
SMI_CK
LNKLED1 [2]
LNKLED0 [2]
SMI_MDIO
PHY_MDIO
R23
R24
83/1%
DGND
4.7K
DGND
DVDD33
AGND
C5
0.1uF
Fiber_3.3V
AGND
C7
C8
C9
C10
C11
0.1UF
0.1UF
0.1UF
0.1UF
100UF
F.B/120/S0805
JP4
DGND
P3_78
DVDD18
AVDD18
B
[2]
[2]
[2]
[2]
PHY_MDC
PHY_MDIO
SMI_CK
SMI_MDIO
PHY_MDC
PHY_MDIO
SMI_CK
SMI_MDIO
AVDD18
P3_45
C12
C18
C19
C20
C21
C22
C23
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C13
C14
C15
C16
U2
C17
P3_RX+
P3_RX-
C24
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
100UF
47UF
P3_TX+
P3_TX-
P4 INTERFACE
DGND
P2_RX+
P2_RX-
AGND
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
COL4
TXE4
RXC4
TXC4
RXD43
RXD42
RXD41
RXD40
RXDV4
CRS4
TXD43
TXD42
TXD41
TXD40
COL4
TXE4
RXC4
TXC4
RXD43
RXD42
RXD41
RXD40
RXDV4
CRS4
TXD43
TXD42
TXD41
TXD40
AVDD33
P3_TX+
C25
C26
C27
C28
C29
C30
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
100UF
R26 49.9
R27 49.9
A
R29 49.9
P3_RX-
P1_RX+
P1_RXP1_TX+
P1_TX-
AGND
P2_TX+
R30 49.9
R31 49.9
P2_TX-
P2_RX+
C33 0.1UF
R32 49.9
R33 49.9
P0_RX+
P0_RX-
P2_RX-
C34 0.1UF
P0_TX+
P0_TXAGND
R35 75
RXC5
TXC5
TXE5
TXD53
TXD52
TXD51
TXD50
COL5
CRS5
RXD53
RXD52
RXD51
RXD50
RXDV5
R28 49.9
P2_TX+
P2_TX-
C32 0.1UF
P5 INTERFACE
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
P3_RX+
P3_TX-
C31 0.1UF
AGND
RXC5
TXC5
TXE5
TXD53
TXD52
TXD51
TXD50
COL5
CRS5
RXD53
RXD52
RXD51
RXD50
RXDV5
R34 75
P3_45
R41 75
P2_45
R44 75
P1_45
R36 75
P3_78
C35
P1_TX+
R37 49.9
R38 49.9
P1_TX-
1
2
3
4
5
4TD-/RD- 4TX-/RX4TD+/RD+ 4TX+/RX+
4CT
4CM
4RD-/TD- 4RX-/TX4RD+/TD+ 4RX+/TX+
40
39
38
37
36
3CM
6
7
8
9
10
3TD-/RD- 3TX-/RX3TD+/RD+ 3TX+/RX+
3CT
3CM
3RD-/TD- 3RX-/TX3RD+/TD+ 3RX+/TX+
35
34
33
32
31
2CM
11
12
13
14
15
2TD-/RD- 2TX-/RX2TD+/RD+ 2TX+/RX+
2CT
2CM
2RD-/TD- 2RX-/TX2RD+/TD+ 2RX+/TX+
30
29
28
27
26
1CM
16
17
18
19
20
1TD-/RD- 1TX-/RX1TD+/RD+ 1TX+/RX+
1CT
1CM
1RD-/TD- 1RX-/TX1RD+/TD+ 1RX+/TX+
25
24
23
22
21
0CM
P2_78
P2_45
P1_78
P1_45
P0_78
P0_45
MAGCOMHS4012
P1_RX+
R39 49.9
R40 49.9
P1_RX-
3CM
R42 75
R43 75
P2_78
C
3V3_FIBER
DVDD33
P4_TX+
P4_TX-
P4_RX+
P4_RX-
P3_RXP3_RX+
P3_TXP3_TX+
P2_RXP2_RX+
P2_TXP2_TX+
P1_RXP1_RX+
C1 0.01uF/2KV
AGND
L6
P1_TXP1_TX+
75/1%
PORT 4 FIBER
AVDD18
AVDD33
P0_RXP0_RX+
R9
75/1%
HEADER 4
AGND
P0_TXP0_TX+
R8
75/1%
49.9/1%
JP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
0.1UF
R5
RDNC
RD+
NC
CT
TDNC
TD+
R10
P3_SPD_LED
P4_SPD_LED
P4_SET1
DGND
P4_SET0
P4_COL
P4_TXE
P4_RXC
DVDD18
STRAP_DIS
P4_TXC
P4_CRS
P4_RXD[3]
P4_RXD[2]
DVDD33
DGND
P4_RXD[1]
P4_RXDV
P4_RXD[0]
DGND
DVDD18
EECK
EECS
EEDIO
P4_TXD[0]
P4_TXD[1]
DGND
DVDD18
P4_TXD[2]
P4_TXD[3]
P5_RXC
DVDD33
DGND
TEST2
PHY_MDC(SEL_SCLK)
P5_TXC(OSC50M)
P5_TXE(P5_TXCLK)
INTR
[2]
[2]
[2]
[2]
R12
R4
49.9/1%
AVDD18
P0_TXP0_TX+
AGND
AGND
P0_RXP0_RX+
AVDD33
AVDD18
P1_TXP1_TX+
AGND
AGND
P1_RXP1_RX+
AVDD33
AVDD18
P2_TXP2_TX+
AGND
P2_RXP2_RX+
AVDD33
AVDD18
P3_TXP3_TX+
AGND
AGND
P3_RXP3_RX+
AVDD33
P4_RX+
P4_RXAGND
AGND
P4_TX+
P4_TXAVDD18
SPDLED2
SPDLED1
SPDLED0
WOL_EN
FDXLED4
1
2
3
4
5
6
7
8
P4_TX+
R3
R4
R5
R6
C2
C3
RJ-45
JP1
PORT 4 TP
AVDD18
WHEN USE FIBER MODULE, MUST CHANGE
IC PART OF THE TP COMPONENT
DVDD33
DVDD18
DGND
[2]
[2]
[2]
[2]
[2]
DVDD33
1
DVDD33
R100
4.7K
D
2
Choose TP or Fiber to use
SPDLED3
SPDLED4
P4S1
[2] EEDIO
[2] EECS
[2] EECK
[2] X1
[2] X2
[2] RESET
[2] P4S0
[2] P4S1
[2] STRAP_DIS
[2] CFG4
3
C36 0.1UF
C37 0.1UF
32
31
30
29
28
27
26
25
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0.01UF/2KV
B
A
RJ45 X 4
2CM
R45 75
R46 75
AGND
P0_TX+
R52 75
R51 75
P0_45
Davicom Semiconductor Inc
P1_78
1CM
R53 75
P0_78
C40
R47 49.9
R48 49.9
P0_TX-
P0_RX+
C38 0.1UF
R49 49.9
R50 49.9
P0_RX-
Title
DM8806 DEMO BOARD
C39 0.1UF
Size
A3
0CM
AGND
0.01UF/2KV
5
4
3
Date:
2
Document Number
SWITCH6_MAIN
Friday, March 01, 2013
Rev
2.0
Sheet
1
1
of
3
4
3
Power 5V TO 3.3V
X1
5V
P1
DC-JACK
DVDD33
U3
AP1084,TO-263
3
VIN
VOUT
C41
C44
2
3
100UF/16V
25MHZ
F.B/120/S0805
C46
+
100UF/10V
0.1UF
20P
20P
C48
0.1UF
100UF/10V
AGND
DGND
AVDD33
U4
3
GNDO
OUT
DVDD18
L5
C53
1
R62
330
LNKLED3,2
J2 J1 Default: 1
LNKLED4
Port 4 PHY TP mode in M3A or M3C mode
1: Copper mode
0: fiber mode
0.1uF
J3
F.B/120/SO805
C55
C54
100uF/10V
C56
0.1uF
R66
147
E
ADJUSTABLE LDO CALCULATION
Vout = Vref x ( 1 + R66 / R62)
Vref = 1.25 V
For fixed Vout LDO, R62 =
open, R66 = 0 ohm
C
AGND
J5
When in M3B,Port4 in force mode
0 : 10M mode
1 : 100M mode
SPDLED1
AGND
Q1
**SPDLED3,2
J7 J6
C
AGND
DVDD33
SPDLED4
DVDD33
R75
J8
U5
1
2
3
4
10K
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
3
JUMPER
2
C58
0.1UF
U6 RESET_IC(AP1701DW)
FDXLED0
1
3
2
J9
1
R76
RESET
93C66/DIP8
10K
DGND
2
EECS
EECK
EEDIO
1
SMI_CK
SMI_MDIO
NC3
NC4
PHY_MDIO
PHY_MDC
EECS
EECK
EEDIO
X1
X2
RESET
P4S0
P4S1
CFG4
STRAP_DIS
WOL_EN
FDXLED1
DGND
SW1
DGND
TXE4
COL4
CRS4
TXD43
TXD42
TXD41
TXD40
PHY_MDIO
SMI_MDIO
RXD43
RXD42
RXD41
RXD40
RXC4
TXC4
+C59
10UF/10V
DGND
V_P
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
[1] V_P
DVDD33
JP5
RevMII USE
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
5V
DGND
P4 INTERFACE
R102
4.7K
DGND
RXC5
TXC5
TXE5
TXD53
TXD52
TXD51
TXD50
COL5
CRS5
RXD53
RXD52
RXD51
RXD50
RXDV5
HEADER_16X2
DVDD33
DGND
P5 INTERFACE
SMI_CK
RXDV5
PHY_MDC
5V
RESET
RXC5
TXC5
TXE5
TXD53
TXD52
TXD51
TXD50
COL5
CRS5
RXD53
RXD52
RXD51
RXD50
RXDV5
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
P5 INTERFACE
A
D3
R59
3
2
1
2
330
3
2
1
2
10K
3
1
3
D
1
J3
D4
R61
DUAL LED
1 R60
330
3
2
1
2
10K
R86
R88
NC/10K
NC/10K
TXE4
TXE5
JP6
D5
R64
3
1
D6
R67
Default: 0
MII
RMII
TXC
TXE
TXD3
TXD2
TXD1
TXD0
RXDV
RXC
RXER
RXD3
RXD2
RXD1
RXD0
COL
CRS
MDC
MDIO
TXE
TXD1
TXD0
RXDV
RXC
RXD1
RXD0
CRS_DV
MDC
MDIO
RevMII
TXC
RXC
TXE
TXD3
TXD2
TXD1
TXD0
RXDV
RXD3
RXD2
RXD1
RXD0
CRS
RXER
EXTERNAL MII
RXC
TXC
RXDV
RXD3
RXD2
RXD1
RXD0
TXE
TXD3
TXD2
TXD1
TXD0
CRS
COL
RXER
4
330
3
2
1
2
10K
D7
DUAL LED
1 R68
2
[1] SPDLED2
R69
330
3
2
1
2
10K
3
1
3
1
3
1
J7
D8
DUAL LED
1 R70
2
[1] SPDLED3
R71
330
3
2
1
2
10K
3
1
J8
D9
DUAL LED
1 R72
2
[1] SPDLED4
R73
330
3
2
1
2
10K
C
3
1
J10
D10
DUAL LED
1 R74
2
[1] FDXLED0
R77
330
3
2
1
2
10K
3
1
J11
D11
DUAL LED
1 R78
2
[1] FDXLED1
R79
330
3
2
1
2
10K
3
1
J12
D12
DUAL LED
1 R80
2
[1] FDXLED2
R81
330
3
2
1
2
10K
3
1
J13
D13
DUAL LED
1 R82
2
[1] FDXLED3
R83
330
3
2
1
2
10K
3
1
J14
D14
DUAL LED
1 R84
2
[1] FDXLED4
R85
330
3
2
1
2
10K
3
1
B
J15
P4S0
R87
4.7K
2
3
3
2
1
1
J16
Reserved
P4S1
**EECS
3
2
1
2
J6
Strap pins disabled
0: strap pins enabled
1: no strap pin function
GPIO1(NC4)
DUAL LED
1 R65
2
[1] SPDLED1
Port 5 Mode
FDXLED3 FDXLED2
0
0
Reserved, do not use
0
1
RMII
1
0
MII
1
1
RevMII
FDXLED4
When Port5 in force mode
J14 0 : link OFF
1 : link ON
Flow Control in PHY Register 4 bit 10
0: bit value is “1”
1: bit value is “0”
330
10K
J5
Port 4 in M3B Mode
SPDLED3 SPDLED2
0
0
RevMII with TXC4 turbo clock
0
1
RMII
1
0
MII
1
1
RevMII with TXC4 25MHz/2.5MHz clock
Port 4 in M3C Mode
SPDLED3 SPDLED2
0
X
Reserved, do not use
1
X
PHY_MII
When in M3B / M3C and Port4 in force mode
0 : link OFF
1 : link ON
GPIO0(NC3)
DUAL LED
1 R63
2
[1] SPDLED0
Port 5 link/duplex/speed mode in MII/RMII
0: force mode
1: PHY_MDC/PHY_MDIO polling mode
R90
CFG4
When in M3B , Port 4 link/duplex/speed mode in MII/RMII
0: force mode
1: PHY_MDC/PHY_MDIO polling mode
When in M3B , Port 4 link/duplex/speed mode in RevMII mode,
Port 4 always in force mode
Port 4 operation mode
CFG4
P4_SET1J16 P4_SET0J15
0
0
0
use internal PHY(M3A)
0
0
1
MII/RMII/RevMII(M3B)
1
X
X
TP MII (M3C)
V_P J17
Default: 0 Reserved
4.7K
2
3
3
2
1
R92
1
4.7K/NC
EECK
J17
V_P
R93
4.7K
2
3
3
2
1
1
NC3
R95
NC/4.7K
NC4
R96
NC/4.7K
EECS
R97
NC/4.7K
EECK
R98
NC/4.7K
DGND
STRAP_DIS R99
NC/4.7K
WOL_EN
R101
NC/4.7K
PHY_MDC
R103
NC/4.7K
A
Davicom Semicondutor Inc
Title
DM8806 DEMO BOARD
Size
A3
DGND
Date:
5
DUAL LED
1 R58
2
[1] LNKLED4
**FDXLED3,2
J13 J12
STRAP_DIS
SMI_CK
RXDV4
PHY_MDC
RESET
DVDD33
TXE5
COL5
CRS5
TXD53
TXD52
TXD51
TXD50
PHY_MDIO
COL4
TXE4
RXC4
TXC4
RXD43
RXD42
RXD41
RXD40
RXDV4
CRS4
TXD43
TXD42
TXD41
TXD40
SMI_MDIO
RXD53
RXD52
RXD51
RXD50
RXC5
TXC5
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
330
10K
2
[1] LNKLED3
When Port5 in force mode
J11 0 : 10M mode
1 : 100M mode
P4 INTERFACE
COL4
TXE4
RXC4
TXC4
RXD43
RXD42
RXD41
RXD40
RXDV4
CRS4
TXD43
TXD42
TXD41
TXD40
330
J2
When Port5 in force mode
J10 0 : Half-duplex mode
1 : Full-duplex mode
HEADER_16X2
B
R57
Reserved
When in M3B,Port4 in force mode
0 : Half-duplex mode
1: Full-duplex mode
C57
1uF
[1] SMI_CK
[1] SMI_MDIO
[1] NC3
[1] NC4
[1] PHY_MDIO
[1] PHY_MDC
[1] EECS
[1] EECK
[1] EEDIO
[1] X1
[1] X2
[1] RESET
[1] P4S0
[1] P4S1
[1] CFG4
[1] STRAP_DIS
[1] WOL_EN
1
J4
SPDLED0
100uF/10V
DGND
B
2SB1386
R55
DUAL LED
1 R56
2
[1] LNKLED2
PHY_MDC PORT 0 AND 1 TRUNK PORTS ENABLE
0: Disable
1: Enable
Choose U4 or Q1 to use
[1] VCNTL
330
J4
4
MULTIPLE FOOTPRINT
PLACE SOT223&SOT89 PACKAGE AT
SAME LOCATION
Wake On LAN Enable
0: disable
1: Enable to detect WOL magic packet event
LNKLED1 802.3az Energy Efficient Ethernet function for all ports
0: Disable
1: Enable
AGND
AVDD18
AP1117-1.8V
UT 2
IN
R54
J1
D2
WOL_EN
C47
LED
C42
D
Power 3.3V TO 1.8V
LED
D16
[1] LNKLED1
2
+ C43
0.1UF
DVDD33
D15
AVDD33
1
C45
1
[1] LNKLED0
L4
G
1
2
X2
X1
5
3
2
Document Number
RPOWER_STRAP_RST_XTAL_EPRROM
Friday, March 01, 2013
Sheet
1
Rev
2.0
2
of
3
5
VER
D
4
DATE
3
ENGINEER
2
1
NOTE
1.0
11/16/2010 MARCO FAN
NEW CIRCUIT
2.0
01/31/2011 MARCO FAN
Modify: 1. RXD0
D
Connect
4.7K to DGND
2. Dual LED add 10K fix Dual LED bug
3.IC pin define error , pin98 & pin100
2.0
03/01/2013 WILLIE NIOU
Exchange
RENAME FOR DM8806 CIRCUIT
C
C
B
B
A
A
Davicom Semiconductor Inc
Title
DM8806 DEMO BOARD
Size
A4
Date:
5
4
3
2
Document Number
HISTORY
Friday, March 01, 2013
Rev
2.0
3
Sheet
1
of
3