User’s Guide ATM12864D Liquid Crystal Display Module ATM12864D LCM Use’s Guide Contents Chapter 1. Introduction to ATM12864D LCM 2 Features 2 Mechanical Specifications 2 Temperature Characteristics 2 External Dimensions 3 Application Diagram 4 Electro- Optical characteristics 4 Interface Pin Connections 6 Electrical Absolute Maximum Rating (KS0107B) 7 DC Electrical Characteristics (KS0107B) 7 Electrical Absolute Maximum Rating (KS0108B) 8 DC Electrical Characteristics (KS0108B) 8 Chapter 2. Driver IC (KS0107B) Function Description 9 Introduction 9 AC Characteristics 10 Master Mode 10 Slave Mode 11 Functional Description 11 RC Oscillator 11 Timing Generation Circuit 12 Data Shift & Phase Select Control 13 Chapter 3. Driver IC (KS0108B) Function Description 13 Introduction 14 AC Characteristics 14 Operating Principles & Methods 16 Display Control Instruction 19 64CH Common Driver For Dot Matrix LCD CHAPTER 1 Introduction to ATM12864D LCM VT12864D is a dot matrix graphic LCD module which is fabricated by low power COMS technology. It can display 128*64 dots size LCD panel using a 128*64 bit-mapped Display Data RAM (DDRAM). It interfaces with an 8-bit microprocessor. Features l l l l l l l l l Display format: 128*64 dots matrix graphic STN yellow-green mode Easy interface with 8-bit MPU Low power consumption LED back-light Viewing angle: 6 O’ clock Driving method : 1/64 duty , 1/9 bias LCD driver IC: KS0108B(2 个)、KS0107B Connector: Zebra Mechanical Specifications ITEM Module Size(W*H*T) Viewing Area(W*H) Number of Dots Dot Size(W*H) Dot Pitch(W*H) Module Size With B/L DIMENSION 93.0*70.0*10.0 72.0*40.0 128.0*64.0 0.48*0.48 0.52*0.52 93.0*70.0*15.0 UNIT mm mm PCS mm mm mm Temperature Characteristics PARAMETER Operating temperature Storage temperature SYMBOL Topr Tstg RATING -25~+65 -30~+70 UNIT ℃ ℃ 2 64CH Common Driver For Dot Matrix LCD Figure 1. External Dimensions PIN SIGNAL PIN SIGNAL 1 2 3 4 5 6 7 8 9 10 Vss VDD V0 D/I R/W E DB0 DB1 DB2 DB3 11 12 13 14 15 16 17 18 19 20 DB4 DB5 DB6 DB7 CS1 CS2 RES VEE A K *NOTE: 1.All units are mm. 2.Tolerances unless otherwise specified ±0.2. 3 4 64CH Common Driver For Dot Matrix LCD Figure 2. Application Diagram LCD panel (128X64) SEG1 .... SEG64 .. COM1 COM64 SEG65 .... SEG128 KS0108B (Bottom view) M FRM CLK1 CLK2 CL2 VDD SHL FS MS PCLK2 DS2 DS1 VSS S64 M FRM CLK1 CLK2 CL2 CR C KS0107B S1 C64 C1 R VEE V5 V4 V3 V2 V1 V0 ADC VDD V0 V1 V2 V3 V4 V5 VEE VSS CS2B CS1B E RW RS DB[0:7] RESETB CS3 VSS VDD 12 V0 E RW RS DB[0:7] RESETB MPU V1 VSS V2 V3 V4 CS2 CS1 V5 VSS 12 VSS ADC VDD V0 V1 V2 V3 V4 V5 VEE CS2B S64 CS1B E RW RS DB[0:7] RESETB CS3 S1 LCD VVEE KS0108B M FRM CLK1 CLK2 CL2 (Bottom view) DC─DC CONVERTOR VDD VSS *Note 1/64 duty, 1/9 bias VDD >V1>V2>V3>V4>V5>VEE VEE 5 64CH Common Driver For Dot Matrix LCD Electro-Optical characteristics TN Type (Twisted Nematic ) ITEM SYMBOL θ2 -θ1 Viewing Angle φ MIN. TYP. MAX. UNIT CONDITION NOTE 40 - - deg. Cr = 2.0 1,2 θ=20ο φ= 0ο θ=20ο φ= 0ο θ=20ο φ= 0ο Contrast Ratio Cr - 4 - - Response Time (rise) tR - 110 - ms Response Time (fall) tF - 110 - ms TYP. MAX. UNIT CONDITION NOTE - +90 deg. Cr = 2.0 1,2 STN Type (Super Twisted Nematic ) ITEM SYMBOL MIN. θ2 -θ1 70 Viewing Angle -90 φ Contrast Ratio Cr - 4 - - Response Time (rise) tR - 110 - ms Response Time (fall) tF - 110 - ms 1. Definition of angle θ& φ 3 4 4 θ=20ο φ= 0ο θ=20ο φ= 0ο θ=20ο φ= 0ο ο θ2 θ1 ο θ 1<20 <θ 2 2.0 θ1 ο Y’(φ=0 ) 3. Definition of contrast Cr 100% ο θ2 4. Definition of optical response On Off Intensity Selected Dots Cr = ( A / B ) p Off 90% Nonselected Dots 0% 20 B A Set Point Intensity 100% 10% 100% Driving Voltage Negative : P = -1 Positive : P = +1 4 4 2. Definition of viewing angle θ 1 & φ 2 Cr Y(φ=180 ) 3 tR Time tF 64CH Common Driver For Dot Matrix LCD Interface Pin Connections PIN NO. 1 2 3 4 SYMBOL I/O TYPE VSS Supply VDD Supply V0 Supply D/I DESCRIPTION Ground Power supply LCD driver supply voltage Data input/output pin of internal shift register MS 5 SHL H H H L L H L L Read or Write R/W RW H while L 6 E DIO1 DIO2 Output Output Input Output Output Output Output Input Description Data appears at DB[7:0] and can be read by the CPU E= H CS1B=L,CS2B=L and CS3=H. Display data DB[7:0] can be written at falling edge of E when CS1B=L, CS2B=L and CS3=H. Enable signal E H L 7 8 9 10 11 12 13 14 15 16 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 CS1 CS2 I/O 17 RESETB I Description Read data in DB[7:0] appears while E= “High”. Display data DB[7:0] is latched at falling edge of E. Data bus [0~7] Bi-directional data bus I Chip selection When CS1=H,CS2=L, select IC1 When CS1=L,CS2=H, select IC2 Reset signal. When RSTB=L 【1】ON/OFF register becomes set by 0.(display off) 【2】display start line register becomes set by 0 (Z-address 0 set, display from line 0) 【3】After releasing reset , this condition can be changed only by instruction. 18 19 20 VEE A K Power VEE is connected by the same voltage. Back-light anode Back-light cathode 6 7 64CH Common Driver For Dot Matrix LCD Electrical Absolute Maximum Ratings (KS0107B) PARAMETER Operating voltage Supply voltage Driver supply voltage SYMBOL VDD VEE VB VLCD RATING -0.3 ~ +7.0 VDD -19.0 ~ VDD +0.3 -0.3 ~ VDD +0.3 VEE-0.3 ~ VDD +0.3 UNIT V V V V NOTE *1 *4 *1,2 *3,4 *Notes: *1. Based on VSS = 0V *2. Applies to input terminals and I/O terminals at high impedance. (Except V0L, V1L, V4L, and V5L) *3. Applies to V0L, V1L, V4L, and V5L. *4. Voltage level: VDD ≥V0≥V1≥V2≥V3≥V4≥V5≥VEE DC Electrical Characteristics(KS0107B) (VDD= 4.5 to 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= -30 to +85℃) ITEM SYMB CONDITION MIN. OL Operating voltage VDD 4.5 Input voltage VIH 0.7VDD VIL VSS TYP . - MAX. UNIT 5.5 VDD 0.3VD V NOT E *1 D output voltage Input leakage current OSC Frequency VOH VOL ILKG IOH = -0.4mA IOL= 0.4mA VIN = VDD ~ VSS VDD-0.4 -1.0 - 0.4 +1.0 µA fosc Rf=47kΩ±2% Cf=20pF±5% VDD -VEE=17V Load current± 150µA Master mode 1/128 Duty Master mode 1/128 Duty Master mode 1/128 Duty Master mode External Duty Slave mode 315 450 585 kHz - - 1.5 kΩ - - 1.0 mA - - 0.2 *4 - - 0.1 *5 50 - 600 0.5 - 1500 On Resistance (Vdiv-Ci) RONS Operating current IDD1 IDD2 Supply Current IEE Operating fop1 Frequency fop2 *2 *1 *3 kHz Notes *1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1, DIO2, M , and CL2 in the input state. *2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M , and CL2 in the output state. *3. This value is specified about current flowing through VSS. Internal oscillation circuit: Rf=47kΩ, cf=20pF Each terminals of DS1, DS2, FS, SHL, and MS is connected to VDD and out is no load. *4. This value is specified about current flowing through VSS. Each terminals is DS1, DS2, FS, SHL, PCLK2 and CR is connected to VDD,MS is connected to VSS and CL2, M, DIO1 is external clock. *5. This value is specified about current flowing through VEE, Don’ t connect to VLCD (V1~V5). 8 64CH Common Driver For Dot Matrix LCD Electrical Absolute Maximum Ratings(KS0108B) PARAMETER Operating voltage Supply voltage Driver supply voltage SYMBOL VDD VEE VB VLCD RATING -0.3 ~ +7.0 VDD -19.0 ~ VDD +0.3 -0.3 ~ VDD +0.3 VEE-0.3 ~ VDD +0.3 UNIT V V V V NOTE *1 *4 *1,3 *2 *Notes: *1. Based on VSS = 0V *2. Applies the same supply voltage to VEE. VLCD=VDD-VEE. *3. Applies to M, FRM, CLK1,CLK2, CL, RESETB, ADC, CS1B, CS2B,CS3, E, R/W, RS and DB0~DB7. *4. Applies V0L,V2L,V3L and V5L. Voltage level: VDD ≥V0≥V1≥V2≥V3≥V4≥V5≥VEE DC Electrical Characteristics(KS0108B) (VDD= 4.5 to 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= -30 to +85℃) ITEM SYMBO CONDITION MIN. L Operating voltage VDD 4.5 Input High voltage VIH1 0.7VDD VIH2 2.0 Input Low voltage VIL1 0 TYP . - MAX. UNIT 5.5 VDD VDD 0.3VD V NOT E *1 *2 *1 D Output High Voltage Output Low Voltage Input leakage current Three-state (OFF) Input Current Driver Input leakage current On Resistance (Vdiv-Ci) Operating current VIL2 VOH IOH = -0.2mA 0 2.4 - 0.8 - VOL ILKG IOL= 1.6mA VIN = VSS ~ VDD -1.0 - 0.4 +1.0 ITSL VIN = VSS ~ VDD -5.0 - 5.0 *5 IDIL VIN = VEE ~ VDD -2.0 2.0 *6 RONS VDD -VEE=15V Load current± 100µA During Display During Access Access Cycle=1MHz - - 7.5 kΩ *8 - - 0.1 0.5 mA *7 *7 IDD1 IDD2 Notes *1. CL, FRM, M, RSTB, CLK1, CLK2 *2. CS1B, CS2B, CS3, E, R/W, RS, DB0~DB7 *3. DB0~DB7 *4. Except DB0~DB7 *5. DB0~DB7 at high impedance *6. V0, V1, V3, V3, V4, V5 *7. 1/64 duty , FCLK=250KHZ, Frame Frequency=70HKZ, Output: No Load *8. VDD-VEE=13.5V V0L>V2L>= VDD-2/7(VDD-VEE)>V3L= VEE+2/7(VDD-VEE)>V5L *2 *3 µA *3 *4 64CH Common Driver For Dot Matrix LCD 9 CHAPTER 2 Driver IC Function Description KS0107 Driver IC 64COM graphic driver for dot matrix LCD Introduction The KS0107B is an :CD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing signal to control the KS0108B (64 channel segment drover.). The KS0107B is fabricated by low power CMOS high voltage process technology, and is composed of the liquid crystal display system in combination with the KS0108B (64 channel segment drover.). AC Characteristics (VDD=4.5~5.5V, Ta=-30℃~+85℃) 1. Master mode (MS=VDD, PCLK2=VDD, Cf=20pF, Rf=47KΩ) CL2 tWL 0.7VDD 0.3VDD tWHC tWHC tDH tSU tSU DIO1(SHL=VDD tD tD DIO2(SHL=VDD) DIO1(SHL=VSS ) tDF FRM tDM tDM 0.7VDD 0.3VDD M tR tWH1 tWL1 CLK1 tD21 tD12 tF CLK2 tWH2 tF CHARACTERISTIC Data Setup Time Data Hold Time tR SYMBOL tSU tDH MIN 20 40 TYP - MAX - UNIT 64CH Common Driver For Dot Matrix LCD Data Delay Time FRM Delay Time M Delay Time CL2 Low Level Width CL2 High Level Width CLK1 Low Level Width CLK2 Low Level Width CLK1 High Level Width CLK2 High Level Width CLK1-CLK2 Phase Difference CLK2-CLK1 Phase Difference CLK1,CLK2 Rise/Fall Time tD tDF tDM tWLC tWHC tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR /t F 5 -2 -2 35 35 700 700 2100 2100 700 700 - - 2 2 150 µs ns Slave mode (MS=VSS) CL2 (PLK2=V SS) tF tWLC1 tR 0.7VDD tWHC1 tSU CL2 (PLK2=VDD) tR tWLC2 tHCL 0.7VDD 0.3VDD tH DIO1(SHL=V DD) DIO2(SHL=V SS) Output Data CHARACTERISTICS CL2 Low Level Width CL2 High Level Width CL2 Low Level Width CL2 High Level Width Data Setup Time Data Hold Time Data Delay Time Output Data Hold Time CL2 Rise/Fall Time *1: Connect load CL=30pF tWLC tF tD DIO1(SHL=V DD) DIO2(SHL=V SS) Input Data 0.3VDD 0.7VDD 0.3VDD SYMBOL tWLC1 tWHC1 tWLC2 tWHL tSU tDH tD tH tR /tF MIN 450 150 150 450 100 100 10 - TYP - OUTPUT 30pF MAX 200 30 UNIT ns NOTE PCLK2=VSS PCLK2=VSS PCLK2=VDD PCLK2=VDD *1 10 64CH Common Driver For Dot Matrix LCD 11 FUNCTIONAL DESCRIPTION 1.RC Oscillator The RC Oscillator generates CL2, M, FRM, of the KS0107B and CLK1, CLK2 of the KS0107B by the oscillation resister R and capacitor C. When selecting the master/slave, oscillation circuit is as following: 1) Master Mode KS0107B KS0107B R CR Rf 2) C R open Cf CR C open External clock Slave Mode KS0107B R open CR VDD C open 2.Timing Generation circuit It generates CL2, M, FRM, CLK1, and CLK2 by the frequency from oscillation circuit. 1) 2) Selection of Master/Slave (M/S) When M/S is “H”, it generates CL2, M, FRM, CLK1, and CLK2 internally. When M/S is “L”, it operates by receiving M, CLK2 from master device. Frequency Selection (FS) To adjust FRM by 70Hz, the oscillation frequency should be as following: FS OSCILLATION FREQUENCY H fOSC =430KHz L fOSC =215KHz In the slave mode, it is connected to VDD. 64CH Common Driver For Dot Matrix LCD 3) Duty Selection (DS1, DS2) It provides various duty selection according to DS1, DS2. DS1 L H 3. DS2 L H L H DUTY 1/48 1/64 1/96 1/128 Data shift & Phase Select Control 1) 2) Phase Selection It is a circuit to shift data on synchronization or rising edge or falling edge of the CL2 according to PCLK2. PCLK2 PHASE SELECTION H Data shift on rising edge of CL2 L Data shift on falling edge of CL2 Data shift Direction Selection When M/S is connected to VDD, DIO1 and DIO2 terminal is only output. When M/S is connected to VSS, it depends on the SHL. MS H L SHL H L H L DIO1 Output Output Input Output DIO2 Output Output Output Input DIRECTION OF DATA C1~C64 C64~C1 DIO1~C1~C64~DIO2 DIO2~C64~C1~DIO1 12 64CH Segment Driver For Dot Matrix LCD 13 CHAPTER 3 Driver IC Function Description KS0108 Driver IC 64 SEG graphic driver for dot matrix LCD Introduction The KS0108B is an LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device consists of the display RAM, 64 bit data latch 64 bit drivers and decoder logics. It has the internal display RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix liquid crystal driving signals corresponding to stored data. The KS0108B composed of the liquid crystal display system in combination with the KS0107B(64 common driver). AC Characteristics (V DD=4.5~5.5V ,V SS=0V, Ta=-30℃~+85℃) （1） Clock Timing CHARACTERISTIC CLK1, CLK2 Cycle Time CLK1‘LOW’Level Width CLK2‘LOW’Level Width CLK1‘HIGH’Level Width CLK2‘HIGH’Level Width CLK1-CLK2 Phase Difference CLK2-CLK1 Phase Difference CLK1, CLK2 Rise Time CLK1, CLK2 Fall Time SYMBOL tCY tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR tF MIN 2.5 625 625 1875 1875 625 625 - TYP - MAX 20 150 150 UNIT µs ns 64CH Segment Driver For Dot Matrix LCD tCY tF CLK 1 0 .7 V D D 0 .3 V D D tW H 1 tR t W L1 CLK 2 tD1 2 tWL2 0 .7 V D D 0 .3 V D D tF tD 2 1 tF tW H 2 tCY （2）.Display Control Timing CHARACTERISTIC FRM Delay Time M Delay Time CL ‘LOW’Level Width CL‘HIGH’Level Width SYMBOL tDF tDM tWL tWH MIN -2 -2 35 35 TYP - MAX 2 2 - tWL CL 0. 7V DD 0. 3V DD t WH tDF FRM tDF 0.7V DD 0. 3VDD tDM M 0.7VDD 0. 3VDD UNIT us 14 64CH Segment Driver For Dot Matrix LCD （3）. MPU Interface CHARACTERISTIC E Cycle E High Level Width E Low Level Width E Rise Time E Fall Time Address Set-Up Time Address Hold Time Data Set-Up Time Data Delay Time Data Hold Time (Write) Data Hold Time (Read) SYMBOL tC tWH tWL tR tF tASU tAH tSU tD tDHW tDHR MIN 1000 450 450 140 10 200 10 20 TYP - MAX 25 25 320 - UNIT ns tC E tWL tWH tR R/W tF tAH tASU tASU tAH CS1B,CS2B CS3,RS tDSU DB0~DB7 MPU Write timing t DHW 15 64CH Segment Driver For Dot Matrix LCD 16 tC E tWL tWH tR tF R/W t ASU tAH t ASU tAH CS1B,CS2B CS3,RS tD tWH DB0~DB7 MPU Read timing OPERATING PRINCIPLES & METHODS 1. I/O Buffer Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB and ADC can operate regardless CS!B-CS3. 2. Input register Input register is provided to interface with MPU which is different operating frequency. Input register stores the data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU is written into input register. Then writing it into display RAM. Data latched for falling of the E signal and write automatically into the display data RAM by internal operation. 3. Output register Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active mode and R/W and RS=H, stored data in display data RAM is latched in output register. When CS1B to CS3 is in active mode and R/W=H , RS=L, status data (busy check) can read out. To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in display data RAM is latched into output register. In second access, MPU can read data which is latched. That is to read the data in display data RAM, it needs dummy read. But status read is not needed dummy read. 64CH Segment Driver For Dot Matrix LCD RS L R/W L H L H H 4. 17 FUNCTION Instruction Status read (busy check) Data write (from input register to display data RAM ) Data read (from display data RAM to output register) Reset The system can be initialized by setting RSTB terminal at low level when turning power on, receiving instruction from MPU. When RSTB becomes low, following procedure is occurred. 1. Display off 2. Display start line register become set by 0.(Z-address 0) While RSTB is low, No instruction except status read can by accepted. Therefore, execute other instructions after making sure that DB4= (clear RSTB) and DB7=0 (ready) by status read instruction. The conditions of power supply at initial power up are shown in table 1. Table 1. Power Supply Initial Conditions ITEM SYMBOL MIN TYP MAX UNIT Reset Time tRS 1.0 - - us Rise Time tR - - 200 ns 4.5[V] VDD tRS RSTB 5. tR 0.7VDD 0.3VDD Busy flag Busy flag indicates that KS0108B is operating or no operating. When busy flag is high, KS0108B is in internal operating . When busy flag is low, KS0108B can accept the data or instruction. DB7indicates busy flag of the KS0108B. E Busy Flag T Busy 1/fCLK<T Busy<3/fCLK fCLK is CLK1, CLK2 Frequency 64CH Segment Driver For Dot Matrix LCD 18 6. Display On/Off Flip-Flop The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low), selective voltage or non selective voltage appears on segment output terminals. When flip-flop is set (logic high), non selective voltage appears on segment output terminals regardless of display RAM data. The display on/off flip-flop can changes status by instruction. The display data at all segment disappear while RSTB is low. The status of the flip-flop is output to DB5 by status read instruction. The display on/off flip-flop synchronized by CL signal. 7. X Page Register X page register designates pages of the internal display data RAM. Count function is not available. An address is set by instruction. 8. Y address counter Y address counter designates address of the internal display data RAM. An address is set by instruction and is increased by 1 automatically by read or write operations of display data. 9. Display Data RAM Display data RAM stores a display data for liquid crystal display. To indicate on state dot matrix of liquid crystal display , write datra1. The other way , off state, writes 0. Display data RAM address and segment output can be controlled by ADC signal. ADC=H => Y-address 0: S1~Y address 63: S64 ADC=L => Y-address 0: S64~Yaddress 63: S1 ADC terminal connect the VDD or VSS. 10.Display Start Line Register The display start line register indicates of display data RAM to display top line of liquid crystal display. Bit data (DB<0.5>) of the display start line set instruction is latched in display start line register. Latched data is transferred to the Z address counter while FRM is high, presetting the Z address counter. It is used for scrolling of the liquid crystal display screen. 64CH Segment Driver For Dot Matrix LCD 19 Display Control Instruction The display control instructions control the internal state of the KS0108B. Instruction is received from MPU to KS0108B for the display control. The following table shows various instructions. INSTRUCTION RS RW Read Display Date 1 1 Read data Write Display Date 1 0 Write data Status Read 0 1 Bus y 0 Set Address (Y address) 0 0 0 1 Y address (0~63) Set Display Start Line 0 0 1 1 Display start line (0~63) Set Address (X address) 0 0 1 0 1 1 1 Display On/off 0 0 0 0 1 1 1 1. DB7 DB6 DB5 ON/ OFF DB4 DB3 Reset 0 DB2 DB1 DB0 0 0 0 Page (0~7) 1 1 0/1 FUNCTION Reads data (DB[7:0]) from display data RAM to the data bus. Writes data (DB[7:0]) into the DDRAM. After writing instruction, Y address is incriminated by 1 automatically Reads the internal status BUSY 0: Ready 1: In operation ON/OFF 0: Display ON 1: Display OFF RESET 0: Normal 1: Reset Sets the Y address at the column address counter Indicates the Display Data RAM displayed at the top of the screen. Sets the X address at the X address register. Controls the display ON or OFF. The internal status and the DDRAM data is not affected. 0: OFF, 1: ON Display On/Off The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D=0, it remains in the display data RAM. Therefore, you can make it appear by changing D=0 into D=1. RS 0 2. R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 1 DB1 1 DB0 D Set Address (Y Address) Y address (AC0~AC5) of the display data RAM is set in the Y address counter. An address is set by instruction and increased by 1 automatically by read or write operations of display data. RS 0 R/W 0 DB7 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0 64CH Segment Driver For Dot Matrix LCD 3. 20 Set Page (X Address) X address (AC0~AC2) of the display data RAM is set in the X address register. Writing or reading to or from MPU is executed in this specified page until the next page is set. RS 0 4. R/W 0 DB7 1 DB6 0 DB5 1 DB4 1 DB3 1 DB2 AC2 DB1 AC1 DB0 AC0 Display Start Line (Z Address) Z address (AC0~AC5) of the display data RAM is set in the display start line register and displayed at the top of the screen. When the display duty cycle is 1/64 or others (1/32~1/64), the data of total line number of LCD screen, from the line specified by display start line instruction, is displayed. RS 0 5. DB7 1 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0 DB4 RESET DB3 0 DB2 0 DB1 0 Status Read RS 1 6. R/W 0 R/W 0 DB7 BUSY DB6 0 DB5 ON/OFF l BUSY When BUSY is 1, the Chip is executing internal operation and no instructions are accepted. When BUSY is 0, the Chip is ready to accept any instructions. l ON/OFF When ON/OFF is 1, the display is on. When ON/OFF is 0, the display is off. l RESET When RESET is 1, the system is being initialized. In this condition, no instructions except status read can be accepted. When RESET is 0, initializing has finished and the system is in the usual operation condition. Write Display Data Writes data (D0~D7) into the display data RAM. After writing instruction, Y address is increased by 1 automatically. RS 1 7. DB0 0 R/W 0 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0 DB1 D1 DB0 D0 Read Display Data Reads data (D0~D7) from the display data RAM. After reading instruction, Y address is increased by 1 automatically. RS 1 R/W 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2