64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 INTRODUCTION The S6B0107 (TQFP type: S6B2107) is an LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing signal to control the S6B0108 (64 channel segment driver – TQFP type: S6B2108). The S6B0107 is fabricated by low power CMOS high voltage process technology, and is composed of the liquid crystal display system in combination with the S6B0108 (64 channel segment driver). FEATURES • Dot matrix LCD common driver with 64 channel output • 64-bit shift register at internal LCD driver circuit • Internal timing generator circuit for dynamic display • Selection of master/slave mode • Applicable LCD duty: 1/48, 1/64, 1/96, 1/128 • Power supply voltage: + 5V ± 10% • LCD driving voltage: 8V - 17V (VDD-VEE ) • Interface Driver COMMON SEGMENT Other S6B0107 S6B0108 • High voltage CMOS process • 100QFP / 100TQFP or bare chip available Controller MPU 1 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD C1 C2 C3 C62 C63 C64 BLOCK DIAGRAM V0L V1L V4L V5L V0R V1R V4R V5R 64 bit 4- Level Driver 64 bit Bi-Directional Shift Register DIO1 PCLK2 SHL Data Shift Direction & Phase Selection Control Circuit DIO2 M CL2 2 FS MS DS2 V EE V SS DS1 Timing Generator Circuit OSC V DD C R CR FRM CLK1 CLK2 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 PIN CONFIGURATION 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 100 QFP 1 2 3 4 5 6 80 79 78 77 76 75 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 7 8 9 10 11 12 13 14 15 16 17 18 19 20 C2 C1 V EE V1L V4L V5L V0L 21 22 23 24 25 26 27 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 V DD DIO1 FS 28 29 30 54 53 52 51 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 V EE V1R V4R V5R V0R NC CL2 NC DS1 DS2 C NC R NC CR NC SHL V SS NC MS CLK2 CLK1 NC FRM M NC PCLK2 DIO2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 S6B0107 C22 C21 C20 C19 C18 C17 3 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 PAD DIAGRAM (CHIP LAYOUT FOR THE 100QFP) C21 C20 2 3 79 78 C44 C45 C19 C18 C17 4 5 6 77 76 75 C46 C47 C48 C16 C15 C14 7 8 9 74 73 72 C49 C50 C51 C13 C12 C11 10 11 12 71 70 69 C52 C53 C54 C10 C9 C8 13 14 15 68 67 66 C55 C56 C57 C7 C6 C5 16 17 18 65 64 63 C58 C59 C60 C4 C3 19 20 62 61 C61 C62 C2 C1 V EE 21 22 23 60 59 58 C63 C64 V EE V1L V4L V5L 24 25 26 57 56 55 V1R V4R V5R V0L 27 54 V0R Y (0, 0) Chip size: 3450 × 4000 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 CR NC SHL V SS NC MS CLK2 CLK1 NC FRM M NC PCLK2 DIO2 NC CL2 NC × 100 V DD DIO1 FS DS1 DS2 C NC R NC PAD size: 100 Unit :µ m There is the mark S6B0107 on the center of the chip. 4 X 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 PAD CENTER COORDINATES (100QFP) Pad Number Pad Name Coordinate X Y Pad Number Pad Name Coordinate X Y Pad Number Pad Name Coordinate X Y 1 C22 -1314.5 1775.4 32 DS2 -677.6 -1775 71 C52 1500.9 630 2 C21 -1499.9 1630 34 C -527.6 -1775 72 C51 1500.9 755 3 C20 -1499.9 1505 35 R -377.6 -1775 73 C50 1500.9 880 4 C19 -1499.9 1380 37 CR -227.6 -1775 74 C49 1500.9 1005 5 C18 -1499.9 1255 39 SHL -77.6 -1775 75 C48 1500.9 1130 6 C17 -1499.9 1130 40 VSS 113.8 -1775 76 C47 1500.9 1255 7 C16 -1499.9 1005 42 MS 308.7 -1775 77 C46 1500.9 1380 8 C15 -1499.9 880 43 CLK2 458.7 -1775 78 C45 1500.9 1505 9 C14 -1499.9 755 44 CLK1 608.7 -1775 79 C44 1500.9 1630 10 C13 -1499.9 630 46 FRM 758.7 -1775 80 C43 1310.5 1775.4 11 C12 -1499.9 505 47 M 908.7 -1775 81 C42 1185.5 1775.4 12 C11 -1499.9 380 49 PCLK2 1058.7 -1775 82 C41 1060.5 1775.4 13 C10 -1499.9 255 50 DI02 1208.7 -1775 83 C40 935.5 1775.4 14 C9 -1499.9 130 52 CL2 1358.7 -1775 84 C39 810.5 1775.4 15 C8 -1499.9 5 54 V0R 1500.9 -1495 85 C38 685.5 1775.4 16 C7 -1499.9 -120 55 V5R 1500.9 -1370 86 C37 560.5 1775.4 17 C6 -1499.9 -245 56 V4R 1500.9 -1245 87 C36 435.5 1775.4 18 C5 -1499.9 -370 57 V1R 1500.9 -1120 88 C35 310.5 1775.4 19 C4 -1499.9 -495 58 VEE 1500.9 -995 89 C34 185.5 1775.4 20 C3 -1499.9 -620 59 C64 1500.9 -870 90 C33 60.5 1775.4 21 C2 -1499.9 -745 60 C63 1500.9 -745 91 C32 -64.5 1775.4 22 C1 -1499.9 -870 61 C62 1500.9 -620 92 C31 -189.5 1775.4 23 VEE -1499.9 -995 62 C61 1500.9 -495 93 C30 -314.5 1775.4 24 V1L -1499.9 -1120 63 C60 1500.9 -370 94 C29 -439.5 1775.4 25 V4L -1499.9 -1245 64 C59 1500.9 -245 95 C28 -564.5 1775.4 26 V5L -1499.9 -1370 65 C58 1500.9 -120 96 C27 -689.5 1775.4 27 V0L -1499.9 -1495 66 C57 1500.9 5 97 C26 -814.5 1775.4 28 VDD -1345.6 -1775 67 C56 1500.9 130 98 C25 -939.5 1775.4 29 DI01 -1127.6 -1775 68 C55 1500.9 255 99 C24 -1064.5 1775.4 30 FS -977.6 -1775 69 C54 1500.9 380 100 C23 -1189.5 1775.4 31 DS1 -827.6 -1775 70 C53 1500.9 505 5 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 V EE V1R V4R V5R V0R 100 TQFP (S6B2107) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 S6B2107 (100 TQFP) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V EE V1L V4L V5L V0L V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 6 NC CL2 NC DIO2 PCLK2 NC M FRM NC CLK1 CLK2 MS NC VSS SHL NC CR NC R NC C DS2 DS1 FS DIO1 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 PAD DIAGRAM (CHIP LAYOUT FOR THE 100-TQFP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Y (0, 0) X Chip size: 3850 X 100 PAD size: 100 X 100 Unit : µm 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 V EE V1R V4R V5R V0R DIO1 FS DS1 DS2 C NC R NC CR NC SHL V SS NC MS CLK2 CLK1 NC FRM M NC PCLK2 DIO2 NC CL2 NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 V EE V1L V4L V5L V0L V DD There is the mark S6B2107 on the center of the chip. 7 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD PAD CENTER COORDINATES (100-TQFP) Pad Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 8 Pad Name C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DIO1 FS DS1 DS2 C R CR Coordinate X Y -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1245 -1095 -945 -795 -645 NC -495 NC -345 1534 1409 1284 1159 1034 909 784 659 534 409 284 159 34 -91 -216 -341 -466 -591 -716 -841 -966 -1091 -1216 -1341 -1466 -1821 -1821 -1821 -1821 -1821 -1821 -1821 Pad Number Pad Name Coordinate X 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 SHL VSS MS CLK2 CLK1 FRM M PCLK2 DIO2 CL2 V0R V5R V4R V1R VEE C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 NC -195 0 NC 195 345 495 NC 645 795 NC 945 1095 NC 1245 NC 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 Pad Number Pad Name Y -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1466 -1341 -1216 -1091 -966 -841 -716 -591 466 -341 -216 -91 34 159 284 409 534 659 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 Coordinate X Y 1697 1697 1697 1697 1697 1697 1697 1500 1375 1250 1125 1000 875 750 625 500 375 250 125 0 -125 -250 -375 -500 -625 -750 -875 -1000 -1125 -1250 -1375 -1500 784 909 1034 1159 1284 1409 1534 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 PIN DESCRIPTION Table 1. Pin Description Pin Number QFP (TQFP) Symbol I/O 28(25) 40(37) 23(20), 58(55) VDD VSS VEE Power For internal logic circuit (+5V ± 10%) GND ( = 0 V) For LCD driver circuit Power Bias supply voltage terminals to drive LCD. 27(24), 54(51) 24(21), 57(54) 25(22), 56(53) 26(23), 55(52) V0L, V1L, V4L, V5L, V0R V1R V4R V5R Description Slelect Level Non-Select Level V0L (R), V5L (R) V1L (R), V4L (R) V0L and V0R (V1L & V1R, V4L & V4R, V5L & V5R) should be connected by the same voltage. 42(39) MS Input Selection of master/slave mode - Master mode (MS = 1) DIO1, DIO2, CL2 and M is output state. - Slave mode (MS = 0) SHL = 1 → DIO1 is input state (DIO2 is output state) SHL = 0 → DIO2 is input state (DIO1 is output state) CL2 and M are input state. 39(36) SHL Input Selection of data shift direction. SHL 49(46) PCLK2 Input H DIO1 → C1 ...... C64 → DIO2 L DIO2 → C64 ...... C1 → DIO1 Selection of shift clock (CL2) phase. PCLK2 30(27) FS Input Data Shift Direction Shift Clock (CL2) Phase H Data shift at the rising edge of CL2 L Data shift at the falling edge of CL2 Selection of oscillation frequency. - Master mode When the frame frequency is 70 Hz, the oscillation frequency should be fosc = 430kHz at FS = 1(VDD) fosc = 215kHz at FS = 0(VSS) - Slave mode Connect to VDD. 9 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD Table 1. Pin Description (Continued) Pin Number QFP (TQFP) 31(28) 32(29) Symbol I/O DS1 DS2 Input Description Selection of display duty. - Master mode DS1 DS2 Duty L L 1/48 L H 1/64 H L 1/96 H H 1/128 - Slave mode Connect to VDD 33(30) 35(32) 37(34) C R CR RC Oscillator - Master mode: Use these terminals as shown below. S6B0107 R CR S6B0107 C R Open - CR C Cf Rf External Open Slave mode: Stop the oscillator as shown below. R CR Open C Open V DD 44(41) 43(40) CLK1 CLK2 Output Operating clock output for the S6B0108 - Master mode: connection to CLK1 and CLK2 of the S6B0108 - Slave mode: open 46(43) FRM Output Synchronous frame signal. - Master mode: connection to FRM of the S6B0108 - Slave mode: open 47(44) M Input/ Output Alternating signal input for LCD driving. - Master mode: output state Connection to M of the S6B0108 - Slave mode: input state Connection to the controller 52(49) CL2 Input / Output Data shift clock - Master mode: output state Connection to CL of the S6B0108 - Slave mode: input state Connection to shift clock terminal of the controller. 10 64CH COMMON DRIVER FOR DOT MATRIX LCD 29(26) 50(47) DIO1 DIO2 Input/ Output S6B0107 Data input/output pin of internal shift register. MS H L DS2 DIO1 DIO2 H Output Output L Output Output H Input Output L Output Input 11 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD Table 1. Pin Description (Continued) Pin Number QFP (TQFP) 22-1(19-1) 100-59(10056) Symbol I/O C1-C64 Output 34(31), 36(33) 38(35), 41(38) 45(42), 48(45) 51(48), 53(50) Description Common signal output for LCD driving. NC Data M Out L L V1 L H V4 H L V5 H H V0 No connection MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Value Unit Note Operating voltage VDD -0.3 to +7.0 V (1) Supply voltage VEE VDD-19.0 to VDD+0.3 V (4) Driver supply voltage VB -0.3 to VDD+0.3 V (1), (2) VLCD VEE -0.3 to VDD+0.3 V (3), (4) Operating temperature TOPR -30 to +85 °C - Storage temperature TSTG -55 to +125 °C - NOTES: 1. Based on VSS = 0V 2. 3. 4. 12 Applies to input terminals and I/O terminals at high impedance. (Except V0L(R), V1L(R), V4L(R) and V5L(R)) Applies to V0L(R), V1L(R), V4L(R) and V5L(R). Voltage level: VDD ≥ V0L = V0R ≥ V1L = V1R ≥ V4L = V4R ≥ V5L = V5R ≥ VEE . 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (VDD = +5V ± 10%, VSS = 0V, |VDD-VEE |=8 - 17V, TA = -30 - +85°C) Characteristic Symbol Condition Min Typ Max Unit Note High VIH - 0.7VDD - VDD V (1) Low VIL VSS - 0.3VDD High VOH IOH = -0.4mA VDD-0.4 - - V (2) Low VOL IOL = 0.4mA - - 0.4 Input leakage current ILKG VIN = VDD-VSS -1.0 - 1.0 µA (1) OSC frequency fOSC Rf = 47kΩ ± 2% 315 450 585 kHz Input Voltage Output voltage Cf = 20pf ± 5% On resistance (VDIVCi) RON VDD-VEE = 17V Load current = ± 150µA - - 1.5 KΩ Operating current IDD1 Master mode 1/128 Duty - - 1.0 mA (3) IDD2 Slave mode 1/128 Duty - - 200 µA (4) Supply current IEE Master mode 1/128 Duty - - 100 Operating fop1 Master mode External clock 50 - 600 Frequency fop2 Slave mode 0.5 - 1500 (5) kHz NOTES: 1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1, DIO2, M and CL2 in the input state. 2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M and CL2 in the output state. 3. This value is specified at about the current flowing through VSS. Internal oscillation circuit: Rf = 47kΩ, Cf = 20pF. Each terminal of DS1, DS2, FS, SHL and MS is connected to VDD and out is no load. 4. This value is specified at about the current flowing through VSS. Each terminal of DS1, DS2, FS, SHL, PCLK2 and CR is connected to VDD, and MS is connected to VSS. CL2, M, DIO1 is external clock. 5. This value is specified at about the current flowing through VEE . Don’t connect to VLCD (V1-V5). 13 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD AC CHARACTERISTICS (VDD = 5V ± 10%, TA = -30°C - +85°C) Master Mode (MS = VDD, PCLK2 = VDD, Cf = 20pF, Rf = 47kΩ ) CL2 tWLC 0.7VDD 0.3VDD tWHC tsu tDH DIO1 (SHL = V DD ) DIO2 (SHL = V SS ) tD tD DIO2 (SHL = V DD ) DIO1 (SHL = V SS ) tDF FRM tDM tDM 0.7VDD M 0.3VDD tF tR tWH1 CLK1 tWL1 tD12 tD21 CLK2 tWH2 tF 14 tsu tR tWHC 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 Master Mode Characteristic Symbol Min Typ Max Unit Data setup time tSU 20 - - µs Data hold time tDH 40 - - Data delay time tD 5 - - FRM delay time tDF -2 - 2 M delay time tDM -2 - 2 CL2 low level width tWLC 35 - - CL2 high level width tWHC 35 - - CLK1 low level width tWL1 700 - - CLK2 low level width tWL2 700 - - CLK1 high level width tWH1 2100 - - CLK2 high level width tWH2 2100 - - CLK1-CLK2 phase difference tD12 700 - - CLK2-CLK1 phase difference tD21 700 - - CLK1, CLK2 rise/fall time tR/ tF - - 150 ns 15 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD Slave Mode (MS = VSS) tF tR tWLC1 0.7VDD CL2 (PLK2 = V SS ) 0.3VDD tWHC1 tSU tWHC2 tWLC CL2 (PLK2 = V DD ) tR tF tHCL tD DIO1 (SHL = V DD ) 0.7VDD DIO2 (SHL = V SS ) Input Data 0.3VDD tH DIO1 (SHL = V DD ) DIO2 (SHL = V SS ) 0.7VDD 0.3VDD Onput Data Characteristics Symbol Min Typ Max Unit Note CL2 low level width tWLC1 450 - - ns PCLK2 = VSS CL2 high level width tWHC1 150 - - ns PCLK2 = VSS CL2 low level width tWLC2 150 - - ns PCLK2 = VDD CL2 high level width tWHL 450 - - ns PCLK2 = VDD Data setup time tSU 100 - - ns Data hold time tDH 100 - - ns Data delay time tD - - 200 ns Output data hold time tH 10 - - ns tR/tF - - 30 ns CL2 rise/fall time NOTE: Connect load CL = 30pF Output 30pF 16 (NOTE) 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 FUNCTIONAL DESCRIPTION RC Oscillator The RC Oscillator generates CL2, M, FRM of the S6B0107, and CLK1 and CLK2 of the S6B0108 by the oscillation resister R and capacitor C. When selecting the master/slave mode, the oscillation circuit is as following: Master Mode: In the master mode, use these terminals as shown below. S6B0107 R S6B0107 C CR Rf Cf 47KΩ 20pF R Open Internal Oscillation CR External Clock C Open External Clock Slave Mode: In the slave mode, stop the oscillator as shown below. S6B0107 R Open CR V DD C Open Timing Generation Circuit It generates CL2, M, FRM, CLK1 and CLK2 by the frequency from the oscillation circuit. Selection of Master/Slave (M/S) Mode - When M/S is H, it generates CL2, M, FRM, CLK1 and CLK2 internally. - When M/S is “L”, it operates by receiving M and CL2 from the master device. Frequency Selection (FS) To adjust FRM frequency by 70Hz, the oscillation frequency should be as follows: FS Oscillation Frequency H fOSC = 430kHz L fOSC = 215kHz In the slave mode, it is connected to VDD. 17 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD Duty Selection (DS1, DS2) It provides various duty selections according to DS1 and DS2. DS1 DS2 DUTY L L 1/48 H 1/64 L 1/96 H 1/128 H Data Shift & Phase Select Control Phase Selection It is a circuit to shift data on synchronization or rising edge, or falling edge of the CL2 according to PCLK2. PCLK2 Phase Selection H Data shift on rising edge of CL2 L Data shift on falling edge of CL2 Data Shift Direction Selection When M/S is connected to VDD, DIO1 and DIO2 terminal is only output. When M/S is connected to VSS, it depends on the SHL. MS SHL DIO1 DIO2 H H Output Output C1 → C64 L Output Output C64 → C1 H Input Output DIO1 → C1 → C64 → DIO2 L Output Input DIO2 → C64 → C1 → DIO1 L 18 Direction of Data 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 TIMING DIAGRAM 1/48 DUTY TIMING (MASTER MODE) Condition: DS1 = L, DS2 = L, SHL = H(L), PCLK2 = H ~ ~ C ~ ~ CLK1 1 2 3 2 1 3 48 3 46 ~ ~ ~ ~ ~ ~ 47 48 ~ ~ V0 ~ ~ V4 V0 V4 ~ ~ V1 V0 V1 V1 V4 V5 ~ ~ ~ ~ DIO2 ( DIO1 ) V1 ~ ~ V5 V4 V5 ~ ~ V0 V4 V4 V5 ~ ~ V1 V4 V1 ~ ~ V4 V5 V0 V1 V5 ~ ~ V1 V4 ~ ~ V1 V1 C48 ( C1 ) 2 ~ ~ M C47 ( C2 ) 1 ~ ~ DIO1 ( DIO2 ) 47 ~ ~ FRM 46 ~ ~ CL2 C2 ( C47 ) 64 ~ ~ CLK2 C1 ( C48 ) 63 Relation of CL2 & DIO1 ( DIO2 ) ~ ~ ~ ~ ~ ~ ~ ~ DIO1 ( DIO2 ) ~ ~ CL2 ~ ~ CLK2 19 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 1/128 DUTY TIMING (MASTER MODE) Condition: DS1 = H, DS2 = H, SHL = H(L), PCLK2 = H C CLK1 1 2 3 23 24 CLK2 1 2 3 2 3 126 127 128 ~ ~ ~ ~ ~ ~ ~ ~ DIO1 ( DIO2 ) ~ ~ ~ ~ M V1 V0 ~ ~ V1 V5 V1 V4 V4 ~ ~ V0 V1 ~ ~ V4 V0 V1 V4 ~ ~ C2 ( C127 ) 1 ~ ~ FRM C1 ( C128 ) 126 127 128 ~ ~ CL2 V5 V0 V1 V1 V1 V4 ~ ~ V5 V4 V5 ~ ~ C127 ( C2 ) V4 V1 V5 V5 ~ ~ ~ ~ DIO2 ( DIO1 ) Relation of CL2 & DIO1 ( DIO2 ) ~ ~ ~ ~ ~ ~ 20 ~ ~ DIO1 (DIO2) ~ ~ CL2 ~ ~ CLK2 V4 ~ ~ V1 V0 ~ ~ C128 ( C1 ) V4 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 1/48 DUTY TIMING (SLAVE MODE) Condition: PCLK2 = L, SHL = H(L) 1 2 46 47 48 1 2 46 47 48 CL2 ~ ~ ~ ~ ~ ~ M ~ ~ DIO1 ( DIO2 ) ~ ~ ~ ~ V1 V1 V0 V0 ~ ~ C1 ( C48 ) V4 ~ ~ V5 V1 V0 V1 ~ ~ C2 ( C47 ) V4 V4 V4 V1 ~ ~ V5 V0 V1 V1 V1 ~ ~ V4 C47 ( C2 ) V4 V4 ~ ~ V5 V0 V1 ~ ~ V4 V4 ~ ~ C48 ( C1 ) V5 V5 DIO2 ( DIO1 ) ~ ~ ~ ~ 21 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD POWER DRIVER CIRCUIT V DD V0 V0L/R V DD R1 V1 V1L/R R1 V2 To R2 V3 S6B0107 S6B0108 R1 V4 V4L/R R1 V5 V5L/R VR V EE V EE Relation of Duty & Bias Duty Bias RDIV 1/48 1/8 R2 = 4R1 1/64 1/9 R2 = 5R1 1/96 1/11 R2 = 7R1 1/128 1/12 R2 = 8R1 When duty factor is 1/48, the value of R1 & R2 should satisfy. R1/(4R1 + R2) = 1/8 R1 + 3kΩ, R2 = 12kΩ 22 V0 V DD DIO2 SHL 2 M FRM 5 S6B0107 CLK1 (slave) CLK2 CLK1 FRM CR C R V2 V3 V4 V5 CR V EE SHL KS2 DS1 FS 5 RS R/W E RSTB DB0 - DB7 CS1B CS2B CS3 V DD CL CLK2 CLK1 M S 1 - S 64 64 15 15 CS3 CS2B S6B0108 CS1B DB0 -DB7 RSTB E R/W RS V SS V1 C64 PCLK2 FRM SEG1 S1 - S V5R/L V3R/L V2R/L V0R/L V EE V EE V5R/L V3R/L V2R/L V0R/L V DD CL CLK2 CLK1 M FRM V SS CL CLK2 CLK1 M FRM V DD 15 64 15 V5R/L V3R/L V2R/L V EE V0R/L SEG128 V EE V5R/L V3R/L V2R/L V0R/L 64 S1 - S S1 - S CS3 CS2B CS1B DB0 -DB7 RSTB E R/W RS V SS open open open open open MS FS M S6B0108 V SS CLK2 CL2 V EE MS CL2 V 5R/L PCLK2 DIO2 V 4R/L S6B0107 (master) C1 open open COM128 V 1R/L R V 0R/L DS2 DIO1 V DD DS1 V EE C64 COM1 V 5R/L R1 C V 4R/L C1 V 1R/L C1 V SS CL CLK2 CLK1 M FRM V DD 15 CS3 CS2B S6B0108 CS1B DB0 -DB7 RSTB E R/W RS V 0R/L V SS 5 CS3 CS2B CS1B S6B0108 DB0 -DB7 RSTB E R/W RS V DD V DD 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 APPLICATION CIRCUIT 1/128 duty Segment driver (S6B0108) interface circuit LCD Panel MPU 23