S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD July 2001 Ver. 0.0 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. 2. Always test and inspect products under the environment with no penetration of light. S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 Specification Revision History Version 0.0 2 Content Original Date July.2001 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 CONTENTS INTRODUCTION ............................................................................................................................................. 1 BLOCK DIAGRAM .......................................................................................................................................... 2 PIN CONFIGURATION .................................................................................................................................... 3 100-QFP.................................................................................................................................................. 3 PAD DIAGRAM (CHIP LAYOUT FOR THE 100QFP).................................................................................... 4 PAD CENTER COORDINATES (100QFP)................................................................................................... 5 100-TQFP (S6B2107)................................................................................................................................ 6 PAD DIAGRAM (CHIP LAYOUT FOR THE 100-TQFP)................................................................................. 7 PAD CENTER COORDINATES (100-TQFP)................................................................................................ 8 PIN DESCRIPTION ........................................................................................................................................10 ELECTRICAL CHARACTERISTICS .................................................................................................................13 DC CHARACTERISTICS ..........................................................................................................................13 AC CHARACTERISTICS (VDD = 5V ± 10%, TA = -30°C to +85°C)..............................................................14 FUNCTIONAL DESCRIPTION ...................................................................................................................17 TIMING DIAGRAM .........................................................................................................................................19 1/48 DUTY TIMING (MASTER MODE).......................................................................................................19 1/128 DUTY TIMING (MASTER MODE).....................................................................................................20 1/48 DUTY TIMING (SLAVE MODE)..........................................................................................................21 POWER DRIVER CIRCUIT.......................................................................................................................22 APPLICATION CIRCUIT ...........................................................................................................................23 3 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 INTRODUCTION The S6B0107 (TQFP type: S6B2107) is a LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic display systems. This device provides 64 shift registers and 64 output drivers. It generates the timing signal to control the S6B0108 (64 channel segment driver - TQFP type: S6B2108). The S6B0107 is fabricated by low power CMOS high voltage process technology, and is composed of the liquid crystal display system in combination with the S6B0108 (64 channel segment driver). FEATURES — Dot matrix LCD common driver with 64 channel output — 64-bit shift register at internal LCD driver circuit — Internal timing generator circuit for dynamic display — Selection of master/slave mode — Applicable LCD duty: 1/48, 1/64, 1/96, 1/128 — Power supply voltage: + 5V ± 10% — LCD driving voltage: 8V - 17V (V DD-VEE) — Interface Driver COMMON SEGMENT Other S6B0107 S6B0108 — High voltage CMOS process — 100QFP/100TQFP and bare chip available Controller MPU 1 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD C1 C2 C3 C62 C63 C64 BLOCK DIAGRAM V0L V1L V4L V5L V0R V1R V4R V5R 64 bit 4- Level Driver 64 bit Bi-Directional Shift Register DIO1 PCLK2 SHL Data Shift Direction & Phase Selection Control Circuit DIO2 M CL2 2 S MS DS2 VEE VSS DS1 Timing Generator Circuit OSC VDD C R CR FRM CLK1 CLK2 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 PIN CONFIGURATION 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 100-QFP S6B0107 (100-QFP) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R NC CL2 NC 31 32 33 35 37 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DS1 DS2 C R CR SHL VSS NC MS CLK2 CLK1 NC FRM M NC PCLK2 DIO2 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD DIO1 FS 3 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 PAD DIAGRAM (CHIP LAYOUT FOR THE 100QFP) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (0, 0) X Chip size: 3450 × 4000 PAD size: 100 × 100 Unit : µm CL2 52 DIO2 50 PCLK2 49 M 47 FRM 46 CLK1 44 CLK2 43 MS 42 VSS 40 SHL 39 CR 37 R 35 C 33 DS2 32 DS1 31 FS 30 DIO1 29 S6B0107 There is the mark S6B0107 on the center of the chip. 4 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 Y VDD 28 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 PAD CENTER COORDINATES (100QFP) Pad Pad Coordinate Pad Pad Number Name X 1 C22 2 Coordinate Pad Pad Y Number Name X -1314.5 1775.4 32 DS2 C21 -1499.9 1630 33 3 C20 -1499.9 1505 4 C19 -1499.9 5 C18 6 Coordinate Y Number Name X Y -677.6 -1775 71 C52 1500.9 630 C -527.6 -1775 72 C51 1500.9 755 35 R -377.6 -1775 73 C50 1500.9 880 1380 37 CR -227.6 -1775 74 C49 1500.9 1005 -1499.9 1255 39 SHL -77.6 -1775 75 C48 1500.9 1130 C17 -1499.9 1130 40 VSS 113.8 -1775 76 C47 1500.9 1255 7 C16 -1499.9 1005 42 MS 308.7 -1775 77 C46 1500.9 1380 8 C15 -1499.9 880 43 CLK2 458.7 -1775 78 C45 1500.9 1505 9 C14 -1499.9 755 44 CLK1 608.7 -1775 79 C44 1500.9 1630 10 C13 -1499.9 630 46 FRM 758.7 -1775 80 C43 1310.5 1775.4 11 C12 -1499.9 505 47 M 908.7 -1775 81 C42 1185.5 1775.4 12 C11 -1499.9 380 49 PCLK2 1058.7 -1775 82 C41 1060.5 1775.4 13 C10 -1499.9 255 50 DI02 1208.7 -1775 83 C40 935.5 1775.4 14 C9 -1499.9 130 52 CL2 1358.7 -1775 84 C39 810.5 1775.4 15 C8 -1499.9 5 54 V0R 1500.9 -1495 85 C38 685.5 1775.4 16 C7 -1499.9 -120 55 V5R 1500.9 -1370 86 C37 560.5 1775.4 17 C6 -1499.9 -245 56 V4R 1500.9 -1245 87 C36 435.5 1775.4 18 C5 -1499.9 -370 57 V1R 1500.9 -1120 88 C35 310.5 1775.4 19 C4 -1499.9 -495 58 VEE 1500.9 -995 89 C34 185.5 1775.4 20 C3 -1499.9 -620 59 C64 1500.9 -870 90 C33 60.5 1775.4 21 C2 -1499.9 -745 60 C63 1500.9 -745 91 C32 -64.5 1775.4 22 C1 -1499.9 -870 61 C62 1500.9 -620 92 C31 -189.5 1775.4 23 VEE -1499.9 -995 62 C61 1500.9 -495 93 C30 -314.5 1775.4 24 V1L -1499.9 -1120 63 C60 1500.9 -370 94 C29 -439.5 1775.4 25 V4L -1499.9 -1245 64 C59 1500.9 -245 95 C28 -564.5 1775.4 26 V5L -1499.9 -1370 65 C58 1500.9 -120 96 C27 -689.5 1775.4 27 V0L -1499.9 -1495 66 C57 1500.9 5 97 C26 -814.5 1775.4 28 VDD -1345.6 -1775 67 C56 1500.9 130 98 C25 -939.5 1775.4 29 DI01 -1127.6 -1775 68 C55 1500.9 255 99 C24 -1064.5 1775.4 30 FS -977.6 -1775 69 C54 1500.9 380 100 C23 -1189.5 1775.4 31 DS1 -827.6 -1775 70 C53 1500.9 505 5 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 100-TQFP (S6B2107) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 S6B2107 (100-TQFP) DIO1 FS DS1 DS2 C NC R NC CR NC SHL VSS NC MS CLK2 CLK1 NC FRM M NC PCLK2 DIO2 NC CL2 NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD 6 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 PAD DIAGRAM (CHIP LAYOUT FOR THE 100-TQFP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NOTE: 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Y (0, 0) X C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 VEE V1R V4R V5R V0R CL2 49 DIO2 47 PCLK2 46 M 44 FRM 43 CLK1 41 CLK2 40 MS 39 VSS 37 SHL 36 CR 34 R 32 C 30 DS2 29 DS1 28 FS 27 Chip size: 3850 × 4100 PAD size: 100 × 100 Unit : µm DIO1 26 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 VEE V1L V4L V5L V0L VDD There is the mark S6B2107 on the center of the chip. 7 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD PAD CENTER COORDINATES (100-TQFP) 8 Pad Pad Coordinate Pad Pad Number Name X 1 C19 2 Coordinate Pad Pad Y Number Name Number Name X Y -1697 1534 35 69 C51 1697 784 C18 -1697 1409 36 SHL -195 -1821 70 C50 1697 909 3 C17 -1697 1284 37 VSS 0 -1821 71 C49 1697 1034 4 C16 -1697 1159 38 72 C48 1697 1159 5 C15 -1697 1034 39 MS 195 -1821 73 C47 1697 1284 6 C14 -1697 909 40 CLK2 345 -1821 74 C46 1697 1409 7 C13 -1697 784 41 CLK1 495 -1821 75 C45 1697 1534 8 C12 -1697 659 42 76 C44 1500 1822 9 C11 -1697 534 43 FRM 645 -1821 77 C43 1375 1822 10 C10 -1697 409 44 M 795 -1821 78 C42 1250 1822 11 C9 -1697 284 45 79 C41 1125 1822 12 C8 -1697 159 46 PCLK2 945 -1821 80 C40 1000 1822 13 C7 -1697 34 47 DIO2 1095 -1821 81 C39 875 1822 14 C6 -1697 -91 48 82 C38 750 1822 15 C5 -1697 -216 49 83 C37 625 1822 16 C4 -1697 -341 50 84 C36 500 1822 17 C3 -1697 -466 51 V0R 1697 -1466 85 C35 375 1822 18 C2 -1697 -591 52 V5R 1697 -1341 86 C34 250 1822 19 C1 -1697 -716 53 V4R 1697 -1216 87 C33 125 1822 20 VEE -1697 -841 54 V1R 1697 -1091 88 C32 0 1822 21 V1L -1697 -966 55 VEE 1697 -966 89 C31 -125 1822 22 V4L -1697 -1091 56 C64 1697 -841 90 C30 -250 1822 23 V5L -1697 -1216 57 C63 1697 -716 91 C29 -375 1822 24 V0L -1697 -1341 58 C62 1697 -591 92 C28 -500 1822 25 VDD -1697 -1466 59 C61 1697 466 93 C27 -625 1822 26 DIO1 -1245 -1821 60 C60 1697 -341 94 C26 -750 1822 27 FS -1095 -1821 61 C59 1697 -216 95 C25 -875 1822 28 DS1 -945 -1821 62 C58 1697 -91 96 C24 -1000 1822 29 DS2 -795 -1821 63 C57 1697 34 97 C23 -1125 1822 X Y NC NC NC NC NC CL2 1245 -1821 NC Coordinate 64CH COMMON DRIVER FOR DOT MATRIX LCD 30 C 31 32 -1821 NC R 33 34 -645 -495 -1821 NC CR -345 -1821 S6B0107 64 C56 1697 159 98 C22 -1250 1822 65 C55 1697 284 99 C21 -1375 1822 66 C54 1697 409 100 C20 -1500 1822 67 C53 1697 534 68 C52 1697 659 9 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD PIN DESCRIPTION Table 1. Pin Description Pin Number QFP (TQFP) 28(25) 40(37) 23(20), 58(55) 27(24), 54(51) 24(21), 57(54) 25(22), 56(53) 26(23), 55(52) Symbol I/O VDD Power For internal logic circuit (+5V ± 10%) GND ( = 0 V) For LCD driver circuit Power Bias supply voltage terminals to drive LCD. VSS VEE V0L, V1L, V4L, V5L, V0R V1R V4R V5R Description Slelect Level Non-Select Level V0L (R), V5L (R) V1L (R), V4L (R) V0L and V0R (V1L & V1R, V4L & V4R, V5L & V5R) should be connected by the same voltage. 42(39) MS Input Selection of master/slave mode - Master mode (MS = 1) DIO1, DIO2, CL2 and M is output state. - Slave mode (MS = 0) SHL = 1 → DIO1 is input state (DIO2 is output state) SHL = 0 → DIO2 is input state (DIO1 is output state) CL2 and M are input state. 39(36) SHL Input Selection of data shift direction. SHL 49(46) PCLK2 Input Data Shift Direction H DIO1 → C1 ...... C64 → DIO0 L DIO2 → C64 ...... C1 → DIO0 Selection of shift clock (CL2) phase. PCLK2 30(27) FS Input Shift Clock (CL2) Phase H Data shift at the rising edge of CL2 L Data shift at the falling edge of CL2 Selection of oscillation frequency. - Master mode When the frame frequency is 70 Hz, the oscillation frequency should be fosc = 430kHz at FS = 1(V DD) fosc = 215kHz at FS = 0(V SS) - Slave mode Connect to VDD. 10 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 Table 1. Pin Description (Continued) Pin Number QFP (TQFP) 31(28) 32(29) Symbol I/O DS1 DS2 Input Description Selection of display duty. - Master mode DS1 DS2 Duty L L 1/48 L H 1/64 H L 1/96 H H 1/128 - Slave mode Connect to VDD 33(30) 35(32) 37(34) C R CR RC Oscillator - Master mode: Use these terminals as shown below. S6B0107 S6B0107 R Rf CR Cf C R Open CR C External Open - Slave mode: Stop the oscillator as shown below. R CR Open VDD C Open 44(41) 43(40) CLK1 CLK2 Output Operating clock output for the S6B0108 - Master mode: connection to CLK1 and CLK2 of the S6B0108 - Slave mode: open 46(43) FRM Output Synchronous frame signal. - Master mode: connection to FRM of the S6B0108 - Slave mode: open 47(44) M Input/ Output Alternating signal input for LCD driving. - Master mode: output state Connection to M of the S6B0108 - Slave mode: input state Connection to the controller 52(49) CL2 Input / Output Data shift clock - Master mode: output state Connection to CL of the S6B0108 - Slave mode: input state Connection to shift clock terminal of the controller. 29(26) 50(47) DIO1 DIO2 Input/ Output Data input/output pin of internal shift register. MS H L DS2 DIO1 DIO2 H Output Output L Output Output H Input Output L Output Input 11 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD Table 1. Pin Description (Continued) Pin Number QFP (TQFP) Symbol I/O 22-1(19-1) 100-59(100-56) C1-C64 Output 34(31), 36(33) 38(35), 41(38) 45(42), 48(45) 51(48), 53(50) Description Common signal output for LCD driving. NC Data M Out L L V1 L H V4 H L V5 H H V0 No connection MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Value Unit Note Operating voltage VDD -0.3 - +7.0 V (1) Supply voltage VEE VDD-19.0 - VDD+0.3 V (4) Driver supply voltage VB -0.3 - VDD+0.3 V (1), (2) VLCD VEE-0.3 - VDD+0.3 V (3), (4) Operating temperature TOPR -30 - +85 °C – Storage temperature TSTG -55 - +125 °C – NOTES: 1. Based on VSS = 0V 2. 3. 4. 12 Applies to input terminals and I/O terminals at high impedance. (Except V0L(R), V1L(R), V4L(R) and V5L(R)). Applies to V0L(R), V1L(R), V4L(R) and V5L(R). Voltage level: VDD ≥ V0L = V0R ≥ V1L = V1R ≥ V4L = V4R ≥ V5L = V5R ≥ VEE. 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (V DD = +5V ± 10%, VSS = 0V, |V DD-VEE |=8 - 17V, Ta = -30 to +85°C) Characteristic Symbol Condition Min Typ Max Unit Note – 0.7V DD – VDD V (1) VSS – 0.3V DD V (2) (1) Input High VIH Voltage Low VIL Output High VOH IOH = -0.4mA VDD-0.4 – – Voltage Low VOL IOL = 0.4mA – – 0.4 Input leakage current ILKG VIN = VDD-VSS -1.0 – 1.0 µA OSC frequency fOSC Rf = 47kΩ ± 2% 315 450 585 kHz – – 1.5 KΩ Cf = 20pf ± 5% On resistance (VDIV-CI) RON VDD-VEE = 17V Load current = ± 150µA Operating current IDD1 Master mode 1/128 Duty – – 1.0 mA (3) IDD2 Slave mode 1/128 Duty – – 200 µA (4) Supply current IEE Master mode 1/128 Duty – – 100 Operating fop1 Master mode External clock 50 – 600 Frequency fop2 Slave mode 0.5 – 1500 (5) kHz NOTES: 1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1, DIO2, M and CL2 in the input state. 2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M and CL2 in the output state. 3. This value is specified at about the current flowing through VSS. Internal oscillation circuit: Rf = 47kΩ, Cf = 20pF Each terminal of DS1, DS2, FS, SHL and MS is connected to VDD and out is no load. 4. This value is specified at about the current flowing through VSS. Each terminal of DS1, DS2, FS, SHL, PCLK2 and CR is connected to VDD, and MS is connected to VSS. CL2, M, DIO1 is external clock. 5. This value is specified at about the current flowing through VEE. Don't connect to VLCD (V1-V5). 13 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD AC CHARACTERISTICS (VDD = 5V ± 10%, TA = -30°C to +85°C) Master Mode (MS = VDD, PCLK2 = VDD, Cf = 20pF, Rf = 47kΩ) CL2 tWLC 0.7VDD 0.3VDD tWHC tsu DIO1 (SHL = V D D) DIO2 (SHL = V SS) tD tD DIO2 (SHL = V D D) DIO1 (SHL = V SS) tDF FRM tDM tDM 0.7VDD 0.3VDD M tF tR tWH1 CLK1 tWL1 tD12 tD21 CLK2 tWH2 tF 14 t su tDH tR tW H C 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 Master Mode Characteristic Symbol Min Typ Max Unit Data setup time tSU 20 – – µs Data hold time tDH 40 – – Data delay time tD 5 – – FRM delay time tDF -2 – 2 M delay time tDM -2 – 2 CL2 low level width tWLC 35 – – CL2 high level width tWHC 35 – – CLK1 low level width tWL1 700 – – CLK2 low level width tWL2 700 – – CLK1 high level width tWH1 2100 – – CLK2 high level width tWH2 2100 – – CLK1-CLK2 phase difference tD12 700 – – CLK2-CLK1 phase difference tD21 700 – – CLK1, CLK2 rise/fall time tR/tF – – 150 ns 15 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD Slave Mode (MS = VSS) tF tR tWLC1 CL2 (PLK2 = V SS) 0.7VDD 0.3VDD tWHC1 tSU tWHC2 tWLC CL2 (PLK2 = VDD) tR tF DIO1 (SHL = V DD) DIO2 (SHL = V SS) Input Data 0.7VDD 0.3VDD tH DIO1 (SHL = V DD) DIO2 (SHL = V SS) Onput Data Characteristics tHCL tD 0.7VDD 0.3VDD Symbol Min Typ Max Unit Note CL2 low level width tWLC1 450 – – ns PCLK2 = VSS CL2 high level width tWHC1 150 – – ns PCLK2 = VSS CL2 low level width tWLC2 150 – – ns PCLK2 = VDD CL2 high level width tWHL 450 – – ns PCLK2 = VDD Data setup time tSU 100 – – ns Data hold time tDH 100 – – ns Data delay time tD – – 200 ns Output data hold time tH 10 – – ns tR/tF – – 30 ns CL2 rise/fall time NOTE: Connect load CL = 30pF Output 30pF 16 (NOTE) 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 FUNCTIONAL DESCRIPTION RC Oscillator The RC Oscillator generates CL2, M, FRM of the S6B0107, and CLK1 and CLK2 of the S6B0108 by the oscillation resister R and capacitor C. When selecting the master/slave mode, the oscillation circuit is as following: Master Mode: In the master mode, use these terminals as shown below. S6B0107 R CR S6B0107 C Rf Cf 47KΩ 20pF R Open Internal Oscillation CR C Open External Clock External Clock Slave Mode: In the slave mode, stop the oscillator as shown below. S6B0107 R CR Open C Open VD D Timing Generation Circuit It generates CL2, M, FRM, CLK1 and CLK2 by the frequency from the oscillation circuit. Selection of Master/Slave (M/S) Mode – When M/S is "H", it generates CL2, M, FRM, CLK1 and CLK2 internally. – When M/S is "L", it operates by receiving M and CL2 from the mater device Frequency Selection (FS) To adjust FRM frequency by 70Hz, the oscillation frequency should be as follows: FS Oscillation Frequency H fOSC = 430kHz L fOSC = 215kHz In the slave mode, it is connected to VDD. 17 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD Duty Selection (DS1, DS2) It provides various duty selections according to DS1 and DS2. DS1 DS2 DUTY L L 1/48 H 1/64 L 1/96 H 1/128 H Data Shift & Phase Select Control Phase Selection It is a circuit to shift data on synchronization or rising edge, or falling edge of the CL2 according to PCLK2. PCLK2 Phase Selection H Data shift on rising edge of CL2 L Data shift on falling edge of CL2 Data Shift Direction Selection When M/S is connected to VDD, DIO1 and DIO2 terminal is only output. When M/S is connected to VSS, it depends on the SHL. MS SHL DIO1 DIO2 H H Output Output C1 → C64 L Output Output C64 → C1 H Input Output DIO1 → C1 → C64 → DIO2 L Output Input DIO2 → C64 → C1 → DIO1 L 18 Direction of Data 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 TIMING DIAGRAM 1/48 DUTY TIMING (MASTER MODE) Condition: DS1 = L, DS2 = L, SHL = H(L), PCLK2 = H ~ ~ ~ ~ C CLK1 1 2 3 1 2 1 2 3 46 47 48 ~ ~ ~ ~ M 48 ~ ~ ~ ~ DIO1 (DIO2) 46 47 ~ ~ FRM 3 ~ ~ CL2 V4 V0 V4 V1 V1 V5 V0 V4 V5 V4 V4 ~ ~ ~ ~ DIO2 (DIO1) V1 ~ ~ V1 V5 V4 ~ ~ C48 (C1) V4 ~ ~ V5 V0 V4 ~ ~ C47 (C2) V1 V1 V5 ~ ~ V1 V0 V1 V5 ~ V1 V4 ~ V1 ~ ~ C2 (C47) 64 ~ ~ CLK2 C1 (C48) 63 Relation of CL2 & DIO1 (DIO2) ~ ~ ~ ~ CLK2 DIO1 (DIO2) ~ ~ ~ ~ ~ ~ ~ ~ CL2 19 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD 1/128 DUTY TIMING (MASTER MODE) Condition: DS1 = H, DS2 = H, SHL = H(L), PCLK2 = H C CLK1 1 2 3 23 24 CLK2 1 2 ~ ~ ~ ~ V0 V1 ~ ~ V4 V1 V5 V0 V5 V5 V4 V1 V1 V5 Relation of CL2 & DIO1 (DIO2) ~ ~ ~ ~ ~ ~ 20 ~ ~ DIO1 (DIO2) ~ ~ CL2 ~ ~ CLK2 V4 V5 ~ ~ ~ ~ DIO2 (DIO1) V0 V1 ~ ~ V1 V4 ~ ~ V4 ~ ~ C128 (C1) V1 V5 ~ ~ C127 (C2) V4 ~ ~ V1 V1 V4 ~ ~ V4 V0 V0 V1 ~ ~ C2 (C127) 126 127 128 ~ ~ C1 (C128) 3 ~ ~ M 2 ~ ~ ~ ~ DIO1 (DIO2) 126 127 128 1 ~ ~ FRM 3 ~ ~ CL2 V4 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 1/48 DUTY TIMING (SLAVE MODE) Condition: PCLK2 = L, SHL = H(L) 1 2 46 47 48 1 2 46 47 48 CL2 ~ ~ ~ ~ ~ ~ M ~ ~ DIO1 (DIO2) ~ ~ ~ ~ V1 V1 V0 V0 ~ ~ C1 (C48) V4 ~ ~ V5 V1 V0 V1 ~ ~ C2 (C47) V4 V4 V4 V1 ~ ~ V5 V0 V1 V1 V1 ~ ~ V4 C47 (C2) V4 V4 ~ ~ V5 V1 ~ ~ V0 V4 V4 ~ ~ C48 (C1) V5 V5 DIO2 (DIO1) ~ ~ ~ ~ 21 S6B0107 64CH COMMON DRIVER FOR DOT MATRIX LCD POWER DRIVER CIRCUIT VD D V0 V0L/R R1 VD D V1 V1L/R R1 V2 R2 V3 To S6B0108 S6B0107 R1 V4 V4L/R R1 V5 V5L/R VR VEE VEE Relation of Duty & Bias Duty Bias RDIV 1/48 1/8 R2 = 4R1 1/64 1/9 R2 = 5R1 1/96 1/11 R2 = 7R1 1/128 1/12 R2 = 8R1 When duty factor is 1/48, the value of R1 & R2 should satisfy. R1/(4R1 + R2) = 1/8 R1 = 3kΩ, R2 = 12kΩ 22 64CH COMMON DRIVER FOR DOT MATRIX LCD S6B0107 APPLICATION CIRCUIT VDD CLK2 V5R/L 15 V5R/L CLK1 V3R/L CS3 CS2B CS1B DB0 -DB7 RSTB E R/W RS VSS CL V3R/L V2R/L M V2R/L VEE V0R/L FRM S6B0108 V0R/L S1 - S64 S1 - S64 SEG128 V5R/L V3R/L V2R/L VEE VSS CL CLK2 CLK1 S6B0108 M FRM CS3 CS2B CS1B DB0 -DB7 RSTB E R/W RS VDD 15 V0R/L 1/128 duty segment drive (S6B0108) interface circuit RS R/W E RSTB DB0 - DB7 CS1B CS2B CS3 15 15 5 CLK2 CLK1 M FRM COM128 VDD VEE VSS CL CLK2 CLK1 COM1 CS3 CS2B CS1B DB0 -DB7 RSTB E R/W RS VSS CL S6B0108 SEG1 S1 - S64 S1 - S64 VEE V5R/L S6B0108 M FRM VDD 15 CS3 CS2B CS1B DB0 -DB7 RSTB E R/W RS V3R/L V2R/L V0R/L LCD Panel CLK2 MS S6B0107 (slave) CLK1 2 FRM CLK1 VDD VDD V0 VSS R VEE V5R/L 5 V4R/L CR V1R/L VEE V5R/L V4R/L V1R/L VSS VDD C FRM V0R/L SHL MS FS V5 M V4 M V3 PCLK2 CL2 V2 S6B0107 (master) DS2 CLK2 CL2 V1 DIO2 DS1 open open open open open R VEE SHL KS2 DS1 FS C64 DIO2 PCLK2 C1 open open DIO1 CR V0R/L R1 C VDD C1 C64 C1 5 MPU 23