Gigabit Ethernet MAC from MorethanIP

1000Base-X PCS Core
for Actel FPGAs
Product Brief
Version 1.1 - February 2003
1 Introduction
With the deployment of Fast Ethernet to the desktop, Gigabit Ethernet has become the standard
backbone link to connect workgroup switches to backbone switches or access routers.
The IEEE802.3 specification defines, in Clause 36, a family of Physical Coding Sublayers (PCS)
collectively known as 1000Base-X. It covers three embodiments within this family:
•
1000Base-CX for two pairs balanced copper cabling,
•
1000Base-LX for long wavelength optical transmission
•
1000Base-SX for short wavelength optical transmission.
The 1000Base-X PCS Core is compliant with Clause 36 of the IEEE802.3 standard and implements
8B/10B coding, link synchronization, frame encapsulation generation / termination. The Core also
supports Auto-Negotiation (Clause 37 of IEEE802.3 standard), which is used to automatically, or
under user application software control, exchange ability information between the Core and the remote
end of the link and configure the Core to take the best advantage on the advertised features of the
Remote node.
The core can seamlessly connect to any industry standard Gigabit Ethernet SERDES (SERializer /
DESerializer) device via a Gigabit TBI (Ten Bit Interface) and to MAC Layer device with a standard
GMII (Gigabit Medium Independent Interface) or an industry standard RGMII (Reduced Gigabit
Medium Independent Interface), which provides a low pin, count 5-Bit DDR (Dual Data Rate) interface
that is typically implemented in Ethernet Layer 2 switches devices.
The Core implements a PHY Management interface with control and management registers as define
in Clause 22 of the IEEE 802.3 specification. The Core management interface address can be set via
an external 5-Bit address bus and a LED control interface can be used to monitor kink synchronization
and carrier sense.
The core is optionally delivered in generic synthesizable HDL (VHDL or Verilog) code, for use in Actel
Axcelerator FPGAs (Field Programmable Gate Arrays) or ASIC technologies, or as a FPGA netlist,
which provides a lower cost IP solution for Actel Axcelerator implementations.
1
Optimized for
1000Base-X PCS Core
for Actel FPGAs
Product Brief
Version 1.1 - February 2003
2 1000Base-X PCS core Features
•
Implements Clause 36 of 802.3-2000 specification for 1000Base-X family of PCS (Physical Coding
Sub-layer)
•
Implements PCS frame encapsulation / de-encapsulation with /S/, /T/ orderset insertion /
termination and /I/ Idle ordered set generation during inter-packet gap
•
Implements receive link synchronization state machine and 10-Bit data alignment from SERDES
with K28.5 character detection
•
Link coding implemented with 8B/10B providing DC balanced bitstream for efficient SERDES
operation
•
Implement User controllable 1000Base-X Auto-Negotiation (IEEE 802.3 Clause 37) which fully
programmable node ability register
•
Link timer used during Auto Negotiation programmable via the Core PHY Management interface
using a MorethanIP specific management register
•
MDIO Slave PHY Management interface which provides a standard interface for Core
configuration and management
•
Implements standard management register set as defined in Clause 22 of IEEE802.3 which
specific Extended registers for improved flexibility
•
Supports PHY isolation support to allow the implementation of a Hot Swappable PHY device and
provides control to for technology specific powerdown
•
PHY serial loopback support with standard MDIO command register
•
Programmable physical MDIO address via an external 5-Bit address
•
Programmable (Via PHY Management interface) GMII Loopback mode available for system test
•
Can be implemented in Actel Axcelerator FPGAs or ASICs
•
Can optionally be delivered in VHDL or Verilog source code or netlist which provides a lower cost
licensing option
•
Design Kit contains extensive Ethernet frame generators and checking models enabling fully
automated design verification and testing for standard compliance and error behavior, enabling for
fast turn-around design cycles
2
Optimized for
1000Base-X PCS Core
for Actel FPGAs
Product Brief
Version 1.1 - February 2003
3 Block Diagram
TBI
1000Base-X PMA
Interface
De-Encapsulation
Synchronization
8b/10b
Decoder
PHY Management
Interface
Encapsulation
SERDES
8b/10b
Encoder
MDIO
Slave
Configuration
1.25Gbps MDI
Transmit Serial
Interface
Transmit GMII
Interface
Auto Negotiation
1.25Gbps MDI
Receive Serial
Interface
Receive GMII
Interface
1000Base-X PCS
Management
Configuration
Status LEDs
Figure 1: 1000Base-X PCS Core Block Diagram
3
Optimized for
1000Base-X PCS Core
for Actel FPGAs
Product Brief
Version 1.1 - February 2003
4 Implementation Summary
Table 1: 1000Base-X PCS Core Complexity Summary
Complexity
Axcelerator
Device
AX500
Speed
Grade
-3
Requirement
(With 512-Byte FIFOs)
C-Cells
R-Cells
500
1100
(19%)
(20%)
Total
Utilization
RAM
20%
0
Performance
(Gigabit
Ethernet)
>130MHz
125MHz
5 1000Base-X PCS Core Design Kit Overview
Table 2: Design Kit Overview
Design and Simulation
Language
VHDL / Verilog or netlist for Actel Axcelerator FPGA
implementation.
Simulation
Configurable VHDL Testbench with embedded frame
generator and checker, providing an easy to use and robust
debugging environment.
Verification
Comprehensive test environment with Ethernet frame
generator and verification models for standard compliant and
errored frame generation and automated core behavior
verification.
Design Tools
Simulation
Modelsim Version 5.4d or higher
Synthesis
Exemplar Leonardo Spectrum 2002c or higher
Synplicity Synplify 7.1 or higher
Implementation
Actel Libero IDE (Integrated Design Environment) V2.2 or
higher, or Actel Designer R1-2002 or higher.
4
Optimized for
1000Base-X PCS Core
for Actel FPGAs
Product Brief
Version 1.1 - February 2003
6 References
1. IEEE 802.3 2002 Edition
7 Ordering Code
M T IP -1 0 0 0 _ P C S -la n g -a r c h
T e c h n o lo g y c o d e
Language code
Table 3: Language Code
Technology Code
BIN
Target Technology
Binary netlist for Actel Axcelerator FPGAs.
VHDL
Synthesizable generic VHDL source code for Actel
Axcelerator FPGAs or ASIC Implementations
VLOG
Synthesizable generic Verilog source code for Actel
Axcelerator FPGAs or ASIC implementations
Table 4: Technology Code
Technology Code
Target Technology
GEN
Source code option for Actel Axcelerator FPGAs or
ASIC implementations.
ACTL
Netlist for Actel Axcelerator FPGAs.
5
Optimized for
1000Base-X PCS Core
for Actel FPGAs
Product Brief
Version 1.1 - February 2003
8 Contact
MorethanIP
E-Mail
: [email protected]
Internet : www.morethanip.com
Europe
An der Steinernen Bruecke 1
D-85757 Karlsfeld
Germany
Tel
: +49 (0) 8131 333939 0
FAX
: +49 (0) 8131 333939 1
North America
2130 Gold Street Ste. 250
Alviso, CA 95002
USA
Tel
: +1 408 273 4567
Fax
: +1 408 273 4667
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Optimized for