Gigabit Fibre Channel Transport Core for Actel FPGAs Product Brief Version 2.1- September 2003 1 Introduction The Fibre Channel (FC) is logically a bi-directional point-to-point serial data channel, structured for high performance information transport. Physically, Fibre Channel is an interconnection of one or more point-to-point links. Each link end terminates in a Port. Ports are fully specified in the Physical Interface (FC-PI) specification and Framing and Signaling (FC-FS) specification. Fibre is a general term used to cover all physical media supported by Fibre Channel including optical fiber, twisted pair, and coaxial cable. Upper Level Protocols (ULP) FC-4 Mapping FC-3 Common Services FC-2 Signaling Protocol FC-1 Transmission Protocol (Physical Coding) FC-0 Physical Interface (PI) Framing and Signaling (FC-FS) Physical Interface and Media (FC-PI) Figure 1: Fibre Channel Function Hierarchy The Gigabit FC-2 Core provides a generic solution for 1Gbps Fibre Channel applications. The core is designed to support standard Fibre Channel applications such as point-to-point as well as fabric interconnect. On the Client side, the Core implements a 16-Bit FIFO interface running asynchronously from the Fibre Channel line clock. The FC-2 Layer provides services such as CRC generation / check, generate Fibre Compliant frames and buffer-to-buffer credit with necessary Fibre Channel timers and link set-up FC_PORT state machine. The FC-1 function implements the line coding (8B/10B), maintains DC balancing on the line, performs frame encapsulation, Fibre Channel Primitive Sequences generation / decoding, receive data alignment and link synchronization. On the line interface, the Core implements a standard 10-Bit interface that can be connected to any commercial SERDES (SERializer / DESerializer). The Core can be targeted to Actel programmable logic devices and ASIC technologies. 1 Optimized for Actel Gigabit Fibre Channel Transport Core for Actel FPGAs Product Brief Version 2.1- September 2003 2 Gigabit Fibre Channel Transport Core Features • Support Gigabit (1.06Gbps Baud rate) Fibre Channel applications • Fibre Channel logic operates at rates up 106.25MHz • Seamless interface to commercial SERDES device or Fibre Channel control via a standard 10-Bit interface (TBI) • Built-In client interface FIFO providing rate and clock decoupling • Simple 16-Bit or 32-Bit FIFO interface to user client application • CRC-32 checking at 106.25MHz wire speed using a multi-stage CRC calculation architecture • Optional CRC check and correction on the Core transmit path controllable on a frame by frame basis • Frame minimum and maximum length verification with long frame truncation and error indication • Link coding implemented with 8B/10B providing DC balanced bitstream for efficient SERDES operation • Maintain 8B/10B current disparity rules with automatic correction using positive or negative encoded EOF primitives • Negative encoded K28.5 Comma detection with automatic optical stream alignment • Implements FC-1 link synchronization with Loss of Synchronization indication • Implements Fibre Channel FC_PORT Port control state machine with programmable timers • Core configurable as N or F Fibre Channel port with automatic Fabric frames discard (N Port configuration) • Provide FC Transport support for point-to-point Fibre Channel applications • Support any Fibre Channel Traffic Class and Frame termination condition • Implement Buffer-to-Buffer Credit management with credit recovery, credit reset and automatic R_RDY, BB_SCr and BB_SCs primitives generation • Programmable 16-Bit credit recovery timer • Programmable Transmit and Receive FIFO depth • Implements processor control interface with 32-Bit statistic counters and configuration registers • Simple handshake user application FIFO interface with fully programmable depth and threshold levels • Can be implemented in Actel Axcelerator FPGAs or ASICs • Meets Gigabit Fibre Operation requirements when implemented in Military and Aeronautic devices 2 Optimized for Actel Gigabit Fibre Channel Transport Core for Actel FPGAs Product Brief Version 2.1- September 2003 3 Block Diagram Receive Client Interface 8b/10b Decoder RX Control CRC Check Link Sync Transmit FIFO TX Control CRC Check /Gen. 8b/10b Encoder Link Service Credit Buffer Management Configuration and Statistics Register Interface Figure 2: Gigabit Fibre Channel Transport Core Overview 3 Optimized for Actel 1.062Gbps Transmit Interface FC_PORT State Machine Primitive Generation Transmit Client Interface Primitive Decoding Receive FIFO 1.062Gbps Receive Interface FC-1 Comma Detection and Alignment FC-2 Gigabit Fibre Channel Transport Core for Actel FPGAs Product Brief Version 2.1- September 2003 4 Implementation Summary Table 1: Gigabit Fibre Channel Transport Complexity Summary Axcelerator Device AX1000 AX1000 Speed Grade Complexity (Temp Grade) C-Cells R-Cells -1 3600 2500 Military (30%) (41%) -3 3600 2500 Commercial (30%) (41%) Performance Requirement Total Utilization RAM 33% 6 >115MHz 106.25MHz 33% 6 >170MHz 106.25MHz 5 Deliverables Overview Table 2: Deliverables Overview Design and Simulation Language VHDL / Verilog or netlist for Actel Axcelerator FPGA implementation. Simulation Configurable VHDL Testbench with embedded frame generator and checker, providing an easy to use and robust debugging environment. Verification Comprehensive test environment with Ethernet frame generator and verification models for standard compliant and errored frame generation and automated core behavior verification. Design Tools Simulation Modelsim Version 5.7a or higher Synthesis Exemplar Leonardo Spectrum 2003a or higher Synplicity Synplify 7.3 or higher Implementation Actel Libero IDE (Integrated Design Environment) V5.0 or higher, or Actel Designer R1-2002 or higher. 4 Optimized for Actel Gigabit Fibre Channel Transport Core for Actel FPGAs Product Brief Version 2.1- September 2003 6 Ordering Code MTIP-1000_FC_TR-lang-arch Technology code Language code Table 3: Language Code Technology Code BIN Target Technology Binary netlist for Actel Axcelerator FPGAs. VHDL Synthesizable generic VHDL source code for Actel Axcelerator FPGAs or ASIC Implementations VLOG Synthesizable generic Verilog source code for Actel Axcelerator FPGAs or ASIC implementations Table 4: Technology Code Technology Code Target Technology GEN Generic source code. ACTL Netlist for Actel Axcelerator FPGAs. 5 Optimized for Actel Gigabit Fibre Channel Transport Core for Actel FPGAs Product Brief Version 2.1- September 2003 7 Contact MorethanIP E-Mail : [email protected] Internet : www.morethanip.com Europe An der Steinernen Bruecke 1 D-85757 Karlsfeld Germany Tel : +49 (0) 8131 333939 0 FAX : +49 (0) 8131 333939 1 6 Optimized for Actel