POS-PHY Level 3 PHY Interface for Actel FPGAs 1 Introduction 2

POS-PHY Level 3 PHY Interface
for Actel FPGAs
Product Brief
Version 1.0 – December 2002
1 Introduction
The Packet Over SONET-Physical Layer (POSPHY) Level 3 (L3) is defined to connect a Link
Layer device which implements packet based
protocols, to a Physical device (e.g. SONETSDH Framer) at speed up to 3.2Gbps
(Exceeding OC48 Rates). The POS-PHY
interface specifies the PHY-LINK interface.
•
Optional Parity generation / checking on the
POS-PHY Ingress / Egress interfaces
•
Programmable Single PHY or Multi PHY
(MPHY) operation with In-Band addressing
The POS-PHY Level-3 specification from the
Saturn Group, originally meets the need for
system designers to integrate standard POS
(Packet Over Sonet) Physical devices Link Layer
applications. The POS-PHY interface has been
developed to provide a simple, versatile and
easy to use interface for packet transfer
applications. The POS-PHY interface has then
been used in a large variety of applications and
has become an essential block in
Telecommunication applications.
•
Programmable number of PHY port from 1
(Single PHY operation) to 256
•
Round robin Ingress port arbitration when
used in MPHY mode to guarantee fairness
between the multiple PHYs
•
Advanced management options with error
handling, POS-PHY protocol violation check
and fully user programmable oversized
packet discard feature
The POS-PHY Level-3 Macrocell from
MorethanIP is designed for ease of use
performance.
•
Packet transfers in multiple programmable
data sections supported on Egress and
Ingress to increase flexibility and reduce
application FIFO requirements
•
Programmable delay insertion between
consecutive packets on Ingress for
Macrocell adaptation to the Link Layer
device POS-PHY performance
•
Simple User PHY application Master / Slave
interface on Egress / Ingress with a two
signals handshake simplifying the PHY
application design and integration
•
Delivered with a complete and
programmable simulation environment
•
Scripts for Exemplar / Modelsim synthesis /
simulation tools provided
•
Optionally Delivered in VHDL or Verilog
source code for easy integration and with a
platform independent JAVA configuration
utility or as a netlist for Actel FPGAs
•
Optimized FIFO with Actel specific
embedded memory blocks for high
integration and speed
2 Features
•
Compliant with PMC-Sierra POS-PHY Level
3 Saturn Compatible Interface for POS-PHY
Devices (Compatibility Specification – PMC
1980495)
•
Programmable POS-PHY Level-3 data width
(8, 32-Bit) or Pseudo 16-Bit non standard
pseudo POS-PHY Level-3 interface
•
Meets 104MHz performance and 32-Bit
interface operation supporting 3.2Gbps
(Exceeding OC48 requirements) packet rate
transfers
•
•
Selectable Byte Level or Packet Level
transfers supported with Polled or Direct
status indication and User programmable
FIFO thresholds
Packet rate decoupling with fully User
programmable (Depth) FIFOs
1
Optimized for
POS-PHY Level 3 PHY Interface
for Actel FPGAs
Product Brief
Version 1.0 – December 2002
3 Block Diagram
MPHY Port 1
Port Address
POS-PHY Interface I/Os
Parity
Generation
MPHY Port N
+1
Round Robin
Arbiter
Control
State-Machine
MPHY Port 1
Port Arbitration
Direct Status
Multiplexed Polling
FIFO Status
MPHY Port N
Parity
Check
Decoder
Control
State-Machine
Figure 1: Block Diagram
2
Optimized for
POS-PHY Level 3 PHY Interface
for Actel FPGAs
Product Brief
Version 1.0 – December 2002
4 Implementation Summary
Table 1: Implementation Summary - Axcelerator
Complexity
Axcelerator
Device
AX500
Speed
Grade
-1
(32-Bit single PHY Interface with 1024-Byte FIFOs)
C-Cells
R-Cells
489
738
(9%)
(28%)
Total
Utilization
RAM
19%
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Performance
Requirement
>115MHz
104MHz
5 Design Kit Overview
Table 2: Design Database Overview
Design and Simulation
Language
VHDL / Verilog or netlist for Actel Axcelerator FPGA
implementation.
Simulation
Configurable VHDL Testbench with embedded frame
generator and checker, providing an easy to use and robust
debugging environment.
Verification
Comprehensive test environment with Ethernet frame
generator and verification models for standard compliant and
errored frame generation and automated core behavior
verification.
Design Tools
Simulation
Modelsim Version 5.4d or higher
Synthesis
Exemplar Leonardo Spectrum 2002c or higher
Synplicity Synplify 7.1 or higher
Implementation
Actel Libero IDE (Integrated Design Environment) V2.2 or
higher, or Actel Designer R1-2002 or higher.
6 References
•
PMC-Sierra POS-PHY Level 3 Saturn Compatible Interface for POS-PHY Devices
(Compatibility Specification – PMC 1980495)
3
Optimized for
POS-PHY Level 3 PHY Interface
for Actel FPGAs
Product Brief
Version 1.0 – December 2002
7 Ordering Code
MTIP-PL3_PHY-lang-arch
Technology code
Language code
Table 3: Language Code
Technology Code
BIN
Target Technology
Binary netlist for Actel Axcelerator FPGAs.
VHDL
Synthesizable generic VHDL source code for
Actel Axcelerator or ASIC implementations
VLOG
Synthesizable generic Verilog source code for
Actel Axcelerator or ASIC implementations
Table 4: Technology Code
Technology Code
Target Technology
GEN
Source code option for Actel Axcelerator or ASIC
implementations.
ACTL
Netlist for Actel Axcelerator FPGAs.
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Optimized for
POS-PHY Level 3 PHY Interface
for Actel FPGAs
Product Brief
Version 1.0 – December 2002
8 Contact
MorethanIP
E-Mail
: [email protected]
Internet : www.morethanip.com
Europe
An der Steinernen Bruecke 1
D-85757 Karlsfeld
Germany
Tel
: +49 (0) 8131 333939 0
FAX
: +49 (0) 8131 333939 1
North America
2130 Gold Street Ste. 250
Alviso, CA 95002
USA
Tel
: +1 408 273 4567
Fax
: +1 408 273 4667
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Optimized for