PF885-03 SED1353 SED1353 STN Color LCD Controller ● ● ● ● Color/monochrome LCD controller Pin convertible with SED1352 (monochrome LCD controller) Low operating voltage (2.7V to 5.5V) Supports interface with various types of MPUs ■ DESCRIPTION SED1353 is a dot matrix graphics LCD controller capable of supporting up to 1024 × 1024 (monochrome display) resolution. 256-color-display out of 4096 colors and monochrome display in up to 16-level gray scale display are available. SED1353 allows easy connection with MC68000 families and other 8/16 bits MPUs. As for memory for the display, it supports up to 128 KB SRAM. Low operating power of SED1353 makes it a most suitable color LCD controller not only for factory automation equipments but also for small hand held equipments, too. ■ FUNCTIONS ● 16-bit, 16 MHz and MC68xxx MPU interface. ● READY or WAIT# terminal controlled 8/16 bits MPU interface. ● Either index register approah or direct mapping can be selected when making access to the internal register. ● Support a crystal oscillator or external clock input. ● 8/16 bits SRAM interface. ● Designed to operate at low power. ● Designed for two types of power save mode. ● Setup of virtual display sreen is available. ● Supports split-screen (displays two different pages on a single screen). ● Display mode: Black and white binary display. 2/4 bits per pixel, 4/16-levelgray-scale-display. ● Display memory interface 128KB (one 64K × 16 SRAM) 128KB (two 64K × 8 SRAM) 64KB (two 32KB × 8 SRAM) 40KB (8K x 8 SRAM and 32K × 8 SRAM) 32KB (one 32K × 8 SRAM) 16KB (two 8K × 8 SRAM) 8KB (one 8K × 8 SRAM) ● LCD panel supported: Single screen drive STN panel Dual screen drive STN panel ● Maximum number of vertical lines: 1024 lines (for single screen drive) 2048 lines (for dual screen drive) ● SED1353D0A: Chip shipped. ● SED1353F0A: QFP5-100 pin ● SED1353F1A: QFP15-100 pin 2/4/8 bits per pixel, 4/16/256-level-gray-scaledisplay. 1 SED1353 ■ SYSTEM CONFIGURATION DIAGRAM CLOCK DATA CONTROL MUP SED1353 LCD PANEL ADDRESS 80xx Z80 68xxx SRAM ■ SYSTEM INTERFACE 16-bit MC68xxx MPU & 16KB SRAM (2 of 8K × 8) MC68xxx SED1353 A20 to A23 FC0 to FC1 Decoder MEMCS# A14 to A16 VD8–15 Decoder IOCS# VD0–7 VWE# A10 to A19 A1 to A19 AB1 to AB19 D0 to D15 DB0 to DB15 READY DTACK# UDS# AB0 LDS# BHE# VCS0# IOR# VCS1# VA0–12 IOW# AS# R/W# WE# 64Kbit WE# 64Kbit CS# CS# WE# WE# Note: Example implemation, actual may vary 8-bit Z80 MPU & 16KB SRAM (2 of 8K × 8) Z80 Decoder MREQ# MI# A10 to A15 Decoder IORQ# A0 to A15 D0 to D7 WAIT# WR# RD# RESET# Note: Example implemation, actual may vary 2 SED1353 MEMCS# VD0–7 IOCS# VWE# AB0 to AB15 DB0 to DB7 READY MEMW# MEMR# VCS0# IOR# VCS1# IOW# VA0–12 RESET 64Kbit CS# 64Kbit CS# SED1353 16-bit 8086 MPU & 64KB SRAM (2 of 32K × 8) CLK READY RESET# RDY 8284A 8086 (Maximum mode) CLK S2# READY S1# 8288 CLK MRDC# S2# S1# AMWC# IORC# S0# AIOWC# DEN DT/R ALE RESET# S0# A16 to A19 BHE# AD0 to AD15 MEMR# VD0–7 VWE# MEMW# IOR# IOW# AB16 to AB19 Decoder A16 SED1353 M/IO# BHE# AB0 to AB15 VCS0# VA0–14 BHE# A0 to A16 MEMCS# STB IOCS# D0 to D15 T OE Transceiver DB0 to DB15 WE# 256kbit CS# WE# 256kbit CS# VCS1# RESET VD8–15 READY Note: Example implemation, actual may vary 8-bit ISA Bus & 40KB SRAM (1 of 8K × 8 & 1 of 32K × 8) 8–Bit ISA Bus REFRESH SED1353 SA13 to SA16 MEMCS# VD0–7 VWE# MEMW# Decoder SMEMW# SMEMR# MEMR# READY IOCHRDY SD0 to SD7 DB0 to DB7 SA0 to SA19 SA10 to SA15 AEN IOW# IOR# RESET# SA(1or4) to SA9 Decoder AB0 to AB19 VCS0# IOCS# VA0–14 IOW# IOR# RESET optional WE# 64 kbit CS# WE# 256 kbit CS# Decoder 0WS# VCS1# Note: Example implemation, actual may vary 16-bit ISA Bus & 128KB SRAM (1 of 128K × 8) 16–bit ISA Bus REFRESH SED1353 SA14 to SA16 MEMCS# Decoder SMEMW# MEMW# VWE# SMEMR# MEMR# READY IOCHRDY 1 Mbit SD0 to SD15 DB0 to DB15 SA0 to SA19 AB0 to AB19 SA10 to SA15 Decoder AEN SA(1or4) to SA9 IOCS# IOW# IOW# IOR# SBHE# IOR# BHE# RESET# IOCS16# WE# VCS0# LB# VCS1# UB# VA0–15 RESET A0–15 VD0–7 I/O1–8 VD8–15 I/O9–16 Decoder LA17 to LA23 MEMCS16# Decoder Note: Example implemation, actual may vary 3 SED1353 ■ RESOLUTIONS SUPPORTED Example Display Size Display RAM Monochrome 8KB 320 × 200 256 × 128 128 × 128 — 1 of 8K × 8 8-bit 8-bit 16KB 512 × 256 320 × 200 200 × 160 160 × 100* 2 of 8K × 8 8-bit 8-bit/16-bit 16-bit 16-bit 32KB 512 × 512 512 × 256 256 × 256 192 × 100* 1 of 32K × 8 8-bit 8-bit 40KB 1024 × 320 512 × 320 320 × 256 320 × 128* 1 of 8K × 8 & 1 of 32K × 8 8-bit 8-bit 64KB 1024 × 512 512 × 512 512 × 256 256 × 256* 2 of 32K × 8 8-bit 8-bit/16-bit 16-bit 16-bit X 128KB Y 1024 × 1024 4 Grays/ Colors X 16 Grays/ Colors Y X 1024 × 512 Y 512 × 512 SRAM Type 256 Colors* X CPU Interface SRAM Interface Y 512 × 256* 1 of 64K × 16 16-bit 16-bit 2 of 64K × 8 16-bit 16-bit Note: * 256 colors must use 16-bit SRAM interface The above display sizes depend on number of gray scale (colors) and memory capacity. ■ BLOCK DIAGRAM Control Registers IOR#,IOW#,IOCS#, MEMCS#,MEMR#, MEMW#,BHE#, AB[19:0] Bus Signal Translation Port Decoder LCDENB Sequence Controller Lookup Table Memory Decoder READY DB[15:0] Address Generator Data Bus Conversion MPU/CRT Selctor Display Data Formatter Timing Generator Power Save VD[15:0] VA[15:0] VSC0#,VSC1# VWE# OSC2 OSC1 4 VOE# SRAM Interface Oscillator LCD Panel Interface UD[3:0] LD[3:0] LP,YD, XSCL, WF(XSCL2) SED1353 ■ OVERVIEW OF THE FUNCTIONAL BLOCKS BUS Signal Translation This block converts the SED1353 internal bus so that it may be used for MC68000 series MPU or READY terminal controlled MPU series. This conversion is done through the setting of VD2 terminal from the Configuration Option (see page 11). Control Register This register block consists of 16 types of control registers. Access to these registers are available either through the direct mapping approach or index register approach. Sequence Controller This block generates horizontal and vertical display timing being set up in the internal register. LCD Panel Interface This block selects a gray scale for passive monochrome and color LCD panels through timing, then outputs data to the LCD panel. Lookup Table This block consists of each RGB 16 × 4-bit palettes. In the monochrome gray scale mode, a gray scale pattern can be specified using the “Green” palette. In the color mode, all RGB palettes are used to set up a color pattern out of 4096 colors. Port Decoder This decoder validates a given I/O cycle through setup of VD1 terminal, VD2 to VD4 terminals, IOCS # terminal and address lines AB9 to 1 from the Configuration Option (see page 11). Memory Decoder This decoder validates a given memory cycle through setup of VD15 to VD13, MEMCS # terminal and address lines AB19 to 17 from the Configuration Option (see page 11). Data Bus Conversion This block connects an external data bus (8 or 16 bits) to the internal data bus through the setup of VDD terminal from the Configuration Option (see page 11). Address Generator This block generates the address used to validate access to the display memory. MPU/CRT Selector This block arbitrates between MPU accees to the display memory and an access to it for LCD display. Display Data Fomatter This block reads data from the display memory, then outputs it in the format consistant with the specified display mode (monochrome/color, levels of gray scale and number of colors). Clock Inputs/Timing This block generates a master clock (mclk) conforming to the specified gray scale leves 1, number of colors and display memory interface. The following master clocks are available depeding on conditions specified: – mclk = input clock: 16-grays/16-color mode (8-bit display memory) or 256-color mode (16-bit display memory). – mclk = 1/2 input clock: B&W, 4-grays/4-color mode (8-bit display memory), or 16-grays scale/16-color mode (16-bit display memory). – mclk = 1/4 input clck: B&W, 4-grays scale/4-color mode (16-bit display memory). Pixel clock = input clock = fOSC SRAM Interface This block generates the interface signal to the display memory (SRAM). 5 SED1353 ■ DC CHARACTERISTICS ● Absolute Maximum Ratubgs Item Supply voltage Input voltage Output voltage Storage voltage Code VDD VIN VOUT TSTG Rating VSS – 0.3 + 6.0 VSS – 0.3 to VDD + 0.5 VSS – 0.3 to VDD + 0.5 –65 to 150 Unit V V V °C Conditions VSS = 0 V Min 2.7 VSS ● Recommended Operation Conditions Item Supply voltage Input voltage Operating current Operating voltage Code VDD VIN IOPR TOPR Max 5.5 VDD –40 Typ 3.0/3.3/5.0 — 4.5/5.0/11 25 Min Typ Max 0.8 0.4 0.3 fOSC = 6MHz, 256 colors 85 Unit V V mA °C ● Input Characteristics 6 Item Low level input voltage Code VIL High level input voltage VIH Positive threshold VT+ Negative threshold VT– Hysteresis voltage VH Leak voltage Input pin capacity Pulldown resistance Pulldown resistance Pulldown resistance IIZ CIN RPD RPD RPD Conditions VDD = 4.5V VDD = 3.0V VDD = 2.7V VDD = 5.5V VDD = 3.6V VDD = 3.3V VDD = 5.0V VDD = 3.3V VDD = 3.0V VDD = 5.0V VDD = 3.3V VDD = 3.0V VDD = 5.0V VDD = 3.3V VDD = 3.0V — f = 1MHz, VDD = 0V VDD = 5.0V, VI = VDD VDD = 3.3V, VI = VDD VDD = 3.0V, VI = VDD 2.0 1.3 1.2 V 2.4 1.4 1.3 0.6 0.5 0.4 0.1 0.1 0.1 –1 50 90 100 Unit V V V V 100 180 200 1 12 200 360 400 µA pF kΩ kΩ kΩ SED1353 ● Output Characteristics Item Low level output voltage Type 1: TS1D2, CO1 Type 2: TS2 Type 3: TS3, CO3, CO3S Low level output Type 1: TS1D2, CO1 Type 2: TS2 Type 3: TS3, CO3, CO3S Low level output voltage Type 1: TS1D2, CO1 Type 2: TS2 Type 3: TS3, CO3, CO3S High level output voltage Type 1: TS1D2, CO1 Type 2: TS2 Type 3: TS3, CO3, CO3S High level output voltage Type 1: TS1D2, CO1 Type 2: TS2 Type 3: TS3, CO3, CO3S High level output voltage Type 1: TS1D2, CO1 Type 2: TS2 Type 3: TS3, CO3, CO3S Output leak current Output pin capacity Bi-directional pin capacity Code VOL (5.0V) VOL (3.3V) VOL (3.0V) VOH (5.0V) VOH (3.3V) VOH (3.0V) IOZ COUT CBID Conditions VDD = Min Min Typ Max Unit IOL = 4mA IOL = 8mA IOL = 12mA VDD = Min 0.4 V IOL = 2mA IOL = 4mA IOL = 6mA VDD = Min 0.3 V IOL = 1.8mA IOL = 3.5mA IOL = 5mA VDD = Min 0.3 V IOL = –4mA IOL = –8mA IOL = –12mA VDD = Min VDD – 0.4 V IOL = –2mA IOL = –4mA IOL = –6mA VDD = Min VDD – 0.3 V IOL = –1.8mA IOL = –3.5mA IOL = –5mA — f = 1MHz, VDD = 0V f = 1MHz, VDD = 0V VDD – 0.3 V –1 1 12 12 µA pF pF XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 SED1353F0A VD6 VD5 VD4 VD3 VD2 VD1 VD0 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 RESET AB19 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DB7 VSS VDD DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 WF/XSCL2* LP YD LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 VCS1# VCS0# VWE# VA15 VA14 VA13 VA12 VA11 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 VDD VSS VD7 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ■ SED1353F0A PIN LAYOUT * Pin No.80 = WF: Supports every display mode except for 8-bit single color panel interface (format 1). * Pin No.80 = XSCL2: Supports 8-bit single color panel interface (format 1). 7 SED1353 YD LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 VCS1# VCS0# VWE# VA15 VA14 VA13 VA12 VA11 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ■ SED1353F1A PIN LAYOUT 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 LP WF/XSCL2* XSCL LCDENB VOE# IOCS# IOW# IOR# MEMCS# MEMW# MEMR# READY BHE# OSC1 OSC2 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VSS VDD VDD VSS VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0 RESET AB19 AB18 AB17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 SED1353F1A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 * Pin No. 77 = WF: Supports every display mode except for 8-bit single color panel interface (format 1). * Pin No. 77 = XSCL2: Supports 8-bit single color panel interface (format 1). 80 VSS VDD VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VA11 VA12 VA13 VA14 VA15 VWE# VCS0# VCS1# UD3 UD2 UD1 UD0 90 WF/XSCL2* XSCL LD3 LD2 LD1 LD0 LP YD ■ SED1353D0A PIN LAYOUT Dummy Pad 70 VD7 100 VD6 LCDENB 60 VD5 VOE# VD4 IOCS# VD3 IOW# VD2 IOR# VD1 MEMCS# VD0 MEMW# MEMR# VA10 110 VA9 50 SED1353D0A READY BHE# VA8 VA7 OSC1 VA6 OSC2 VA5 DB0 VA4 VA3 DB1 120 40 DB2 VA2 DB3 VA1 DB4 VA0 DB5 RESET DB6 AB19 DB7 1 10 20 30 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 DB15 DB14 DB13 DB12 DB11 DB10 VDD = = = = DB8 Chip Size Chip Thickness Pad size Pad Pitch VSS DB9 Dummy Pad 5.030 mm x 5.030 mm 0.400 mm 0.090 mm x 0.090 mm 0.126 mm ( Min.) * Pad No. 97 = WF: Supports every display mode except for 8-bit single color panel interface (format 1). * Pad No. 97 = XSCL2: Support 8-bit single color panel interface (format 1). 8 SED1353 ■ PIN DESCRIPTION I = Input O = Output I/O = Input and output P = Power supply ● Bus Interface Pin name DB0–DB15 Type I/O F0A Pin No. 94–100, 1, 4–11 F1A Pin No. 91–98, 1–8 D0A Pin No. 118–119, 121–125, 128, 4–11 13 AB0 I 12 9 AB1–AB19 I 13–31 10–28 BHE# I 91 88 14–20, 22–30, 32–33, 36 113 IOCS# IOW# I I 84 85 81 82 103 104 IOR# I 86 83 106 MEMCS# I 87 84 107 MEMW# I 88 85 109 MEMR# I 89 86 110 READY O 90 87 112 RESET I 32 29 37 Description Connects to the system data bus. In 8-bit bus mode, DB8 to DB15 connect to VD0. When MC68000 MPU interface is used, it connects to UDS#pin (Upper Data Strobe). When other bus interface is used, it connect to the system address bus. Connects to the system bus. When MC68000 MPU interface is used, it connects to LDS# pin (Lower Data Strobe). When other bus interface is used, this pin functions as the bus high enable input on the 16-bit system. On 8-bit bus system, it connects to VDD. Select one of 15 internal registers. When MC68000 MPU interface is used, it connects to R/W# pin. This input pin selects either read cycle (active high) or write cycle (active low) for data transmission. When other bus interface is used, it is active low to write data to the internal register. When MC68000 MPU interface is used, it connects to AS# pin. On the address bus, this input pin indicates an valid address is available. When other bus interface is used, this pin is active low and reads data from the internal register. Accepts active low inputs, it displays access attempts to the display memory. Accepting active low inputs, it writes dat a to the display memory. When MC68000 MPU interface is used, it connects to VDD. Accepting active low inputs, it reads data from the display memory. When MC68000 MPU interface is used , it connects to VDD. When MC68000 MPU interface is used, it is connected with DATCK# pin. As data transfer completes, it is turned low. When other system bus interface is used, it outputs low if the system wait status is needed. As data transfer completes, READY state is reset to return to High-Z. Accepting active high, it turns all signals non-active. ● Display Memory Interface Pin name VD0–VD15 Type I/O F0A Pin No. 44–51, 54–61 F1A Pin No. D0A Pin No. 41–48, 51–58 54–55, 57–61, 64, 68–75 VA0–VA15 O 33–43, 62–66 VCS1# O 69 30–40, 59–63 38–40, 42–43, 45–46, 48–49, 51–52, 77–81 66 84 VCS0# O 68 65 83 VWE# O 67 64 82 VOE# O 83 80 102 Description They connect to the display memory data bus. When 16-bit interface is used, VD0 to VD7 are connected to the display memory buses in even byte address, and VD8 to VD15 are connected to those in odd memory address. When RESET is turned to high, output drivers of these pins are set to High-Z. At the falling edge of RESET, values of VD0 to VD15 are latched by this IC allowing to set various hardware options. They connect to the display memory address buses. It outputs active low chip select signal to the second SRAM or SRAMs at odd byte address. It outputs active low chip select signal to the first SRAM or SRAMs at even byte address. It outputs active low used when writing data to the display memory. It is connected to the SRAM WE# pin. It outputs active low used for reading data from the display memory. It is connected to the SRAM OE# pin. 9 SED1353 ● LCD Interface Type UD3–UD0 LD3–LD0 XSCL FPDI-1* Pin name UD3–UD0 LD3–LD0 FPSHIFT LP WF/XSCL2 Pin name O F0A Pin No. 70–73 74–77 81 F1A Pin No. 67–70 71–74 78 D0A Pin No. 86–89 90–93 100 FPLINE O 79 76 96 MOD O 80 77 97 O O 78 82 75 79 94 101 O FPSHIFT2 YD LCDENB FPFRAME — Description Display data in the dual panel mode. When 4-bit single panel is employed, LD3 to LD0 are driven to low. Shift clock of display data. Aft the falling edge of this signal, data is shifted to X driver on the LCD. Latch clock of display data. At the falling edge of this signal, line data on the LCD X driver is latched and used for turning on the LCD Y driver. The second shift clock for 8-bit single color panel (format) mode. In other modes, it becomes LCD back plane bias signal. This output is toggled one time at each frame. (Setup of WF signal output may be changed from the internal register.) Vertical scan start signal. LCD enable signal. Using this signal, you can externally turn off the panel power and back light. *: Conforming to the VESA flat panel interface standard. ● Clock Input Pin name OSC1 Type I F0A Pin No. 92 F1A Pin No. 89 D0A Pin No. 115 OSC2 O 93 90 116 F0A Pin No. 3, 53 2, 52 F1A Pin No. 50, 100 49, 99 D0A Pin No. 3, 67 1, 65 Description When 2-pin crystal is used for the clock input, this pin is connected to the crystal along with OSC2. And, when an external oscillator circuit is used as the clock source, this pin inputs the clock. When 2-pin crystal is used for the clock input, this pin is connected to the crystal along with OSC2. And, when an external oscillator circuit is used as the clock source, it is turned to NC. ● Power Supply Pin name VDD VSS 10 Type P P Description Power supply pin. Grounding pin. SED1353 ■ OPTIONAL HARDWARE CONFIGURATION During the RESET, SED1353 latches state of SRAM data bus (1 or 0) to offer an optimum hardware configuration to the user system. Since SED1353 has a pull down resistor inside the IC, if the following “1” applies, a 10kΩ external pull up resistor must be provided . In case of “0”, the external pull up resistor is not required. Pin name VD12–VD4 Hardware configuration according to the pin status (1 or 0) 1 0 16-bit host bus interface 8-bit host bus interface Direct mapping I/O access Index mapping I/O access MC68000 MPU interface READ (WAIT#) pin controlled MPU and bus interface When 16-bit bus interface is used, there is data swap When 16-bit bus interface is used, there is not data swap between higher-order data byte and lower-order data between higher-order and lower-order data byte. byte. I/O mapping address select bit [9:1] VD15–VD13 Initial bits used for selecting the address mapping of I/O resistor. hey correspond to the address bit [9:1] of MPU interface. When valid address for I/O cycle is generated, the internal decoder is controlled so that addressing is as specified with these bits. Memory mapping address select bit [3:1] VD0 VD1 VD2 VD3 Initial bits used for selecting address mapping of memory. They correspond to address bit [19:17] of the MPU interface. When valid address for memory cycle is generated, the internal decoder is controlled so that addressing is done as specified with these bits. “Valid memory cycle” denotes the the access where MEMCS”# is turned low. ■ COMPARISON BETWEEN SED1353 AND SED1352 SED1353 is upward convertible and pin convertible with f SED1352. Thus, up grading from SED1352 to 1353 is easy in terms of both hardware and software. The following list main difference between SED1353 and SED1352. For detailed specifications, refer to respective technical manual. ● Functional Comparison Specifications Color display Monochrome display Display data format Setup of vertical scan period done in horizontal direction Look-up Table SED1353 • 4/16/256 colors • black/white binary. • 4/16-level gray scale. • 4/8 bits single/dual monochrome. • 4/8/16 bits signal/dual color. Programmable. SED1352 • Not available • Not available. • 4/16-level gray scale. • 4/8 bits single/dual monochrome. • Not available. Not available. • 3 × 16, 4-bit width. • 1 × 16, 4-bit width. ● Modifications or Additions done on the Internal Register (See SED1353 technical manual for the detail) AUX [01h] AUX [0Eh] bit 2 LCD Data Width bit 0 bit 4 bit 3 Gray Shade/Color bit 5 bit 6 AUX [03h] bit 7 bit 1 Color Mode bit 2 BW/256 colors AUX [0Fh] AUX [0Ch] bit 0:7 Horizontal Non-Display Period bit 4 bit 5 bit 6 bit 7 ID Bit/RGB Index Bit 0 ID Bit/RGB Index Bit 1 Green Bank Bit 0 Green Bank Bit 1 Blue Bank Bit 0 Blue Bank Bit 1 Red Bank Bit 0 Red Bank Bit 1 11 SED1353 NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. © Seiko Epson Corporation 1999 All right reserved. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ELECTRONIC DEVICES MARKETING DIVISION Electronic Device Marketing Department IC Marketing & Engineering Group ■ Electronic devices information on the Epson WWW server. http://www.epson.co.jp ED International Marketing Department I (Europe, U.S.A) 421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: 042–587–5812 FAX: 042–587–5564 ED International Marketing Department II (ASIA) 421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: 042–587–5814 FAX: 042–587–5110 12 Revised September, 1998 Printed in Japan H