NEC UPD75P3036GC-3B9

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75P3036
4-BIT SINGLE-CHIP MICROCONTROLLER
The µ PD75P3036 replaces the µ PD753036’s internal mask ROM with a one-time PROM or EPROM.
Because the µPD75P3036 supports programming by users, it is suitable for use in prototype testing for system
development using the µ PD753036 and for use in small-scale production.
*
Caution The µ PD75P3036KK-T is not designed to guarantee the reliability required for use in massproduction. Please use it only for performance evaluation during testing and test production runs.
Detailed descriptions of functions are provided in the following document. Be sure to read the document
before designing.
µ PD753036 User’s Manual : U10201E
FEATURES
• Compatible with µPD753036
• Internal PROM: 16384 × 8 bits
• µPD75P3036KK-T
: Reprogrammable (ideally suited for system evaluation)
• µPD75P3036GC, 75P3036GK : One-time programmable (ideally suited for small-scale production)
• Internal RAM: 768 × 4 bits
• Can operate in the same power supply voltage as the mask version µPD753036
• VDD = 1.8 to 5.5 V
• LCD controller/driver
• A/D converter
Caution
Mask-option pull-up resistors are not provided in this device.
ORDERING INFORMATION
Part Number
µ PD75P3036GC-3B9
Package
Internal PROM
80-pin plastic QFP
Quality Grade
One-time PROM
Standard
One-time PROM
Standard
EPROM
Not applicable
(14 × 14 mm, 0.65-mm pitch)
µ PD75P3036GK-BE9
80-pin plastic TQFP
(fine pitch) (12 × 12 mm, 0.5-mm pitch)
*
µ PD75P3036KK-T
80-pin ceramic WQFN
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions.
The information in this document is subject to change without notice.
Document No. U11575EJ1V0DS00 (1st edition)
(Previous No. IP-3657)
Date Published November 1996 P
Printed in Japan
The mark
* shows major revised points.
©
1996
µ PD75P3036
Functional Outline
Parameter
Function
• 0.95, 1.91, 3.81, 15.3 µ s (main system clock: during 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7 µ s (main system clock: during 6.0-MHz operation)
• 122 µ s (subsystem clock: during 32.768-kHz operation)
Instruction execution time
Internal memory
PROM
16384 × 8 bits
RAM
768 × 4 bits
General purpose register
• 4-bit operation: 8 × 4 banks
• 8-bit operation: 4 × 4 banks
Input/
output
port
CMOS input
8
CMOS input/output
20
Bit port output
8
Also used for segment pins
N-ch open-drain
input/output pins
8
13 V withstand voltage
Total
44
*
LCD controller/driver
On-chip pull-up resistors can be specified by using software: 27
• Segment selection:
• Display mode selection:
*
2
12/16/20 segments (can be changed to bit port output
in unit of 4; max. 8)
Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias),
1/3 duty (1/3 bias), 1/4 duty (1/3 bias)
Timer
5 channels
• 8-bit timer/event counter: 3 channels
(16-bit timer/event counter, carrier generator, timer with gate)
• Basic interval/watchdog timer: 1 channel
• Watch timer: 1 channel
Serial interface
• 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit
• 2-wire serial I/O mode
• SBI mode
A/D converter
8-bit resolution: 8 channels
Bit sequential buffer (BSB)
16 bits
Clock output (PCL)
• Φ, 524, 262, 65.5 kHz (main system clock: during 4.19-MHz operation)
• Φ, 750, 375, 93.8 kHz (main system clock: during 6.0-MHz operation)
Buzzer output (BUZ)
• 2, 4, 32 kHz (main system clock: during 4.19-MHz operation
or subsystem clock: during 32.768-kHz operation)
• 2.86, 5.72, 45.8 kHz (main system clock: during 6.0-MHz operation)
Vectored interrupt
External: 3, Internal: 5
Test input
External: 1, Internal: 1
System clock oscillator
• Ceramic or crystal oscillator for main system clock oscillation
• Crystal oscillator for subsystem clock oscillation
Standby function
STOP/HALT mode
Power supply voltage
VDD = 1.8 to 5.5 V
Package
• 80-pin plastic QFP (14 × 14 mm)
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
• 80-pin ceramic WQFN
µ PD75P3036
CONTENTS
1. PIN CONFIGURATION (Top View) ............................................................................................... 4
2. BLOCK DIAGRAM ......................................................................................................................... 6
3. PIN FUNCTIONS ............................................................................................................................ 7
3.1
Port Pins ................................................................................................................................................ 7
3.2
Non-port Pins ........................................................................................................................................ 9
3.3
Pin Input/Output Circuits ...................................................................................................................... 11
3.4
Recommended Connection of Unused Pins ...................................................................................... 14
4. Mk I MODE AND Mk II MODE SELECTION FUNCTION .............................................................. 15
4.1
Difference between Mk I Mode and Mk II Mode .................................................................................. 15
4.2
Setting of Stack Bank Selection Register (SBS) ................................................................................ 16
5. DIFFERENCES BETWEEN µPD75P3036 AND µPD753036 ........................................................ 17
6. PROGRAM COUNTER (PC) AND MEMORY MAP ....................................................................... 18
6.1
Program Counter (PC) .......................................................................................................................... 18
6.2
Program Memory (PROM) .................................................................................................................... 18
6.3
Data Memory (RAM) .............................................................................................................................. 20
7. INSTRUCTION SET ....................................................................................................................... 21
8. PROM (PROGRAM MEMORY) WRITE AND VERIFY .................................................................. 30
*
*
8.1
Operation Modes for Program Memory Write/Verify ......................................................................... 30
8.2
Program Memory Write Procedure ...................................................................................................... 31
8.3
Program Memory Read Procedure ...................................................................................................... 32
9. PROGRAM ERASURE (µPD75P3036KK-T ONLY) ...................................................................... 33
10. OPAQUE FILM ON ERASURE WINDOW (µPD75P3036KK-T ONLY) ......................................... 33
11. ONE-TIME PROM SCREENING .................................................................................................... 33
*
*
12. ELECTRICAL SPECIFICATIONS .................................................................................................. 34
13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ........................................................... 49
14. PACKAGE DRAWINGS ................................................................................................................. 51
*
15. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 54
APPENDIX A. FUNCTION LIST OF µPD75336, 753036, AND 75P3036 .......................................... 55
APPENDIX B. DEVELOPMENT TOOLS ............................................................................................ 56
APPENDIX C. RELATED DOCUMENTS ............................................................................................ 60
3
µ PD75P3036
1. PIN CONFIGURATION (Top View)
• 80-pin plastic QFP (14 × 14 mm)
µPD75P3036GC-3B9
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD75P3036GK-BE9
• 80-pin ceramic WQFN
P73/KR7
P72/KR6
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
RESET
X2
X1
VPP
XT2
XT1
VDD
AVREF
AVSS
AN5
AN4
AN3
µPD75P3036KK-T
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
45
16
17
18
44
43
19
42
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
COM0
COM1
COM2
COM3
BIAS
VLC0
VLC1
VLC2
P40/D0
P41/D1
P42/D2
P43/D3
VSS
P50/D4
P51/D5
P52/D6
P53/D7
P00/INT4
P01/SCK
P02/SO/SB0
S31/BP7
S30/BP6
S29/BP5
S28/BP4
S27/BP3
S26/BP2
S25/BP1
S24/BP0
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
Caution
4
Connect the VPP pin directly to V DD.
AN2
AN1
AN0
P83/AN7
P82/AN6
P81/TI2
P80/TI1
P33/MD3
P32/MD2
P31/SYNC/MD1
P30/LCDCL/MD0
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SB1
µ PD75P3036
PIN IDENTIFICATIONS
P00 to P03
: Port0
S12 to S31
: Segment Output 12-31
P10 to P13
: Port1
COM0 to COM3 : Common Output 0-3
P20 to P23
: Port2
VLC0 to VLC2
: LCD Power Supply 0-2
P30 to P33
: Port3
BIAS
: LCD Power Supply Bias Control
P40 to P43
: Port4
LCDCL
: LCD Clock
P50 to P53
: Port5
SYNC
: LCD Synchronization
P60 to P63
: Port6
TI0 to TI2
: Timer Input 0-2
P70 to P73
: Port7
PTO0 to PTO2
: Programmable Timer Output 0-2
P80 to P83
: Port8
BUZ
: Buzzer Clock
BP0 to BP7
: Bit Port0-7
PCL
: Programmable Clock
KR0 to KR7
: Key Return 0-7
INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4
SCK
: Serial Clock
INT2
: External Test Input 2
SI
: Serial Input
X1, X2
: Main System Clock Oscillation 1, 2
SO
: Serial Output
XT1, XT2
: Subsystem Clock Oscillation 1, 2
SB0, SB1
: Serial Bus 0,1
RESET
: Reset
AVREF
: Analog Reference
VPP
: Programming Power Supply
AVSS
: Analog Ground
VDD
: Positive Power Supply
AN0-AN7
: Analog Input 0-7
VSS
: Ground
MD0 to MD3
: Mode Selection 0-3
D0 to D7
: Data Bus 0-7
5
µ PD75P3036
2. BLOCK DIAGRAM
TI0/P13
PTO0/P20
AN0-AN5
AN6/P82
AN7/P83 8
AVREF
AVSS
8-BIT
TIMER/EVENT
COUNTER #0
PORT0
4
P00-P03
PORT1
4
P10-P13
SP (8)
PORT2
4
P20-P23
SBS
PORT3
4
P30/MD0P33/MD3
PORT4
4
P40/D0P43/D3
PORT5
4
P50/D4P53/D7
PORT6
4
P60-P63
PORT7
4
P70-P73
PORT8
4
P80-P83
INTT0 TOUT0
A/D
CONVERTER
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
PROGRAM
COUNTER
(14)
CY
ALU
BANK
INTBT
INTT1
TI1/P80
PTO1/P21
TI2/P81
PTO2/PCL/P22
8-BIT
TIMER/EVENT CASCADED
COUNTER #1 16-BIT
TIMER/
8-BIT
EVENT
TIMER/EVENT COUNTER
COUNTER #2
INTT2
BUZ/P23
WATCH
TIMER
GENERAL
REG.
PROM
PROGRAM
MEMORY
16384 x 8 BITS
DECODE
AND
CONTROL
INTW fLCD
SI/SB1/P03
SO/SB0/P02
SCK/P01
CLOCKED
SERIAL
INTERFACE
RAM
DATA
MEMORY
768 x 4 BITS
INTCSI TOUT0
INT0/P10
INT1/P11
INT4/P00
INT2/P12
INTERRUPT
CONTROL
KR0/P608
KR7/P73
BIT SEQ.
BUFFER (16)
fx/2 N
S12-S23
8
S24/BP0S31/BP7
LCD
CONTROL4
LER/
DRIVER
CPU CLOCK Φ
SYSTEM CLOCK
CLOCK
CLOCK GENERATOR
STAND BY
OUTPUT
DIVIDER
CONTROL
CONTROL
SUB
MAIN
12
3
fLCD
COM0COM3
VLC0-VLC2
BIAS
LCDCL/P30
SYNC/P31
PCL/P22
6
XT1 XT2 X1 X2
VPP VDD VSS RESET
µ PD75P3036
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin name
Function
Status
after reset
I/O circuit
typeNote 1
No
Input
<B>
INT4
P01
I/O
SCK
P02
I/O
SO/SB0
<F> -B
P03
I/O
SI/SB1
<M> -C
P10
Input
INT0
P11
INT1
P12
INT2
P13
TI0
I/O
PTO0
P21
PTO1
P22
PCL/PTO2
P23
BUZ
I/O
LCDCL/MD0
P31
SYNC/MD1
P32
MD2
P33
MD3
P40 Note 2
I/O
D0
P41 Note 2
D1
P42 Note 2
D2
P43 Note 2
D3
P50 Note 2
I/O
D4
P51 Note 2
D5
P52 Note 2
D6
P53 Note 2
D7
This is a 4-bit input port (PORT0).
Connection of an on-chip pull-up resistor can be
specified in 3-bit units by software for P01 to P03.
8-bit
I/O
Input
P30
*
Alternate
function
P00
P20
*
I/O
<F> -A
This is a 4-bit input port (PORT1).
Connection of an on-chip pull-up resistor can be
specified in 4-bit units by software.
P10/INT0 can select noise elimination circuit.
No
Input
<B> -C
This is a 4-bit I/O port (PORT2).
Connection of an on-chip pull-up resistor can be
specified in 4-bit units by software.
No
Input
E-B
This is a programmable 4-bit I/O port (PORT3).
Input and output can be specified in bit units.
Connection of an on-chip pull-up resistor can be
specified in 4-bit units by software.
No
Input
E-B
This is an N-ch open-drain 4-bit I/O port (PORT4).
When set to open-drain, voltage is 13 V.
Also functions as data I/O pin (lower 4 bits)
for program memory (PROM) write/verify.
Yes
High
impedance
M-E
High
impedance
M-E
This is an N-ch open-drain 4-bit I/O port (PORT5).
When set to open-drain, voltage is 13 V.
Also functions as data I/O pin (upper 4 bits)
for program memory (PROM) write/verify.
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.
2. Low level input leakage current increases when input instructions or bit manipulate instructions are executed.
7
µ PD75P3036
3.1 Port Pins (2/2)
Pin name
P60
I/O
I/O
Alternate
function
KR0
P61
KR1
P62
KR2
P63
KR3
P70
I/O
KR5
P72
KR6
P73
KR7
P80
I/O
This is a programmable 4-bit I/O port (PORT6).
Input and output can be specified in bit units.
Connection of an on-chip pull-up resistor can be
specified in 4-bit units by software.
KR4
P71
TI2
P82
AN6
P83
AN7
BP0
Output S24
BP1
S25
BP2
S26
BP3
S27
BP4
Output S28
BP5
S29
BP6
S30
BP7
S31
8-bit
I/O
Status
after reset
I/O circuit
typeNote 1
Yes
Input
<F> -A
Input
<F> -A
Input
<E> -E
This is a 4-bit I/O port (PORT7).
Connection of an on-chip pull-up resistor can be
specified in 4-bit units by software.
TI1
P81
Function
This is a 4-bit I/O port (PORT8).
Connection of an on-chip pull-up resistor can be
specified in 4-bit units by software.
No
Y-B
These pins are also used as 1-bit I/O port (BIT
PORT) segment output pin.
No
Note 2
H-A
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.
*
*
2. BP0 through BP7 select VLC1 as an input source.
However, the output levels change depending on the external circuit of BP0 through BP7 and V LC1.
Example Because BP0 through BP7 are mutually connected inside the µPD75P3036, the output levels of BP0 through
BP7 are determined by R1, R2, and R3.
VDD
µPD75P3036
R2
BP0
ON
VLC1
BP1
R1
ON
R3
8
µ PD75P3036
3.2 Non-port Pins (1/2)
Pin name
TI0
I/O
Input
TI1
P13
Function
External event pulse input to timer/event counter
Status
after reset
I/O circuit
typeNote
Input
<B> -C
P80
TI2
PTO0
Alternate
function
<E> -E
P81
Output
P20
PTO1
P21
PTO2
P22/PCL
Timer/event counter output
Input
E-B
PCL
Output
P22/PTO2
Clock output
Input
E-B
BUZ
Output
P23
Frequency output (for buzzer or system clock trimming)
Input
E-B
SCK
I/O
P01
Serial clock I/O
Input
<F> -A
SO/SB0
I/O
P02
Serial data output
Serial data bus I/O
Input
<F> -B
SI/SB1
I/O
P03
Serial data input
Serial data bus I/O
Input
<M> -C
INT4
Input
P00
Edge detection vectored interrupt input
(valid for detecting both rising and falling edges)
Input
<B>
INT0
Input
P10
Edge detection vectored interrupt input
(detected edge is selectable)
INT0/P10 can select noise elimination
circuit.
Input
<B> -C
INT1
P11
Noise elimination
circuit
/asynchronous
is selectable
Asynchronous
INT2
Input
P12
Rising edge detection test input
Input
<B> -C
KR0 to KR3
Input
P60 to P63
Parallel falling edge detection test input
Input
<F> -A
KR4 to KR7
Input
P70 to P73
Parallel falling edge detection test input
Input
<F> -A
X1
Input
—
—
—
X2
—
—
Ceramic/crystal oscillation circuit connection for main system
clock. If using an external clock, input to X1 and input
inverted phase to X2.
XT1
Input
—
—
—
XT2
—
—
Crystal oscillation circuit connection for subsystem clock.
If using an external clock, input to XT1 and input inverted
phase to XT2. XT1 can be used as a 1-bit (test) input.
Input
—
System reset input (low level active)
—
<B>
Mode selection for program memory (PROM) write/verify
Input
E-B
Data bus for program memory (PROM) write/verify
Input
M-E
RESET
MD0
I/O
P30/LCDCL
MD1
P31/SYNC
MD2, MD3
P32, P33
D0 to D3
I/O
D4 to D7
P40 to P43
Asynchonous
P50 to P53
VPP
—
—
Programmable power supply voltage for program memory
(PROM) write/verify.
For normal operation, connect to VDD .
Apply +12.5 V for PROM write/verify.
—
—
VDD
—
—
Positive power supply
—
—
VSS
—
—
Ground
—
—
Note Circuit types enclosed in brackets indicate Schmitt trigger input.
9
µ PD75P3036
3.2 Non-port Pins (2/2)
Pin name
I/O
Alternate
function
S12 to S23
Output
—
S24 to S31
Output BP0 to BP7
Function
Status
after reset
I/O circuit
type
Segment signal output
Note 1
G-A
Segment signal output
Note 1
H-A
Note 1
G-B
—
—
High
impedance
—
COM0 to COM3 Output
—
Common signal output
VLC0 to VLC2
—
—
Power source for LCD driver
Output
—
Output for external split resistor cut
BIAS
LCDCLNote 2
Note 2
SYNC
AN0 to AN5
Output P30/MD0
Clock output for driving external expansion driver
Input
E-B
Output P31/MD1
Clock output for synchronization of external expansion driver
Input
E-B
Analog signal input for A/D converter
Input
Y
Input
—
AN6
P82
AN7
P83
Y-B
AVREF
—
—
A/D converter reference voltage
—
Z-N
AVSS
—
—
A/D converter reference GND potential
—
Z-N
Notes 1. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs.
S12 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0
2. These pins are provided for future system expansion. Currently, only P30 and P31 are used.
10
µ PD75P3036
3.3 Pin Input/Output Circuits
The input/output circuits for the µPD75P3036’s pins are shown in schematic form below.
(1/3)
TYPE A
TYPE D
VDD
VDD
data
P-ch
OUT
P-ch
IN
output
disable
N-ch
CMOS standard input buffer
TYPE B
N-ch
Push-pull output that can be set to output high-impedance
(with both P-ch and N-ch OFF).
TYPE E-B
VDD
P.U.R.
P.U.R.
enable
P-ch
IN
data
IN/OUT
Type D
output
disable
Type A
Schmitt trigger input with hysteresis characteristics.
P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE E-E
VDD
P.U.R.
VDD
P.U.R.
enable
P-ch
P.U.R.
data
P-ch
P.U.R.
enable
Type D
IN/OUT
output
disable
Type A
IN
P.U.R. : Pull-Up Resistor
Type B
P.U.R. : Pull-Up Resistor
11
µ PD75P3036
(2/3)
*
TYPE F-A
TYPE G-B
VDD
VLC0
P.U.R.
P.U.R.
enable
P-ch
VLC1
P-ch N-ch
data
Type D
IN/OUT
output
disable
OUT
COM or SEG
data
N-ch P-ch
Type B
VLC2
N-ch
P.U.R. : Pull-Up Resistor
*
TYPE F-B
TYPE H-A
VDD
P.U.R.
P.U.R.
enable
P-ch
output
disable
(P)
VDD
SEG
data
Type G-A
Bit Port
data
output
disable
Type E-B
IN/OUT
P-ch
IN/OUT
data
output
disable
N-ch
output
disable
(N)
P.U.R. : Pull-Up Resistor
*
TYPE G-A
TYPE M-C
VDD
VLC0
P.U.R.
VLC1
P.U.R.
enable
P-ch N-ch
P-ch
IN/OUT
OUT
data
N-ch
output
disable
SEG
data
N-ch
VLC2
N-ch
12
P.U.R. : Pull-Up Resistor
µ PD75P3036
(3/3)
*
TYPE M-E
TYPE Y-B
data
output
disable
N-ch
(+13 V
withstand
voltage)
VDD
input
instruction
P.U.R.
enable
P-ch
data
P-ch
Type D
IN/OUT
output
disable
Note
P.U.R.
Type A
Voltage limitation
circuit
(+13 V withstand
voltage)
Note
VDD
IN/OUT
port Note
input
Type Y
The pull-up resistor operates only when an input
instruction is executed (current flows from VDD to
the pin when the pin is low).
P.U.R. : Pull-Up Resistor
*
TYPE Y
TYPE Z-N
AVREF
VDD
P-ch
IN
N-ch
Sampling C
+
–
reference
voltage
VDD
AVSS
input
enable
AVSS
reference voltage
(from voltage tap of
series resistor string)
ADEN
N-ch
AVSS
Note Becomes active when an input instruction is executed.
13
µ PD75P3036
*
3.4 Recommended Connection of Unused Pins
Pin
Recommended connection
P00/INT4
Connect to VSS or VDD
P01/SCK
Connect to VSS or VDD via a resistor individually
P02/SO/SB0
P03/SI/SB1
Connect to VSS
P10/INT0 to P12/INT2 Connect to VSS or VDD
P13/TI0
P20/PTO0
Input status : connect to VSS or VDD via a resistor individually.
P21/PTO1
Output status: open
P22/PTO2/PCL
P23/BUZ
P30/LCDCL
P31/SYNC
P32, P33
P40 to P43
Connect to VSS
P50 to P53
P60/KR0 to P63/KR3
Input status : connect to VSS or VDD via a resistor individually.
P70/KR4 to P73/KR7
Output status: open
P80/TI1
P81/TI2
P82/AN6
P83/AN7
S12 to S23
Open
S24/BP0 to S31/BP7
COM0 to COM3
VLC0 to VLC2
Connect to VSS
BIAS
Connect to VSS only when VLC0 to VLC2 are all not used.
In other cases, leave open.
XT1Note
Connect to VSS or VDD
Note
XT2
Open
AN0 to AN5
Connect to VSS or VDD
VPP
Connect to VDD directly
Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use
the internal feedback resistor).
14
µ PD75P3036
4. Mk I MODE AND Mk II MODE SELECTION FUNCTION
Setting a stack bank selection (SBS) register for the µPD75P3036 enables the program memory to be switched between
Mk I mode and Mk II mode. This function is applicable when using the µPD75P3036 to evaluate the µPD753036.
When the SBS bit 3 is set to 1 : sets Mk I mode (supports Mk I mode for µPD753036)
When the SBS bit 3 is set to 0 : sets Mk II mode (supports Mk II mode for µPD753036)
4.1 Difference between Mk I Mode and Mk II Mode
Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the µPD75P3036.
Table 4-1. Difference between Mk I Mode and Mk II Mode
Item
Mk I Mode
Mk II Mode
Program counter
PC13-0
Program memory (bytes)
16384
Data memory (bits)
768 x 4
Stack
Stack bank
Selectable via memory banks 0 to 2
No. of stack bytes
2 bytes
3 bytes
BRA !addr1 instruction
Not available
Available
Instruction
CALLA !addr1 instruction
Instruction
*
3 machine cycles
4 machine cycles
execution time CALLF !faddr instruction
CALL !addr instruction
2 machine cycles
3 machine cycles
Supported mask ROM versions
When set to Mk I mode for µPD753036
When set to Mk II mode for µPD753036
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series.
Therefore, this mode is effective for enhancing software compatibility with products exceeding 16
Kbytes.
When the Mk II mode is selected, the number of stack bytes used during execution of subroutine
call instructions increases by one byte per stack compared to the Mk I mode. When the CALL !addr
and CALLF !faddr instructions are used, the machine cycle becomes longer by one machine cycle.
Therefore, use the Mk I mode if the RAM efficiency and processing performance are more important
than software compatibility.
15
µ PD75P3036
4.2 Setting of Stack Bank Selection Register (SBS)
Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing
this.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be
sure to initialize the stack bank selection register to 10xxBNote at the beginning of the program. When using the Mk II mode,
be sure to initialize it to 00xxBNote.
Note Set the desired value for xx.
Figure 4-1. Format of Stack Bank Selection Register
Address
F84H
3
2
1
0
SBS3
SBS2
SBS1
SBS0
Symbol
SBS
Stack area specification
0
0
Memory bank 0
0
1
Memory bank 1
1
0
Memory bank 2
1
1
Setting prohibited
0
Be sure to enter “0” for bit 2.
Mode selection specification
0
Mk II mode
1
Mk I mode
Cautions 1. SBS3 is set to “1” after RESET input, and consequently the CPU operates in Mk I mode. When using
instructions for Mk II mode, set SBS3 to “0” and set Mk II mode before using the instructions.
2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after
RESET input and after setting the stack bank selection register.
16
µ PD75P3036
5. DIFFERENCES BETWEEN µPD75P3036 AND µPD753036
The µ PD75P3036 replaces the internal mask ROM in the program memory of the µPD753036 with a one-time PROM or
EPROM. The µPD75P3036’s Mk I mode supports the Mk I mode in the µ PD753036 and the µPD75P3036’s Mk II mode
supports the Mk II mode in the µ PD753036.
Table 5-1 lists differences among the µ PD75P3036 and the µPD753036. Be sure to check the differences among these
products before using them with PROMs for debugging or prototype testing of application systems or, later, when using
them with a mask ROM for full-scale production.
As to CPU function and on-chip hardware, see the User’s Manual.
Table 5-1. Differences between µPD75P3036 and µPD753036
µ PD753036
Item
µPD75P3036
Program counter
14 bits
Program memory (bytes)
16384
16384
Mask ROM
One-time PROM, EPROM
Data memory (x 4 bits)
768
Mask option
Yes (can specify whether to incorporate
on-chip or not)
Pull-up resistor of
ports 4, 5
No (don’t incorporate on-chip)
Split resistor for LCD
driving power supply
Pin configuration
Other
Selection of
Yes (can select either 217 /fX or 2 15/fX)Note
oscillation
stabilization wait time
No (fixed to 215/fX)Note
Selection of
subsystem clock
feedback resistor
Yes (can select either use enabled or use
disabled)
No (use enabled)
Pin No. 29 to 32
P40 to P43
P40/D0 to P43/D3
Pin No. 34 to 37
P50 to P53
P50/D4 to P53/D7
Pin No. 50
P30/LCDCL
P30/LCDCL/MD0
Pin No. 51
P31/SYNC
P31/SYNC/MD1
Pin No. 52
P32
P32/MD2
Pin No. 53
P33
P33/MD3
Pin No. 69
IC
VPP
Noise resistance and noise radiation may differ due to the different circuit sizes and mask
layouts.
Note 217/fX is 21.8 ms during 6.0-MHz operation, and 31.3 ms during 4.19-MHz operation.
215/fX is 5.46 ms during 6.0-MHz operation, and 7.81 ms during 4.19-MHz operation.
Caution
Noise resistance and noise radiation are different in PROM and mask ROM versions. In transferring to
mask ROM versions from the PROM version in a process between prototype development and full
production, be sure to fully evaluate the mask ROM version’s CS (not ES).
17
µ PD75P3036
6. PROGRAM COUNTER (PC) AND MEMORY MAP
6.1 Program Counter (PC) ... 14 bits
This is a 14-bit binary counter that stores program memory address data.
Figure 6-1. Configuration of Program Counter
PC13
PC12
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PC
6.2 Program Memory (PROM) ... 16384 x 8 bits
The program memory consists of 16384 x 8-bit one-time PROM or EPROM.
• Addresses 0000H and 0001H
Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is
generated are written. Reset start is possible from any address.
• Addresses 0002H to 000DH
Vector table wherein the program start address and the values set for the RBE and MBE by each vectored interrupt are
written. Interrupt processing can start from any address.
• Addresses 0020H to 007FH
Table area referenced by the GETI instruction Note.
Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte/3-byte instruction, or two 1-byte
instructions. It is used to decrease the number of program steps.
18
µ PD75P3036
Figure 6-2 shows the addressing ranges for the program memory, branch instruction and the subroutine call instruction.
Figure 6-2. Program Memory Map
0000H
7
6
MBE
RBE
5
0
Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)
0004H
MBE
RBE
INT0 start address (upper 6 bits)
CALLF
!faddr instruction
entry address
Branch address
for the following
instructions
• BR BCXA
• BR BCDE
• BR !addr
Note
• BRA !addr1
• CALLA !addr1Note
INT0 start address (lower 8 bits)
0006H
MBE
RBE
INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)
0008H
MBE
RBE
INTCSI start address (upper 6 bits)
BRCB
!caddr instruction
branch address
INTCSI start address (lower 8 bits)
000AH
MBE
RBE
INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)
000CH
MBE
RBE
INTT1, INTT2 start address (upper 6 bits)
INTT1, INTT2 start address (lower 8 bits)
CALL !addr instruction
subroutine
entry address
Branch/call
address
by GETI
0020H
Reference table for GETI instruction
007FH
0080H
BR $addr instruction
relative branch address
(–15 to –1,
+2 to +16)
07FFH
0800H
0FFFH
1000H
BRCB
!caddr instruction
branch address
1FFFH
2000H
BRCB
!caddr instruction
branch address
2FFFH
3000H
BRCB
!caddr instruction
branch address
3FFFH
*
Note Can be used only in the Mk II mode.
Remark
For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch
to addresses with changes in the PC’s lower 8 bits only.
19
µ PD75P3036
6.3 Data Memory (RAM) ... 768 x 4 bits
Figure 6-3 shows the data memory configuration.
Data memory consists of a data area and a peripheral hardware area. The data area consists of 768 x 4-bit static RAM.
Figure 6-3. Data Memory Map
Data memory
Memory bank
000H
General-purpose register area
(32 x 4)
01FH
020H
0
256 x 4
(224 x 4)
0FFH
100H
256 x 4
(236 x 4)
1
1EBH
1ECH
Display data memory
(20 x 4)
1FFH
200H
Data area
static RAM
(768 x 4)
256 x 4
Stack area Note
2
2FFH
Not incorporated
F80H
Peripheral hardware area
128 x 4
FFFH
Note Memory bank 0, 1, or 2 can be selected as the stack area.
20
15
µ PD75P3036
7. INSTRUCTION SET
(1) Representation and coding formats for operands
In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s
operand representations (for further description, see the RA75X Assembler Package User’s Manual—Language
(EEU-1363)). When there are several codes, select and use just one. Codes that consist of uppercase letters and + or
– symbols are key words that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further description, see the
User’s Manual). The number of labels that can be entered for fmem and pmem are restricted.
Representation
Coding format
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp’
XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1
BC, DE, HL, XA’, BC’, DE’, HL’
rpa
HL, HL+, HL–, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or labelNote
bit
2-bit immediate data or label
fmem
FB0H-FBFH, FF0H-FFFH immediate data or label
pmem
FC0H-FFFH immediate data or label
addr
0000H-3FFFH immediate data or label
addr1
0000H-3FFFH immediate data or label
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H-7FH immediate data (however, bit0 = 0) or label
PORTn
PORT0-PORT8
IEXXX
IEBT, IECSI, IET0-IET2, IE0-IE2, IE4, IEW
RBn
RB0-RB3
MBn
MB0-MB2, MB15
Note When processing 8-bit data, only even-numbered addresses can be entered.
21
µ PD75P3036
(2) Operation legend
A
: A register; 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC)
DE
: Register pair (DE)
HL
: Register pair (HL)
XA’
: Expansion register pair (XA’)
BC’
: Expansion register pair (BC’)
DE’
: Expansion register pair (DE’)
HL’
: Expansion register pair (HL’)
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn : Port n (n = 0 to 8)
22
IME
: Interrupt master enable flag
IPS
: Interrupt priority selection register
IEXXX
: Interrupt enable flag
RBS
: Register bank selection register
MBS
: Memory bank selection register
PCC
: Processor clock control register
.
: Delimiter for address and bit
(XX)
: The contents addressed by XX
XXH
: Hexadecimal data
µ PD75P3036
(3) Description of symbols used in addressing area
MB = MBE • MBS
*1
MBS = 0-2, 15
*2
MB = 0
MBE = 0
: MB = 0 (000H-07FH)
MB = 15 (F80H-FFFH)
*3
MBE = 1
Data memory
addressing
: MB = MBS
MBS = 0-2, 15
*4
MB = 15, fmem = FB0H-FBFH, FF0H-FFFH
*5
MB = 15, pmem = FC0H-FFFH
*6
addr = 0000H-3FFFH
addr, addr1 = (Current PC) –15 to (Current PC) –1
*7
(Current PC) +2 to (Current PC) +16
caddr = 0000H-0FFFH (PC13, 12 = 00B: Mk I or Mk II mode) or
1000H-1FFFH (PC13, 12 = 01B: Mk I or Mk II mode) or
*8
2000H-2FFFH (PC13, 12 = 10B: Mk I or Mk II mode) or
Program memory
addressing
3000H-3FFFH (PC13, 12 = 11B: Mk I or Mk II mode)
*9
faddr = 0000H-07FFH
*10
taddr = 0020H-007FH
*11
addr1 = 0000H-3FFFH
Remarks 1. MB indicates access-enabled memory banks.
2. In area *2, MB = 0 for both MBE and MBS.
3. In areas *4 and *5, MB = 15 for both MBE and MBS.
4. Areas *6 to *11 indicate corresponding address-enabled areas.
(4) Description of machine cycles
S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as
shown below.
• No skip ..................................................................... S = 0
• Skipped instruction is 1-byte or 2-byte instruction .... S = 1
• Skipped instruction is 3-byte instruction Note .............. S = 2
Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1
Caution
The GETI instruction is skipped for one machine cycle.
One machine cycle equals one cycle (= tCY) of the CPU clock Φ. Use the PCC setting to select among four cycle times.
23
µ PD75P3036
Instruction
group
Transfer
Mnemonic
MOV
XCH
Table
reference
MOVT
Operand
No. of Machine
bytes cycle
Addressing
area
Skip
condition
A, #n4
1
1
A<-n4
reg1, #n4
2
2
reg1<-n4
XA, #n8
2
2
XA<-n8
String-effect A
HL, #n8
2
2
HL<-n8
String-effect B
rp2, #n8
2
2
rp2<-n8
A, @HL
1
1
A<-(HL)
*1
A, @HL+
1
2+S
A<-(HL), then L<-L+1
*1
L=0
A, @HL–
1
2+S
A<-(HL), then L<-L–1
*1
L=FH
A, @rpa1
1
1
A<-(rpa1)
*2
XA, @HL
2
2
XA<-(HL)
*1
@HL, A
1
1
(HL)<-A
*1
@HL, XA
2
2
(HL)<-XA
*1
A, mem
2
2
A<-(mem)
*3
XA, mem
2
2
XA<-(mem)
*3
mem, A
2
2
(mem)<-A
*3
mem, XA
2
2
(mem)<-XA
*3
A, reg1
2
2
A<-reg1
XA, rp’
2
2
XA<-rp’
reg1, A
2
2
reg1<-A
rp’1, XA
2
2
rp’1<-XA
A, @HL
1
1
A<->(HL)
*1
A, @HL+
1
2+S
A<->(HL), then L<-L+1
*1
L=0
A, @HL–
1
2+S
A<->(HL), then L<-L–1
*1
L=FH
A, @rpa1
1
1
A<->(rpa1)
*2
String-effect A
XA, @HL
2
2
XA<->(HL)
*1
A, mem
2
2
A<->(mem)
*3
XA, mem
2
2
XA<->(mem)
*3
A, reg1
1
1
A<->reg1
XA, rp’
2
2
XA<->rp’
XA, @PCDE
1
3
XA<-(PC13-8+DE)ROM
XA, @PCXA
1
3
XA<-(PC13-8+XA)ROM
XA, @BCDE
1
3
XA<-(BCDE)ROM Note
*6
3
Note
*6
XA, @BCXA
1
Note Only the lower 2 bits in the B register are valid.
24
Operation
XA<-(BCXA)ROM
µ PD75P3036
Instruction
group
Bit transfer
Arithmetic/
Mnemonic
MOV1
ADDS
logical
operation
ADDC
SUBS
SUBC
AND
OR
XOR
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
Skip
condition
CY, fmem.bit
2
2
CY<-(fmem.bit)
*4
CY, [email protected]
2
2
CY<-(pmem7-2+L3-2 .bit(L1-0 ))
*5
CY, @H+mem.bit
2
2
CY<-(H+mem3-0.bit)
*1
fmem.bit, CY
2
2
(fmem.bit)<-CY
*4
[email protected], CY
2
2
(pmem7-2+L3-2 .bit(L1-0 ))<-CY
*5
@H+mem.bit, CY
2
2
(H+mem3-0.bit)<-CY
*1
A, #n4
1
1+S
A<-A+n4
carry
XA, #n8
2
2+S
XA<-XA+n8
carry
A, @HL
1
1+S
A<-A+(HL)
XA, rp’
2
2+S
XA<-XA+rp’
*1
carry
carry
rp’1, XA
2
2+S
rp’1<-rp’1+XA
carry
A, @HL
1
1
A, CY<-A+(HL)+CY
XA, rp’
2
2
XA, CY<-XA+rp’+CY
rp’1, XA
2
2
rp’1, CY<-rp’1+XA+CY
A, @HL
1
1+S
A<-A–(HL)
XA, rp’
2
2+S
XA<-XA–rp’
borrow
rp’1, XA
2
2+S
rp’1<-rp’1–XA
borrow
A, @HL
1
1
A, CY<-A–(HL)–CY
XA, rp’
2
2
XA, CY<-XA–rp’–CY
rp’1, XA
2
2
rp’1, CY<-rp’1–XA–CY
A, #n4
2
2
A<-A^n4
A, @HL
1
1
A<-A^(HL)
XA, rp’
2
2
XA<-XA ^rp’
rp’1, XA
2
2
rp’1<-rp’1^XA
A, #n4
2
2
A<-Avn4
A, @HL
1
1
A<-Av(HL)
XA, rp’
2
2
XA<-XAvrp’
rp’1, XA
2
2
rp’1<-rp’1vXA
A, #n4
2
2
A<-Avn4
A, @HL
1
1
A<-Av(HL)
XA, rp’
2
2
XA<-XAvrp’
*1
*1
borrow
*1
*1
*1
*1
rp’1, XA
2
2
rp’1<-rp’1vXA
RORC
A
1
1
CY<-A0, A3<-CY, An–1<-A n
manipulation
NOT
A
2
2
A<-A
Increment/
INCS
reg
1
1+S
reg<-reg+1
reg=0
rp1
1
1+S
rp1<-rp1+1
rp1=00H
@HL
2
2+S
(HL)<-(HL)+1
*1
(HL)=0
mem
2
2+S
(mem)<-(mem)+1
*3
(mem)=0
reg
1
1+S
reg<-reg–1
reg=FH
rp’
2
2+S
rp’<-rp’–1
rp’=FFH
Accumulator
decrement
DECS
25
µ PD75P3036
Instruction
group
Comparison
Mnemonic
SKE
Operand
No. of Machine
bytes cycle
Operation
2
2+S
Skip if reg=n4
@HL, #n4
2
2+S
Skip if(HL)=n4
*1
(HL)=n4
A, @HL
1
1+S
Skip if A=(HL)
*1
A=(HL)
XA, @HL
2
2+S
Skip if XA=(HL)
*1
XA=(HL)
A, reg
2
2+S
Skip if A=reg
A=reg
XA, rp’
2
2+S
Skip if XA=rp’
XA=rp’
SET1
CY
1
1
CY<-1
manipulation
CLR1
CY
1
1
CY<-0
reg=n4
SKT
CY
1
1+S
NOT1
CY
1
1
CY<-CY
SET1
mem.bit
2
2
(mem.bit)<-1
*3
fmem.bit
2
2
(fmem.bit)<-1
*4
[email protected]
2
2
(pmem7-2+L3-2 .bit(L1-0 ))<-1
*5
@H+mem.bit
2
2
(H+mem3-0.bit)<-1
*1
mem.bit
2
2
(mem.bit)<-0
*3
fmem.bit
2
2
(fmem.bit)<-0
*4
[email protected]
2
2
(pmem7-2+L3-2 .bit(L1-0 ))<-0
*5
@H+mem.bit
2
2
(H+mem3-0.bit)<-0
*1
mem.bit
2
2+S
Skip if(mem.bit)=1
*3
(mem.bit)=1
fmem.bit
2
2+S
Skip if(fmem.bit)=1
*4
(fmem.bit)=1
[email protected]
2
2+S
Skip if(pmem7-2 +L3-2.bit(L1-0))=1
*5
([email protected])=1
@H+mem.bit
2
2+S
Skip if(H+mem3-0 .bit)=1
*1
(@H+mem.bit)=1
mem.bit
2
2+S
Skip if(mem.bit)=0
*3
(mem.bit)=0
fmem.bit
2
2+S
Skip if(fmem.bit)=0
*4
(fmem.bit)=0
[email protected]
2
2+S
Skip if(pmem7-2 +L3-2.bit(L1-0))=0
*5
([email protected])=0
@H+mem.bit
2
2+S
Skip if(H+mem3-0 .bit)=0
*1
(@H+mem.bit)=0
fmem.bit
2
2+S
Skip if(fmem.bit)=1 and clear
*4
(fmem.bit)=1
[email protected]
2
2+S
Skip if(pmem7-2+L3-2.bit (L1-0))=1 and clear
*5
([email protected])=1
@H+mem.bit
2
2+S
Skip if(H+mem 3-0.bit)=1 and clear
*1
(@H+mem.bit)=1
CY, fmem.bit
2
2
CY<-CY^(fmem.bit)
*4
CY, [email protected]
2
2
CY<-CY^(pmem7-2+L 3-2.bit(L1-0 ))
*5
manipulation
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
26
Skip
condition
reg, #n4
Carry flag
Memory bit
Addressing
area
Skip if CY=1
CY=1
CY, @H+mem.bit
2
2
CY<-CY^(H+mem3-0.bit)
*1
CY, fmem.bit
2
2
CY<-CYv(fmem.bit)
*4
CY, [email protected]
2
2
CY<-CYv(pmem7-2+L 3-2.bit(L1-0 ))
*5
CY, @H+mem.bit
2
2
CY<-CYv(H+mem3-0.bit)
*1
CY, fmem.bit
2
2
CY<-CYv (fmem.bit)
*4
CY, [email protected]
2
2
CY<- CYv(pmem7-2 +L3-2.bit(L1-0))
*5
CY, @H+mem.bit
2
2
CY<-CYv(H+mem3-0.bit)
*1
µ PD75P3036
Instruction
group
Branch
Mnemonic
BRNote 1
BRA
Note 1
BRCB
Operand
No. of Machine
bytes cycle
Operation
Addressing
area
addr
—
—
PC13-0<-addr
Use the assembler to select the
most appropriate instruction
among the following.
• BR !addr
• BRCB !caddr
• BR $addr
*6
addr1
—
—
PC13-0<-addr1
Use the assembler to select
the most appropriate instruction
among the following.
• BRA !addr1
• BR !addr
• BRCB !caddr
• BR $addr1
*11
!addr
3
3
PC13-0<-addr
*6
$addr
1
2
PC13-0<-addr
*7
$addr1
1
2
PC13-0<-addr1
PCDE
2
3
PC13-0<-PC13-8+DE
PCXA
2
3
PC13-0<-PC13-8+XA
BCDE
2
3
PC13-0<-BCDE Note 2
*6
Note 2
*6
BCXA
2
3
PC13-0<-BCXA
!addr1
3
3
PC13-0<-addr1
*11
!caddr
2
2
PC13-0<-PC13, 12+caddr 11-0
*8
Skip
condition
Notes 1. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can
be performed only in the Mk I mode.
2. Only the lower 2 bits in the B register are valid.
27
µ PD75P3036
Instruction
group
Subroutine
Mnemonic
CALLANote
Operand
!addr1
No. of Machine
bytes cycle
3
3
stack control
Operation
(SP–6)(SP–3)(SP–4)<-PC11-0
Addressing
area
Skip
condition
*11
(SP–5)<-0, 0, PC13, 12
(SP–2)<-X, X, MBE, RBE
PC13–0<-addr1, SP<-SP–6
CALLNote
!addr
3
3
(SP–4)(SP–1)(SP–2)<-PC11-0
*6
(SP–3)<-MBE, RBE, PC13, 12
PC13–0<-addr, SP<-SP–4
4
(SP–6)(SP–3)(SP–4)<-PC11-0
(SP–5)<-0, 0, PC13, 12
(SP–2)<-X, X, MBE, RBE
PC13-0<-addr, SP<-SP–6
CALLFNote
!faddr
2
2
(SP–4)(SP–1)(SP–2)<-PC11-0
*9
(SP–3)<-MBE, RBE, PC13, 12
PC13-0<-000+faddr, SP<-SP–4
3
(SP–6)(SP–3)(SP–4)<-PC11-0
(SP–5)<-0, 0, PC13, 12
(SP–2)<-X, X, MBE, RBE
PC13-0<-000+faddr, SP<-SP–6
Note
RET
1
3
MBE, RBE, PC13, 12<-(SP+1)
PC11-0<-(SP)(SP+3)(SP+2)
SP<-SP+4
X, X, MBE, RBE<-(SP+4)
PC11-0<-(SP)(SP+3)(SP+2)
0, 0, PC13, 12<-(SP+1)
SP<-SP+6
RETSNote
1
3+S
MBE, RBE, PC13, 12<-(SP+1)
Unconditional
PC11-0<-(SP)(SP+3)(SP+2)
SP<-SP+4
then skip unconditionally
X, X, MBE, RBE<-(SP+4)
PC11-0<-(SP)(SP+3)(SP+2)
0, 0, PC13, 12<-(SP+1)
SP<-SP+6
then skip unconditionally
RETI Note
1
3
MBE, RBE, PC13, 12<-(SP+1)
PC11-0<-(SP)(SP+3)(SP+2)
PSW<-(SP+4)(SP+5), SP<-SP+6
0, 0, PC13, 12<-(SP+1)
PC11-0<-(SP)(SP+3)(SP+2)
PSW<-(SP+4)(SP+5), SP<-SP+6
Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be
performed only in the Mk I mode.
28
µ PD75P3036
Instruction
group
Subroutine
Mnemonic
PUSH
1
(SP–1)(SP–2)<-rp, SP<-SP–2
BS
2
2
(SP–1)<-MBS, (SP–2)<-RBS, SP<-SP–2
rp
1
1
rp<-(SP+1)(SP), SP<-SP+2
BS
2
2
MBS<-(SP+1), RBS<-(SP), SP<-SP+2
2
2
IME(IPS.3)<-1
2
2
IEXXX<-1
2
2
IME(IPS.3)<-0
IEXXX
2
2
IEXXX<-0
A, PORTn
2
2
A<-PORTn
XA, PORTn
2
2
XA<-PORTn+1, PORTn (n=4, 6)
PORTn, A
2
2
PORTn<-A
PORTn, XA
2
2
PORTn+1, PORTn<-XA (n=4, 6)
HALT
2
2
Set HALT Mode(PCC.2<-1)
STOP
2
2
Set STOP Mode(PCC.3<-1)
NOP
1
1
No Operation
RBn
2
2
RBS<-n (n=0-3)
MBn
2
2
MBS<-n (n=0-2, 15)
taddr
1
3
• When using TBR instruction
EI
control
IEXXX
DI
IN
Note 1
OUTNote 1
CPU control
Special
Operation
1
POP
I/O
No. of Machine
bytes cycle
rp
stack control
Interrupt
Operand
SEL
Note 2, 3
GETI
Addressing
area
Skip
condition
(n=0-8)
(n=2-8)
*10
PC13-0<-(taddr)5-0+(taddr+1)
- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - -
• When using TCALL instruction
(SP–4)(SP–1)(SP–2)<-PC11-0
(SP–3)<-MBE, RBE, PC13, 12
PC13-0<-(taddr)5-0+(taddr+1)
SP<-SP–4
- - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - -
• When using instruction other than
TBR or TCALL
Execute (taddr)(taddr+1) instruction
1
3
• When using TBR instruction
Determined by
referenced
instruction
*10
PC13-0<-(taddr)5-0+(taddr+1)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4
- - - - - - - - - - - -
• When using TCALL instruction
(SP–6)(SP–3)(SP–4)<-PC11-0
(SP–5)<-MBE, RBE, PC13, 12
(SP–2)<-X, X, MBE, RBE
PC13-0<-(taddr)5-0+(taddr+1)
SP<-SP–6
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3
• When using instruction other than
TBR or TCALL
Execute (taddr)(taddr+1) instruction
- - - - - - - - - - - -
Determined by
referenced
instruction
Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.
2. TBR and TCALL instructions are assembler pseudo-instructions for the GETI instruction’s table definitions.
3. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can
be performed only in the Mk I mode.
29
µ PD75P3036
8. PROM (PROGRAM MEMORY) WRITE AND VERIFY
The µ PD75P3036 contains a 16384 x 8-bit PROM as a program memory. The pins listed in the table below are used for
this PROM’s write/verify operations. Clock input from the X1 pin is used instead of address input as a method for updating
addresses.
Pin
Function
VPP
Pin where program voltage is applied during program memory
write/verify (usually VDD potential)
X1, X2
Clock input pins for address updating during program memory
write/verify. Input the X1 pin’s inverted signal to the
X2 pin.
MD0 to MD3
Operation mode selection pin for program memory write/verify
D0/P40 to D3/P43
(lower 4 bits)
D4/P50 to D7/P53
(upper 4 bits)
8-bit data I/O pins for program memory write/verify
VDD
Pin where power supply voltage is applied. Applies 1.8 to 5.5
V in normal operation mode and +6 V for program
memory write/verify.
Caution Pins not used for program memory write/verify should be connected to VSS .
8.1 Operation Modes for Program Memory Write/Verify
When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the µPD75P3036 enters the program memory write/verify
mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below.
Operation mode specification
VPP
VDD
MD0
MD1
MD2
MD3
+12.5 V
+6 V
H
L
H
L
Zero-clear program memory address
L
H
H
H
Write mode
L
L
H
H
Verify mode
H
X
H
H
Program inhibit mode
X: L or H
30
Operation mode
µ PD75P3036
*
8.2 Program Memory Write Procedure
Program memory can be written at high speed using the following procedure.
(1)
Pull unused pins to VSS through resistors. Set the X1 pin low.
(2)
Supply 5 V to the VDD and VPP pins.
(3)
Wait 10 µs.
(4)
Select the zero-clear program memory address mode.
(5)
Supply 6 V to the VDD and 12.5 V to the VPP pins.
(6)
Write data in the 1 ms write mode.
(7)
Select the verify mode. If the data is correct, go to step (8) and if not, repeat steps (6) and (7).
(8)
(X : number of write operations from steps (6) and (7)) x 1 ms additional write.
(9)
Apply four pulses to the X1 pin to increment the program memory address by one.
(10) Repeat steps (6) to (9) until the end address is reached.
(11) Select the zero-clear program memory address mode.
(12) Return the VDD and VPP pins back to 5 V.
(13) Turn off the power.
The following figure shows steps (2) to (9).
X repetitions
Write
VPP
Verify
Additional
write
Address
increment
VPP
VDD
VDD + 1
VDD
VDD
X1
D0/P40-D3/P43
D4/P50-D7/P53
Data input
Data
output
Data input
MD0/P30
MD1/P31
MD2/P32
MD3/P33
31
µ PD75P3036
*
8.3 Program Memory Read Procedure
The µ PD75P3036 can read program memory contents using the following procedure.
(1)
Pull unused pins to VSS through resistors. Set the X1 pin low.
(2)
Supply 5 V to the VDD and VPP pins.
(3)
Wait 10 µ s.
(4)
Select the zero-clear program memory address mode.
(5)
Supply 6 V to the VDD and 12.5 V to the VPP pins.
(6)
Select the verify mode. Apply four clock pulses to the X1 pin. Every four clock pulses will output the data stored
in one address.
(7)
Select the zero-clear program memory address mode.
(8)
Return the VDD and VPP pins back to 5 V.
(9)
Turn off the power.
The following figure shows steps (2) to (7).
VPP
VPP
VDD
VDD + 1
VDD
VDD
X1
D0/P40-D3/P43
D4/P50-D7/P53
Data output
MD0/P30
MD1/P31
“L”
MD2/P32
MD3/P33
32
Data output
µ PD75P3036
*
9. PROGRAM ERASURE (µPD75P3036KK-T ONLY)
The µPD75P3036KK-T is capable of erasing (FFH) the data written in a program memory and rewriting.
To erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400 nm.
Normally, irradiate ultraviolet rays of 254-nm wavelength. The amount of exposure required to completely erase the
programmed data is as follows:
• UV intensity x erasure time : 15 W• s/cm2 or more
• Erasure time : 15 to 20 minutes (when a UV lamp of 12000 µW/cm2 is used. However, a longer time may be
needed because of deterioration in performance of the UV lamp, soiled erasure window, etc.)
When erasing the contents of data, set up the UV lamp within 2.5 cm from the erasure window. Further, if a filter is provided
for a UV lamp, irrradiate the ultraviolet rays after removing the filter.
*
10. OPAQUE FILM ON ERASURE WINDOW (µPD75P3036KK-T ONLY)
To protect from unintentional erasure by rays other than that of the lamp for erasing EPROM contents, and to protect
internal circuit other than EPROM from misoperating due to light radiation, cover the erasure window with an opaque film
when EPROM contents erasure is not performed.
11. ONE-TIME PROM SCREENING
Due to its structure, the one-time PROM versions (µPD75P3036GC-3B9, µPD75P3036GK-BE9) cannot be fully tested
before shipment by NEC. Therefore, NEC recommends that after the required data is written and the PROM is stored
under the temperature and time conditions shown below, the PROM should be verified via a screening.
Storage temperature
Storage time
125 ˚C
24 hours
33
µPD75P3036
* 12.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T A = 25 °C)
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
VDD
–0.3 to +7.0
V
PROM supply voltage
VPP
–0.3 to +13.5
V
–0.3 to V DD +0.3
V
–0.3 to +14
V
Input voltage
VI1
Other than ports 4, 5
VI2
Ports 4, 5
N-ch open drain
Output voltage
VO
High-level output current
IOH
–0.3 to V DD +0.3
V
Per pin
–10
mA
Low-level output current
IOL
Total of all pins
–30
mA
30
mA
Operating ambient
temperature
TA
200
mA
–40 to +85 Note
˚C
Storage temperature
Tstg
–65 to +150
˚C
Per pin
Total of all pins
Note
To drive LCD at 1.8 V ≤ V DD < 2.7 V, TA = –10 to +85 °C
Caution If the absolute maximum ratings of even one of the parameters is exceeded even momentarily,
the quality of the product may be degraded. The absolute maximum ratings are therefore values
which, when exceeded, can cause the product to be damaged. Be sure that these values are
never exceeded when using the product.
Capacitance (T A = 25 °C, V DD = 0 V)
Parameter
Symbol
Conditions
Input capacitance
CIN
f = 1 MHz
Output capacitance
COUT
Unmeasured pins returned to 0 V
I/O capacitance
CIO
34
MIN.
TYP.
MAX.
Unit
15
pF
15
pF
15
pF
µ PD75P3036
Main System Clock Oscillation Circuit Characteristics (T A = –40 to +85 °C, V DD = 1.8 to 5.5 V)
Resonator
Recommended
Constants
Ceramic
resonator
Parameter
Conditions
Oscillation frequency
(fX) Note 1
X1
1.0
TYP.
MAX.
C2
Oscillation
stabilization timeNote 3
VDD
Crystal
resonator
6.0 Note 2 MHz
After V DD has
reached MIN. value of
oscillation voltage
range
Oscillation frequency
(fX) Note 1
4
1.0
6.0 Note 2 MHz
C2
Oscillation
stabilization timeNote 3
VDD = 4.5 to 5.5 V
10
External
clock
ms
30
VDD
Notes 1.
ms
X2
C1
X1
Unit
X2
C1
X1
MIN.
X1 input frequency
(fX) Note 1
1.0
X1 input high-,
low-level widths
(tXH , tXL )
83.3
6.0 Note 2 MHz
X2
500
ns
The oscillation frequency and X1 input frequency shown above indicate characteristics of the
oscillation circuit only. For the instruction execution time, refer to AC Characteristics.
2.
If the oscillation frequency is 4.19 MHz < fX ≤ 6.0 MHz at 1.8 V ≤ V DD < 2.7 V, do not select the processor
clock control register (PCC) = 0011. If PCC = 0011, one machine cycle time is less than 0.95 µ s, falling
short of the rated value of 0.95 µs.
3.
The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been
applied or STOP mode has been released.
Caution When using the main system clock oscillation circuit, wire the portion enclosed in the dotted
line in the above figure as follows to prevent adverse influence due to wiring capacitance:
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring in the vicinity of a line through which a high alternating current flows.
• Always keep the ground point of the capacitor of the oscillation circuit at the same potential
as VDD.
• Do not ground to a power supply pattern through which a high current flows.
• Do not extract signals from the oscillation circuit.
35
µPD75P3036
Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Resonator
Recommended
Constants
Crystal
resonator
Parameter
Conditions
Oscillation frequency
(f XT) Note 1
XT1
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.0
2
s
XT2
R
C3
C4
Oscillation
stabilization timeNote 2
VDD = 4.5 to 5.5 V
10
VDD
External
clock
XT1 input frequency
(f XT) Note 1
XT1
100
kHz
5
15
µs
XT2
XT1 input high-,
low-level widths
(t XTH, tXTL)
Notes 1.
32
The oscillation frequency shown above indicate characteristics of the oscillation circuit only. For the
instruction execution time, refer to AC Characteristics.
2.
The oscillation stabilization time is the time required for oscillation to be stabilized after V DD has been
applied.
Caution When using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line
in the above figure as follows to prevent adverse influence due to wiring capacitance:
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route the wiring in the vicinity of a line through which a high alternating current flows.
• Always keep the ground point of the capacitor of the oscillation circuit at the same potential
as VDD .
• Do not ground to a power supply pattern through which a high current flows.
• Do not extract signals from the oscillation circuit.
The subsystem clock oscillation circuit has a low amplification factor to reduce current
dissipation and is more susceptible to noise than the main system clock oscillation circuit.
Therefore, exercise utmost care in wiring the subsystem clock oscillation circuit.
36
µ PD75P3036
DC Characteristics (TA = –40 to +85 °C, V DD = 1.8 to 5.5 V)
Parameter
Low-level output
Symbol
I OL
current
High-level input
Conditions
VIH1
VIH2
VIH3
Per pin
Low-level output
mA
mA
VDD
V
0.9 V DD
VDD
V
Ports 0, 1, 6, 7, P80, P81,
2.7 V ≤ V DD ≤ 5.5 V
0.8 V DD
VDD
V
RESET
1.8 V ≤ V DD < 2.7 V
0.9 V DD
VDD
V
2.7 V ≤ V DD ≤ 5.5 V
0.7 V DD
13
V
1.8 V ≤ V DD < 2.7 V
0.9 V DD
13
V
Ports 4, 5
N-ch open drain
X1, XT1
Ports 2, 3, 4, 5, P82, P83
VIL2
Ports 0, 1, 6, 7, P80, P81,
RESET
VOH
15
120
0.7 V DD
VIL1
voltage
Unit
2.7 V ≤ V DD ≤ 5.5 V
VIH4
VIL3
MAX.
1.8 V ≤ V DD < 2.7 V
Ports 2, 3, P82, P83
voltage
High-level output
TYP.
Total of all pins
voltage
Low-level input
MIN.
V DD –0.1
VDD
V
2.7 V ≤ V DD ≤ 5.5 V
0
0.3 V DD
V
1.8 V ≤ V DD < 2.7 V
0
0.1 V DD
V
2.7 V ≤ V DD ≤ 5.5 V
0
0.2 V DD
V
1.8 V ≤ V DD < 2.7 V
0
0.1 V DD
V
0
0.1
V
X1, XT1
SCK, SO, ports 2, 3, 6, 7, 8, BP0 to BP7
V DD–0.5
V
I OH = –1 mA
VOL1
voltage
SCK, SO, ports 2 to 8,
I OL = 15 mA
BP0 to BP7
VDD = 4.5 to 5.5 V
0.2
I OL = 1.6 mA
VOL2
SB0, SB1
I LIH1
VIN = V DD
2.0
V
0.4
V
0.2 V DD
V
Pins other than X1, XT1
3
µA
N-ch open drain
Pull-up resistor ≥ 1 kΩ
High-level input
X1, XT1
20
µA
I LIH3
VIN = 13 V
Ports 4, 5 (N-ch open drain)
20
µA
Low-level input
I LIL1
VIN = 0 V
Pins other than ports 4, 5, X1, XT1
leakage current
I LIL2
leakage current
I LIH2
X1, XT1
Ports 4, 5 (N-ch open drain)
–3
µA
–20
µA
–3
µA
When input instruction is not executed
Ports 4, 5 (N-ch
open drain)
When input instruction is executed
I LIL3
High-level output
µA
–10
–27
µA
VDD = 3 V
–3
–8
µA
3
µA
I LOH1
VOUT = VDD
I LOH2
VOUT = 13 V Ports 4, 5 (N-ch open drain)
20
µA
I LOL
VOUT = 0 V
–3
µA
RL1
VIN = 0 V
200
kΩ
leakage current
Low-level output
–30
VDD = 5 V
SCK, SO/SB0, SB1, ports 2, 3, 6, 7, 8,
BP0 to BP7
leakage current
Internal pull-up
Ports 0 to 3, 6 to 8 (except pin P00)
50
100
resistor
37
µPD75P3036
DC Characteristics (TA = –40 to +85 °C, V DD = 1.8 to 5.5 V)
Parameter
LCD drive voltage
Symbol
VLCD
Conditions
VAC0 = 0
MIN.
TYP.
MAX.
Unit
–40 to + 85 ˚C
2.7
VDD
V
–10 to + 85 ˚C
2.2
VDD
V
VAC0 = 1
1.8
VAC current Note 1
I VAC
VAC0 = 1, V DD = 2.0 V ±10 %
LCD output voltage
VODC
I O = ±1.0 µ A
VDD
V
4
µA
0
±0.2
V
0
±0.2
V
1
VLCD0 = VLCD
VLCD1 = VLCD × 2/3
deviationNote 2
VLCD2 = VLCD × 1/3
(common)
LCD output voltage
VODS
I O = ±0.5 µ A
I DD1
6.00 MHz Note 4
crystal
oscillation
C1 = C2
= 22 pF
1.8 V ≤ V LCD ≤ VDDNote 1
deviationNote 2
(segment)
Supply currentNotes 1, 3
I DD2
I DD1
I DD2
I DD3
3.5
10.5
mA
VDD = 3.0 V ±10 % Note 6
0.86
2.5
mA
HALT
VDD = 5.0 V ±10 %
0.9
2.7
mA
mode
VDD = 3.0 V ±10 %
0.5
1.0
mA
VDD = 5.0 V ±10
% Note 5
2.7
8.1
mA
crystal
oscillation
C1 = C2
= 22 pF
VDD = 3.0 V ±10 % Note 6
0.33
1.0
mA
32.768
kHz Note 7
crystal
4.19
MHz Note 4
oscillation
I DD4
I DD5
VDD = 5.0 V ±10 % Note 5
XT1 =
0V
Note 10
HALT
VDD = 5.0 V ±10 %
0.7
2.0
mA
mode
VDD = 3.0 V ±10 %
0.3
0.9
mA
Low-
VDD = 3.0 V ±10 %
45
135
µA
voltage
VDD = 2.0 V ±10 %
22
66
µA
mode
VDD = 3.0 V, T A = 25 ˚C
45
90
µA
Low current
dissipation
mode Note 9
VDD = 3.0 V ±10 %
43
129
µA
43
86
µA
HALT
Low-
V DD = 3.0 V ±10 %
8.5
25
µA
mode
voltage
V DD = 2.0 V ±10 %
Note 8
VDD = 3.0 V, T A = 25 ˚C
3.0
9.0
µA
mode Note 8 V DD = 3.0 V, TA = 25 ˚C
8.5
17
µA
Low current
dissipation V DD = 3.0 V ±10 %
mode Note 9
V DD = 3.0 V, TA = 25 ˚C
4.6
13.8
µA
4.6
9.2
µA
VDD = 5.0 V ±10 %
0.05
10
µA
VDD = 3.0 V ±10 %
0.02
5.0
µA
0.02
3.0
µA
STOP mode
Notes 1.
TA = 25 ˚C
Clear VAC0 to 0 in the low current dissipation mode and STOP mode. When VAC0 is set to 1, the current
increases by about 1 µ A.
2.
Voltage deviation is the difference between the ideal values (VLCDn; n = 0, 1, 2) of the segment and
common outputs and the output voltage.
3.
The current flowing through the internal pull-up resistor is not included.
4.
Including the case when the subsystem clock oscillates.
5.
When the device operates in high-speed mode with the processor clock control register (PCC) set to
0011.
6.
When the device operates in low-speed mode with PCC set to 0000.
7.
When the device operates on the subsystem clock, with the system clock control register (SCC) set
to 1001 and oscillation of the main system clock stopped.
8.
When the sub-oscillation circuit control register (SOS) is set to 0000.
9.
When SOS is set to 0010.
10. When SOS is set to 00×1, and the feedback resistor of the sub-oscillation circuit is not used (× : don't
care).
38
µ PD75P3036
AC Characteristics (TA = –40 to +85 °C, V DD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
0.67
64
µs
(minimum instruction
main system clock
0.95
64
µs
execution time = 1
Operates with
114
125
µs
machine cycle)
subsystem clock
0
1.0
MHz
0
275
kHz
CPU clock cycle
timeNote 1
TI0, TI1, TI2 input frequency
TI0, TI1, TI2 high-, low-level
t CY
f TI
tTIH, tTIL
VDD = 2.7 to 5.5 V
Operates with
VDD = 2.7 to 5.5 V
0.48
µs
1.8
µs
IM02 = 0
Note 2
µs
IM02 = 1
10
µs
INT1, 2, 4
10
µs
KR0 to KR7
10
µs
10
µs
VDD = 2.7 to 5.5 V
widths
Interrupt input high-,
tINTH, tINTL
INT0
low-level widths
RESET low-level width
122
t RSL
tCY vs VDD
Notes 1.
The cycle time of the CPU clock (Φ) is
(with main system clock)
determined by the oscillation frequency
of the connected resonator (and ex-
64
60
ternal clock), the system clock control
register (SCC), and processor clock
6
control register (PCC).
5
Operation guaranteed range
ply voltage V DD vs. cycle time tCY characteristics when the device operates
with the main system clock.
2.
2tCY or 128/f X depending on the setting
of the interrupt mode register (IM0).
Cycle time tCY [ µ s]
The figure on the right shows the sup-
4
3
2
1
0.5
0
1
2
3
4
5
6
Supply voltage VDD [V]
39
µPD75P3036
Serial transfer operation
2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high-, low-level widths
Symbol
t KCY1
t KL1 ,
Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
t KH1
SINote 1
setup time (to SCK ↑)
SINote 1 hold time
t SIK1
t KSI1
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
(from SCK ↑)
SCK ↓ → SONote 1 output
t KSO1
delay time
Notes 1.
RL = 1 kΩ,
Note 2
VDD = 2.7 to 5.5 V
CL = 100 pF
MIN.
TYP.
MAX.
Unit
1300
ns
3800
ns
tKCY1/2–50
ns
tKCY1/2–150
ns
150
ns
500
ns
400
ns
600
ns
0
250
ns
0
1000
ns
Read as SB0 or SB1 when using the 2-wire serial I/O mode.
R L and CL respectively indicate the load resistance and load capacitance of the SO output line.
2.
2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (TA = –40 to +85 °C, V DD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
SCK cycle time
t KCY2
VDD = 2.7 to 5.5 V
SCK high-, low-level widths
t KL2 ,
VDD = 2.7 to 5.5 V
SINote 1 setup time (to SCK ↑)
t SIK2
VDD = 2.7 to 5.5 V
SINote 1 hold time
t KSI2
VDD = 2.7 to 5.5 V
t KSO2
RL = 1 kΩ,
t KH2
(from SCK ↑)
SCK ↓ → SONote 1 output
delay time
Notes 1.
2.
40
MIN.
TYP.
MAX.
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
400
ns
600
Note 2
VDD = 2.7 to 5.5 V
CL = 100 pF
Unit
800
ns
0
300
ns
0
1000
ns
Read as SB0 or SB1 when using the 2-wire serial I/O mode.
R L and CL respectively indicate the load resistance and load capacitance of the SO output line.
µ PD75P3036
SBI mode (SCK ··· internal clock output (master)): (TA = –40 to +85 °C, V DD = 1.8 to 5.5 V)
Parameter
SCK cycle time
SCK high-, low-level widths
Symbol
t KCY3
t KL3,
Conditions
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
t KH3
SB0, 1 setup time
t SIK3
VDD = 2.7 to 5.5 V
(to SCK ↑)
SB0, 1 hold time (from SCK ↑)
t KSI3
SCK ↓ → SB0, 1 output
t KSO3
delay time
MIN.
TYP.
MAX.
1300
ns
3800
ns
tKCY3/2–50
ns
tKCY3/2–150
ns
150
ns
500
ns
t KCY3/2
RL = 1 kΩ,
Note
VDD = 2.7 to 5.5 V
CL = 100 pF
Unit
ns
0
250
ns
0
1000
ns
SCK ↑ → SB0, 1 ↓
t KSB
t KCY3
ns
SB0, 1 ↓ → SCK ↓
t SBK
t KCY3
ns
SB0, 1 low-level width
t SBL
t KCY3
ns
SB0, 1 high-level width
t SBH
t KCY3
ns
Note
RL and C L respectively indicate the load resistance and load capacitance of the SB0, 1 output line.
SBI mode (SCK ··· external clock input (slave)): (TA = –40 to +85 °C, V DD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
SCK cycle time
t KCY4
VDD = 2.7 to 5.5 V
SCK high-, low-level widths
t KL4,
VDD = 2.7 to 5.5 V
t KH4
SB0, 1 setup time
t SIK4
VDD = 2.7 to 5.5 V
(to SCK ↑)
SB0, 1 hold time (from SCK ↑)
SCK ↓ → SB0, 1 output
t KSI4
t KSO4
delay time
RL = 1 kΩ,
CL = 100 pF
Note
VDD = 2.7 to 5.5 V
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
150
ns
t KCY4/2
ns
0
300
ns
0
1000
ns
SCK ↑ → SB0, 1 ↓
t KSB
t KCY4
ns
SB0, 1 ↓ → SCK ↓
t SBK
t KCY4
ns
SB0, 1 low-level width
t SBL
t KCY4
ns
SB0, 1 high-level width
t SBH
t KCY4
ns
Note
RL and C L respectively indicate the load resistance and load capacitance of the SB0, 1 output line.
41
µPD75P3036
A/D Converter Characteristics (T A = –40 to +85 °C, V DD = 1.8 to 5.5 V, 1.8 V ≤ AV REF ≤ V DD)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
bit
2.7 V ≤ V DD ≤ 5.5 V
1.5
LSB
1.8 V ≤ V DD < 2.7 V
3
LSB
Resolution
Absolute accuracy
Note 1
VDD = AVREF
VDD ≠ AV REF
Conversion time
t CONV
Note 2
Sampling time
t SAMP
Note 3
Analog input voltage
VIAN
AV SS
Analog input impedance
RAN
1000
AVREF current
I REF
0.25
Notes 1.
2.
3
LSB
168/f X
µs
44/fX
µs
AVREF
V
MΩ
2.0
mA
Absolute accuracy excluding quantization error (±1/2LSB)
Time until end of conversion (EOC = 1) after execution of conversion start instruction (40.1 µ s: fX =
4.19 MHz).
3.
42
Time until end of sampling after execution of conversion start instruction (10.5 µ s: fX = 4.19 MHz).
µ PD75P3036
AC timing test points (except X1 and XT1 inputs)
VIH (MIN.)
VIH (MIN.)
VIL (MAX.)
VIL (MAX.)
VOH (MIN.)
VOH (MIN.)
VOL (MAX.)
VOL (MAX.)
Clock timing
1/fX
tXL
tXH
VDD – 0.1 V
X1 input
0.1 V
1/fXT
tXTL
tXTH
VDD – 0.1 V
XT1 input
0.1 V
TI0, TI1, TI2 timing
1/fTI
tTIL
tTIH
TI0, TI1, TI2
43
µPD75P3036
Serial transfer timing
3-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
tKSI1, 2
Input data
SI
tKSO1, 2
Output data
SO
2-wire serial I/O mode
tKCY1, 2
tKL1, 2
tKH1, 2
SCK
tSIK1, 2
SB0, 1
tKSO1, 2
44
tKSI1, 2
µ PD75P3036
Serial transfer timing
Bus release signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSBL
tSBH
tSIK3, 4
tSBK
tKSI3, 4
SB0, 1
tKSO3, 4
Command signal transfer
tKCY3, 4
tKL3, 4
tKH3, 4
SCK
tKSB
tSIK3, 4
tSBK
tKSI3, 4
SB0, 1
tKSO3, 4
Interrupt input timing
tINTL
tINTH
INT0, 1, 2, 4
KR0-7
RESET input timing
tRSL
RESET
45
µPD75P3036
Data retention characteristics of data memory in STOP mode and at low supply voltage
(TA = –40 to +85 °C)
Parameter
Symbol
Release signal setup time
Conditions
Oscillation stabilization
TYP.
MAX.
tWAIT
2 15/f X
ms
Note 2
ms
Released by RESET
Released by interrupt request
Unit
µs
0
wait time Note 1
Notes 1.
MIN.
tSREL
The oscillation stabilization wait time is the time during which the CPU stops operating to prevent
unstable operation when oscillation is started.
2.
Set by the basic interval timer mode register (BTM). (Refer to the table below.)
Wait Time
BTM3
BTM2
BTM1
BTM0
–
0
0
0
2 20/f X (approx. 250 ms)
2 20/f X (approx. 175 ms)
–
0
1
1
2 17/f X (approx. 31.3 ms)
2 17/f X (approx. 21.8 ms)
–
1
0
1
2 15/f X (approx. 7.81 ms)
2 15/f X (approx. 5.46 ms)
1
2 13/f X
2 13/f X (approx. 1.37 ms)
f X = 4.19 MHz
–
1
1
f X = 6.0 MHz
(approx. 1.95 ms)
Data retention timing (when STOP mode released by RESET)
Internal reset operation
Oscillation stabilization wait time
STOP mode
Operation mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data retention timing (standby release signal: when STOP mode released by interrupt signal)
Oscillation stabilization wait time
STOP mode
Operation mode
Data retention mode
VDDDR
VDD
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
46
µ PD75P3036
DC Programming Characteristics (T A = 25 ± 5 ˚C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, V SS = 0 V)
Parameter
Symbol
High-level input voltage
Conditions
MIN.
TYP.
MAX.
Unit
VIH1
Except X1, X2
0.7 VDD
VDD
V
VIH2
X1, X2
VDD –0.5
VDD
V
VIL1
Except X1, X2
0
0.3 VDD
V
VIL2
X1, X2
0
0.4
V
Input leakage current
ILI
VIN = VIL or VIH
10
µA
High-level output voltage
VOH
IOH = –1 mA
Low-level output voltage
VOL
IOL = 1.6 mA
VDD supply current
IDD
VPP supply current
IPP
Low-level input voltage
Cautions 1.
2.
VDD –1.0
V
MD0 = VIL, MD1 = VIH
0.4
V
30
mA
30
mA
Ensure that VPP does not exceed +13.5 V including overshoot.
VDD must be applied before V PP, and cut after V PP.
AC Programming Characteristics (T A = 25 ± 5 ˚C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, V SS = 0 V)
Parameter
Symbol
Note 1
Conditions
MIN.
TYP.
MAX.
Unit
tAS
tAS
2
µs
MD1 setup time (to MD0↓)
tM1S
tOES
2
µs
Data setup time (to MD0↓)
tDS
tDS
2
µs
tAH
tAH
2
µs
tDH
tDH
2
µs
MD0↑→Data output float delay time
tDF
tDF
0
VPP setup time (to MD3↑)
tVPS
tVPS
2
µs
VDD setup time (to MD3↑)
tVDS
tVCS
2
µs
Initial program pulse width
tPW
tPW
0.95
Additional program pulse width
tOPW
tOPW
0.95
MD0 setup time (to MD1↑)
tM0S
tCES
2
MD0↓→Data output delay time
tDV
tDV
MD0 = MD1 = VIL
MD1 hold time (from MD0↑)
tM1H
tOEH
tM1H + tM1R ≥ 50 µs
MD1 recovery time (from MD0↓)
tM1R
tOR
Program counter reset time
tPCR
X1 input high-, low-level widths
X1 input frequency
Address setup time
Note 2
Note 2
Address hold time
(to MD0↓)
(from MD0↑)
Data hold time (from MD0↑)
130
1.0
ns
1.05
ms
21.0
ms
µs
1
µs
2
µs
2
µs
—
10
µs
tXH, tXL
—
0.125
µs
fX
—
4.19
MHz
Initial mode setting time
tI
—
2
µs
MD3 setup time (to MD1↑)
tM3S
—
2
µs
MD3 hold time (from MD1↓)
tM3H
—
2
µs
MD3 setup time (to MD0↓)
tM3SR
—
2
µs
Data output delay time from address Note 2 tDAD
Data output hold time from address
Note 2
tHAD
Program memory read
tACC
Program memory read
tOH
Program memory read
0
2
MD3 hold time (from MD0↑)
tM3HR
—
Program memory read
MD3↓→Data output float delay time
tDFR
—
Program memory read
Notes 1.
2.
2
µs
130
µs
µs
2
µs
Symbol of corresponding µ PD27C256A
The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected
to a pin.
47
µPD75P3036
Program Memory Write Timing
tVPS
VPP
VPP
VDD
VDD
VDD+1
VDD
tVDS
tXH
X1
tXL
D0/P40-D3/P43
D4/P50-D7/P53
Data Output
Data Input
Data Input
tDS
tI
tDS
tDH
tDV
Data Input
tDH
tDF
tAH
tAS
MD0
tPW
tM1R
tM0S
tOPW
MD1
tPCR
tM1S
tM1H
MD2
tM3S
tM3H
MD3
Program Memory Read Timing
tVPS
VPP
VPP
VDD
tVDS
VDD+1
VDD
tXH
VDD
X1
tXL
tDAD
tHAD
D0/P40-D3/P43
D4/P50-D7/P53
Data Output
tDV
tI
MD1
tPCR
MD2
tM3SR
48
tDFR
tM3HR
MD0
MD3
Data Output
µ PD75P3036
13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY)
IDD vs. V DD (main system clock: 6.0-MHz crystal resonator)
(TA = 25 °C )
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
Main system clock
HALT mode + 32 kHz oscillation
1.0
0.5
Supply current IDD (mA)
*
0.1
Subsystem clock operation mode
(SOS.1 = 0)
0.05
Subsystem clock HALT mode
(SOS.1 = 0)
Main system clock STOP mode
+ 32 kHz oscillation (SOS.1 = 0)
Subsystem clock HALT mode
(SOS.1 = 1)
Main system clock STOP mode
+ 32 kHz oscillation (SOS.1 = 1)
0.01
0.005
X1
X2 XT1 XT2
Crystal resonator
Crystal resonator
6.0 MHz
32.768 kHz 330 kΩ
22 pF
22 pF
22 pF
VDD
VDD
22 pF
0.001
0
1
2
3
4
5
6
7
8
Supply voltage VDD (V)
49
µPD75P3036
IDD vs. V DD (main system clock: 4.19-MHz crystal resonator)
(TA = 25 °C)
10
5.0
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
1.0
Main system clock
HALT mode + 32 kHz oscillation
Supply current IDD (mA)
0.5
0.1
Subsystem clock operation mode
(SOS.1 = 0)
0.05
Subsystem clock HALT mode
(SOS.1 = 0)
Main system clock STOP mode
+ 32 kHz oscillation (SOS.1 = 0)
Subsystem clock HALT mode
(SOS.1 = 1)
Main system clock STOP mode
+ 32 kHz oscillation (SOS.1 = 1)
0.01
0.005
X1
X2 XT1 XT2
Crystal resonator
Crystal resonator
4.19 MHz
32.768 kHz 330 kΩ
22 pF
22 pF
22 pF
VDD
VDD
22 pF
0.001
0
1
2
3
4
Supply voltage VDD (V)
50
5
6
7
8
µ PD75P3036
14. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14×14)
A
B
60
61
41
40
detail of lead end
C D
S
R
Q
21
20
80
1
F
J
G
H
I
M
K
P
M
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
17.2±0.4
0.677±0.016
B
14.0±0.2
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.2±0.4
0.677±0.016
F
0.825
0.032
G
0.825
0.032
H
0.30±0.10
0.012 +0.004
–0.005
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.6±0.2
L
0.8±0.2
0.063±0.008
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.1±0.1
0.004±0.004
R
5°±5°
5°±5°
S
3.0 MAX.
0.119 MAX.
S80GC-65-3B9-4
51
µ PD75P3036
80 PIN PLASTIC TQFP (FINE PITCH) (
12)
A
B
60
41
61
40
21
F
80
1
20
H
I
M
J
K
M
P
G
R
Q
S
D
C
detail of lead end
N
L
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
14.0±0.2
INCHES
0.551 +0.009
–0.008
B
12.0±0.2
0.472 +0.009
–0.008
C
12.0±0.2
0.472 +0.009
–0.008
D
14.0±0.2
0.551 +0.009
–0.008
F
1.25
G
1.25
H
0.22 +0.05
–0.04
0.049
0.049
0.009±0.002
I
0.10
J
0.5 (T.P.)
K
1.0±0.2
0.039 +0.009
–0.008
L
0.5±0.2
0.020 +0.008
–0.009
M
0.145 +0.055
–0.045 0.006±0.002
N
0.10
P
1.05
Q
0.05±0.05
R
5°±5°
S
1.27 MAX.
0.004
0.020 (T.P.)
0.004
0.041
0.002±0.002
5°±5°
0.050 MAX.
P80GK-50-BE9-4
52
µ PD75P3036
80 PIN CERAMIC WQFN
A
Q
K
B
T
D
80
S
W
C
U1
H
U
1
I M
R
G
J
F
*
Z
X80KW-65A-1
NOTE
Each lead centerline is located within 0.06
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
14.0 ± 0.2
0.551 ± 0.008
B
13.6
0.535
C
13.6
0.535
D
14.0 ± 0.2
0.551 ± 0.008
F
1.84
0.072
G
3.6 MAX.
0.142 MAX.
H
0.45 ± 0.10
0.018+0.004
–0.005
I
0.06
0.003
J
0.65 (T.P.)
0.024 (T.P.)
K
1.0 ± 0.15
0.039+0.007
–0.006
Q
C 0.3
C 0.012
R
0.825
0.032
S
0.825
0.032
T
R 2.0
R 0.079
U
9.0
0.354
U1
2.1
0.083
W
0.75 ± 0.15
0.030+0.006
–0.007
Z
0.10
0.004
53
µ PD75P3036
* 15. RECOMMENDED SOLDERING CONDITIONS
Solder the µ PD75P3036 under the following recommended conditions.
For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device
Mounting Technology Manual (C10535E).
For the soldering methods and conditions other than those recommended, consult NEC.
Table 15-1. Soldering Conditions of Surface Mount Type
(1) µ PD75P3036GC-3B9: 80-pin plastic QFP (14 × 14 mm)
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235 ˚C, Reflow time: 30 seconds or below
(210 ˚C or higher), Number of reflow processes: 3 max.
IR35-00-3
VPS
Package peak temperature: 215 ˚C, Reflow time: 40 seconds or below
(200 ˚C or higher), Number of reflow processes: 3 max.
VP15-00-3
Wave soldering
Solder temperature: 260 ˚C or below, Flow time: 10 seconds or below,
Number of flow processes: 1
Preheating temperature: 120 ˚C or below (package surface temperature)
WS60-00-1
Pin partial heating
Pin temperature: 300 ˚C or below, Time: 3 seconds or below (per side of device)
—
Caution Do not use two or more soldering methods in combination (except the pin partial heating method).
(2) µ PD75P3036GK-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235 ˚C, Reflow time: 30 seconds or below (210 ˚C IR35-107-3
or higher), Number of reflow processes: 3 max., Exposure limit: 7 days Note
(After that, prebaking is necessary at 125 ˚C for 10 hours.)
VPS
Package peak temperature: 215 ˚C, Reflow time: 40 seconds or below (200 ˚C VP15-107-3
or higher), Number of reflow processes: 3 max., Exposure limit: 7 days Note
(After that, prebaking is necessary at 125 ˚C for 10 hours.)
Wave soldering
Solder temperature: 260 ˚C or below, Flow time: 10 seconds or below,
WS60-107-1
Number of flow processes: 1,
Preheating temperature: 120 ˚C or below (package surface temperature)
Exposure limit: 7 days Note (After that, prebaking is necessary at 125 ˚C for 10
hours.)
Pin partial heating
Pin temperature: 300 ˚C or below, Time: 3 seconds or below (per side of device)
—
Note The number of days for storage after the dry pack has been opened. The storage conditions are 25 ˚C, 65 % RH max.
Caution Do not use two or more soldering methods in combination (except the pin partial heating method).
54
µ PD75P3036
APPENDIX A. FUNCTION LIST OF µPD75336, 753036, AND 75P3036
µ PD75336
ROM (bytes)
16256
Mask ROM
RAM (x 4 bits)
768
µPD753036
16384
Mask ROM
Mk I, Mk II mode selection function
No
Yes
Instruction set
75X High-End
75XL
I/O ports
Total
44
CMOS input
8
CMOS I/O
20 (4 of which can directly drive LEDs)
CMOS output
8 (also used as segment pins)
N-ch open-drain I/O
8 (can directly drive LEDs, medium-voltage port)
µ PD75P3036
16384
One-time PROM, EPROM
Mask options
Yes
Timers
4 channels:
• 8-bit timer/
event counter ........ 2 chs
• Basic interval timer ... 1 ch
• Watch timer .......... 1 ch
5 channels:
• 8-bit timer/event counters ........................ 3 chs
(16-bit timer/event counter, carrier generator, timer with gate)
• Basic interval timer/watchdog timer ......... 1 ch
• Watch timer ............................................. 1 ch
Vectored interrupt
• External : 3
• Internal : 4
• External : 3
• Internal : 5
Test input
• External : 1
• Internal : 1
• External : 1
• Internal : 1
Power supply voltage
VDD = 2.7 to 6.0 V
VDD = 1.8 to 5.5 V
Instruction
execution time
When main system
clock is selected
0.95, 1.91, 3.81, or 15.3 µ s
(@ 4.19 MHz)
• 0.95, 1.91, 3.81, or 15.3 µs (@ 4.19 MHz)
• 0.67, 1.33, 2.67, or 10.7 µs (@ 6.0 MHz)
When subsystem
clock is selected
122 µs (@ 32.768 kHz)
Package
No
80-pin plastic QFP (14 x 14 mm)
80-pin plastic TQFP (fine pitch) (12 x 12 mm)
80-pin plastic QFP
(14 x 14 mm)
80-pin plastic TQFP
(fine pitch) (12 x 12 mm)
80-pin ceramic WQFN
55
µ PD75P3036
APPENDIX B. DEVELOPMENT TOOLS
The following development tools have been provided for system development using the µ PD75P3036. Use the common
relocatable assembler for the series together with the device file according to the model.
RA75X relocatable assembler
Host machine
Part No. (name)
OS
PC-9800 Series
MS-DOS
Supply medium
TM
Ver.3.30 to
Ver.6.2Note
*
IBM PC/ATTM
or compatible
Device file
Refer to "OS for
IBM PCs"
3.5-inch 2HD
µS5A13RA75X
5-inch 2HD
µS5A10RA75X
3.5-inch 2HC
µS7B13RA75X
5-inch 2HC
µS7B10RA75X
Host machine
PC-9800 Series
Part No. (name)
OS
Supply medium
MS-DOS
3.5-inch 2HD
µS5A13DF753036
5-inch 2HD
µS5A10DF753036
3.5-inch 2HC
µS7B13DF753036
5-inch 2HC
µS7B10DF753036
Ver.3.30 to
Ver.6.2Note
*
IBM PC/AT
or compatible
Refer to "OS for
IBM PCs"
Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.
Remark
Operations of the assembler and device file are guaranteed only when using the host machine and OS
described above.
56
µ PD75P3036
PROM Write Tools
Hardware
*
Software
PG-1500
This is a PROM programmer that can program single-chip microcontroller with PROM in stand
alone mode or under control of host machine when connected with supplied accessory board
and optional programmer adapter.
It can also program typical PROMs in capacities ranging from 256 K to 4 Mbits.
PA-75P328GC
This is a PROM programmer adapter for the µPD75P3036GC used by connecting to a PG-1500.
PA-75P336GK
This is a PROM programmer adapter for the µ PD75P3036GK used by connecting to a PG-1500.
PA-75P3036KK-T Note 1
This is a PROM programmer adapter for the µPD75P3036KK-T used by connecting to a PG1500.
PG-1500 controller
Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on
host machine.
Host machine
PC-9800 Series
Part No. (name)
OS
Supply medium
MS-DOS
3.5-inch 2HD
µ S5A13PG1500
5-inch 2HD
µ S5A10PG1500
Ver.3.30 to
Ver.6.2Note 2
*
IBM PC/AT
Refer to "OS for
3.5-inch 2HD
µ S7B13PG1500
or compatible
IBM PCs"
5-inch 2HC
µ S7B10PG1500
Notes 1. Under development
2. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.
Remark
Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.
57
µ PD75P3036
Debugging Tools
In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P3036.
Various system configurations using these in-circuit emulators are listed below.
Hardware
IE-75000-RNote 1
The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems using the 75X or 75XL Series products.
For development of the µPD75P3036, the IE-75000-R is used with optional emulation board (IE75300-R-EM) and emulation probe (EP-753036GC-R or EP-753036GK-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.
The IE-75000-R includes a connected emulation board (IE-75000-R-EM).
IE-75001-R
The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems using the 75X or 75XL Series products.
The IE-75001-R is used with optional emulation board (IE-75300-R-EM) and emulation probe
(EP-753036GC-R or EP-753036GK-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.
IE-75300-R-EMNote 2
This is an emulation board for evaluating application systems using the µ PD75P3036.
It is used in combination with the IE-75000-R or IE-75001-R.
EP-75336GC-R
This is an emulation probe for the µ PD75P3036GC.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
EV-9200GC-80
EP-75336GK-R
EV-9500GK-80
Software
IE control program
It includes an 80-pin conversion socket (EV-9200GC-80) to facilitate connections with target
system.
This is an emulation probe for the µ PD75P3036GK.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
It includes an 80-pin conversion adapter (EV-9500GK-80) to facilitate connections with target
system.
This program can control the IE-75000-R or IE-75001-R on a host machine when connected to
the IE-75000-R or IE-75001-R via an RS-232-C and Centronics interface.
Host machine
PC-9800 Series
Part No. (name)
OS
Supply medium
MS-DOS
3.5-inch 2HD
µS5A13IE75X
5-inch 2HD
µS5A10IE75X
Ver.3.30 to
Ver.6.2Note 3
*
IBM PC/AT
Refer to "OS for
3.5-inch 2HC
µS7B13IE75X
or compatible
IBM PCs"
5-inch 2HC
µS7B10IE75X
Notes 1. This is a maintenance product.
2. The IE-75300-R-EM is sold separately.
3. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.
Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described
above.
2. The µPD753036 and 75P3036 are commonly referred to as the µPD753036 Subseries.
58
µ PD75P3036
OS for IBM PCs
The following operating systems for the IBM PC are supported.
OS
TM
*
*
PC DOS
Version
Ver.5.02 to Ver.6.3
J6.1/V to J6.3/V
MS-DOS
Ver.5.0 to Ver.6.22
5.0/V to 6.2/V
IBM DOSTM
Caution
J5.02/V
Ver. 5.0 or later includes a task swapping function, but this software is not able to use that function.
59
µ PD75P3036
* APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are
not marked as such.
Documents Related to Device
Document
Document No.
Japanese
English
µPD75P3036 Data Sheet
U11575J
U11575E (this document)
µPD753036 Data Sheet
U11353J
Planned
µPD753036 User’s Manual
U10201J
U10201E
µPD753036 Instruction Table
IEM-5063
75XL Series Selection Guide
U10453J
—
U10453E
Documents Related to Development Tools
Document
Document No.
Japanese
Hardware IE-75000-R/IE-75001-R User’s Manual
Software
English
EEU-846
EEU-1416
IE-75300-R-EM User’s Manual
U11354J
EEU-1493
EP-75336GC/GK-R User’s Manual
U10644J
U10644E
PG-1500 User’s Manual
EEU-651
EEU-1335
RA75X Assembler Package
Operation
EEU-731
EEU-1346
User’s Manual
Language
EEU-730
EEU-1363
PG-1500 Controller User’s Manual
PC-9800 Series
EEU-704
EEU-1291
EEU-5008
U10540E
(MS-DOS) base
IBM PC Series
(PC DOS) base
Other Related Documents
Document
Document No.
Japanese
English
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Grades on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983J
C10983E
Electrostatic Discharge (ESD) Test
MEM-539
Guide to Quality Assurance for Semiconductor Devices
MEI-603
Microcomputer – Related Product Guide – Third Party Products –
MEI-604
Caution
MEI-1202
—
The related documents listed above are subject to change without notice. Be sure to use the latest
documents for designing, etc.
60
—
µ PD75P3036
[MEMO]
61
µ PD75P3036
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS devices
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
62
µ PD75P3036
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
63
µ PD75P3036
MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC DOS, and PC/AT are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
64